CN1133207C - 用于集成电路芯片筛选测试组件的电路板及方法 - Google Patents

用于集成电路芯片筛选测试组件的电路板及方法 Download PDF

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Publication number
CN1133207C
CN1133207C CN97114368A CN97114368A CN1133207C CN 1133207 C CN1133207 C CN 1133207C CN 97114368 A CN97114368 A CN 97114368A CN 97114368 A CN97114368 A CN 97114368A CN 1133207 C CN1133207 C CN 1133207C
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circuit board
chip
integrated circuit
metal wire
temperature
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CN97114368A
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CN1197287A (zh
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朴桂灿
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Priority claimed from KR1019960064251A external-priority patent/KR100214853B1/ko
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Publication of CN1197287A publication Critical patent/CN1197287A/zh
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Abstract

一种用于筛选测试集成电路芯片的电路板和使用该电路板制造已知合格管芯的方法。该电路板包括：设有多个垂直贯通孔的本体，该本体为有机材料或者陶瓷材料；在该本体的一侧表面上形成的多根金属线；多个插脚，分别插入所述孔中而与该金属线电连接。并且，已知合格管芯的制造方法包括，在把集成电路芯片附着于所述电路板上，而使得集成电路芯片的焊盘与该电路板的金属线电连接的的状态下，进行筛选测试的步骤；进行筛选测试后，使集成电路芯片与电路板分离。

Description

用于集成电路芯片筛选测试组件 的电路板及方法
技术领域
本发明涉及一种半导体装置，更详细地说，涉及一种用于筛选测试(burn-in test，或称为筛选测试)集成电路芯片的电路板和使用该电路板的已知合格管芯(known good die)的制造方法。
背景技术
一般说来，在被分配可使用芯片之前，为了确定芯片的可靠性，对标准集成电路芯片做各种测试。简单地说，有两种重要的可靠性测试，其中之一就是把全部输入端子和输出端子连接在测试信号发生器上，证实输入或输出于这些端子的信号之间的传输特性。另一试验是把规定的芯片暴露在高于正常的操作温度和电压的过分的应力条件下，以决定其寿命并检测其缺陷。
例如，对DRAM的筛选测试，被评价为用来确定像存储单元和信号线这样的存储电路器件的可靠性的有效方法。在筛选测试过程中，若在DRAM芯片上存在缺陷，则发生MOS晶体管的栅氧化膜的破坏和多层导电层之间的短路。有缺陷的芯片就作为不合格品被废弃，而选择没有缺陷的芯片作为已知合格管芯。
通过这样的筛选测试，被确定为不合格产品的集成电路芯片通常约为5～10％。但是，由于这样的不合格产品是已被封装的产品，所以，用于制造已知合格管芯的现有技术就存在着把使用不必要的许多材料和且需要工程费用投资的缺点。
发明内容
本发明的目的在于，提供一种集成电路芯片的筛选测试电路板，可在还没有封装的状态下进行筛选测试，从而能够防止不必要的材料使用和工程费用的投资。
本发明的另一个目的在于，提供一种已知合格管芯的制造方法，可在还没有封装的状态下进行筛选测试，从而能够防止不必要的材料使用和工程费用的投资。
为实现上述目的，本发明提供的一种用于筛选测试集成电路芯片的电路板包括：设有多个垂直贯通孔的本体，该本体为有机材料或者陶瓷材料；在所述本体的一侧表面上形成且与所述集成电路芯片的焊盘电连接的多根金属线；以及多个插脚，分别插入所述孔中而与所述金属线电连接，并从与所述电路板的形成有所述金属线的表面相对的表面突出而与外部电气端子电连接。
另外，本发明提供的一种已知合格管芯的制造方法包括：准备电路板的步骤，在所述电路板的一侧表面上形成多根金属线，并在另一侧表面上突出有分别与所述金属线电连接的多个导电插脚；在所述电路板的形成有所述金属线的表面上，形成具有高于所述管芯的正常工作温度的熔点的粘接性膜的步骤；利用所述粘接性膜把具有多个焊盘及分别在它们上部形成的凸点的集成电路芯片附着到所述电路板上，而使所述凸点定位于所述电路板的金属线上的步骤；筛选测试所述集成电路芯片的步骤；以及，使所述粘接性膜气化而从所述电路板上分离所述集成电路芯片的步骤。
此外，本发明提供的另一种已知合格管芯的制造方法包括：准备电路板的步骤，在所述电路板的一侧表面上形成多根金属线，并在另一侧表面上突出有分别与所述金属线电连接的多个导电插脚；在所述电路板的形成有所述金属线的表面上焊接集成电路芯片而使所述焊盘与所述电路板的金属线电气连接的步骤，所述集成电路芯片包括多个焊盘、焊接在所述焊盘上的导电性构件、以及附着在所述导电性构件上且熔点高于所述已知合格管芯的正常工作温度的含焊料金属；对所述集成电路芯片进行筛选测试的步骤；以及，熔化所述含焊料金属而从所述电路板上分离所述集成电路芯片的步骤。
优选地，使所述粘接性膜气化的步骤，是通过把附着有所述芯片的所述电路板暴露在温度高于粘接性膜的玻璃转变温度的惰性气体中而进行的。
优选地，所述惰性气体是氮气，其温度为180～200℃。
根据本发明，在没有封装的条件下，可以对半导体芯片进行筛选测试，从而在封装之前筛选出合格的半导体芯片，避免了封装之后进行筛选测试的浪费。
附图说明
图1A是表示本发明最佳实施例的集成电路芯片的筛选测试电路板的侧面图；
图1B是图1A中的筛选测试电路板的平面图；
图2是在本发明的已知合格管芯的制造方法第一实施例中使用的集成电路芯片的侧面图；
图3是表示在图1A中电路板上涂覆有含导电粒子树脂的状态的侧面图；
图4是在图3的电路板上表示图2的附着状态的侧面图；
图5是在本发明的已知合格管芯制造方法的第二实施例中使用的集成电路芯片的侧面图；
图6是在图5中的集成电路芯片上形成含焊料金属的方法示意图；
图7是表示图6中的集成电路芯片被附着于图1A中的电路板上的状态的侧面图。
具体实施方式
下面，参照附图详细说明本发明的实施例。
图1A和图1B表示本发明最佳实施例的集成电路芯片的筛选测试电路板。参照图1A和图1B，电路板20包括设有多个贯通孔11a的本体11。本体11最好是由像聚酰亚胺那样的有机物质或陶瓷制成。贯通孔11a的直径最好是100-150密尔(mils)。在本体的一侧表面上形成着与后述的集成电路芯片的焊盘电连接的多根金属线13。金属线13可由铜(Cu)、镍(Ni)或金(Au)构成，在由铜构成的情况下，其厚度为4.4～35μm，最好是35μm；在由金构成的情况下，其厚度为0.2～3.75μm，最好是2.5-3μm；在由镍构成的情况下，其厚度为0.5～6μm，最好是3～5.08μm。从与设有本体11的本体11表面相对着的表面，突出有用于与外部电气端子进行电连接的多个插脚12。插脚12分别插入到形成于本体11上的贯通孔11a中而与金属线13电气连接。
下面，利用图1A和图1B中所示的电路板20来说明制造已知合格管芯的方法。
图2表示在本发明的已知合格管芯制造方法的第一实施例中使用的集成电路芯片。参照图2，集成电路芯片1处于未封装的裸露芯片状态，在其一侧表面上设有用于与芯片外部进行电气连接的多个焊盘2。在含有焊盘2的芯片1表面上利用一般方法镀有导电性下凸点电极金属3。而且，在下凸点电极金属3上用一般的凸缘形成方法形成凸缘4。为了筛选测试这样的集成电路芯片1，将其附着于如图1A和图1B所示的电路板20上。
为了附着这样的集成电路芯片，首先，如图3所示地在设有金属线的电路板20的表面上，形成由含导电金属粒子30b的粘接树脂30a构成的粘接性导电膜30，最好是形成各向异性导电膜。其中，各向异性导电膜由含有导电金属的树脂构成。在约5Kg的压力及80℃的温度下，进行约5秒钟的这种粘接性导电膜的堆积。为使这种粘接性导电膜30在高于集成电路芯片正常工作温度的高温下进行筛选测试时也不熔化，必须具有高于集成电路芯片正常工作温度的熔点或玻璃转变温度。粘接性导电膜30最好是具有约150℃的熔点。
在形成粘接性导电膜后，如图4所示地把集成电路芯片1附着在电路板20上。集成电路芯片1的附着过程是这样的，即，在使集成电路芯片1的凸缘4排列成朝向电路板20的粘接性导电膜30的状态下，把集成电路芯片1安置在电路板20上，然后在粘接性导电膜的玻璃转变温度、一般不超过约150℃的温度下向下压芯片1而使其焊接在电路板20上。利用这种在芯片1的附着期间提供的温度和压力，使芯片1的凸缘4通过粘接性导电膜30中所含的导电金属粒子30b同电路板20的金属线13进行电气连接。
在将集成电路芯片1附着于电路板20之后，进行检查集成电路芯片1中是否存在缺陷的筛选测试。这样的筛选测试以常规方式进行。虽然在本申请中未详细说明，但是本领域技术人员能够理解如下操作，即，为了进行这样的筛选测试，通过插脚12把电路板20安装到通常筛选测试装置、例如为形成插脚格网阵列而使用的筛选板上并进行电连接，然后在高于集成电路芯片正常工作温度、例如在125℃温度下，在多次的规定时间内、例如在48小时、38小时和38小时的3次个期间内把测试信号提供给集成电路芯片。根据筛选测试结果，把确定为没有缺陷的集成电路芯片分类为已知合格管芯，而把确定为有缺陷的集成电路芯片分类为不合格管芯。
进行筛选测试之后，从电路板20上分离集成电路芯片1。为了分离集成电路芯片1，在由高于粘接性导电膜30的玻璃转变温度、例如170-200℃温度的惰性气体(如约200℃的氮气)形成的热环境中，将附着有集成电路芯片1的电路板20保持约10秒钟。从而，粘接性导电膜30在约3～4秒钟后完全汽化，所以使集成电路芯片1从电路板20分离。为了有选择地将集成电路芯片1从电路板20上分离，也可以采用如下方法，即利用具有约200℃温度的高温条(hot bar)，使热量从集成电路芯片1的背面传递到粘接性导电膜30上，从而使粘接性导电膜30气化。
这样被分类为已知合格管芯并从电路板上取下的芯片，使用蜂巢式包装作为载体进行销售，或者被作为多芯片组件、直接芯片辅助装置、倒装片、装芯片板等中的芯片而使用。
图5至图7表示本发明的已知合格管芯制造方法的第二实施例。在图5至图7中，和所述第一实施例的附图中的构件相同的构件，使用相同的附图标号。
在第二实施例中，为进行集成电路芯片的筛选测试，和第一实施例相同地使用图1A和图1B所示的电路板20。然而，在第二实施例中利用和第一实施例不同的方式将集成电路芯片附着在电路板20上。参照表示第二实施例中使用的集成电路芯片的图5，利用一般引线焊接方法，把其组成为从Au、Pb+Sn、Cu、Au+Pb+Sn、Au+Sn、以及Cu+Pb+Sn所构成的成分组中选择的金属线(未图示)焊接到集成电路芯片1的焊盘2上。焊接后的金属线最好留有高度20～100μm和大小50～100μm的球形体6，且在该导电性球形体6的颈部进行机械切断。
球形体6的被切断部分附着有含焊料金属。图6表示在导电性球形体6上附着有焊料。参照图6，把焊接在集成电路芯片1上的球形体6稍稍浸渍于装在匣7内且熔点约为170-185℃的液状含焊料金属8中，从而在球形体6的顶部附着少量的含焊料金属8a。所使用的含焊料金属的组成最好是62Sn/34Pb/2Ag、62Sn/34Pb/2In或63Sn/37Pb。
通过浸渍而附着含焊料金属8a之后，将集成电路芯片1定位成使附着的含焊料金属8a朝向电路板20的金属线13，然后，如图7所示，把集成电路芯片1安置到电路板20上。其后，在高于进行筛选测试时的温度、且高于含焊料金属8a的熔点的170-185℃温度下，通过以0kg-1kg的压力向下压集成电路芯片1，使芯片1通过含焊料金属8a搭载到电路板20上。
将集成电路芯片1搭载在电路板20上之后，进行如第一实施例所述的筛选测试。筛选测试后，把集成电路芯片1从电路板20上分离下来。为了分离集成电路芯片1，将附着有集成电路芯片1的电路板20暴露在由高于含焊料金属8a的熔点、例如180-200℃的惰性气体(如约200℃的氮气)组成的热环境中约10秒钟。这样一来，含焊料金属会在约3～4秒钟后完全熔化，从而使集成电路芯片1从电路板20上分离。为了选择性地从电路板20上分离集成电路芯片1，可以采用如下方法，即使用约200℃的高温条(hot bar)，使热量从集成电路芯片1的背面传递到含焊料金属8a上，从而使含焊料金属8a熔化。
通过如上所述的第二实施例而被分类为已知合格管芯且从电路板上取下来的芯片，使用蜂巢式包装作为载体进行销售，或者被作为多芯片组件、直接芯片辅助装置、倒装片、装芯片板等中的芯片而使用。
根据如上所述的本发明，不需封装集成电路芯片，可以在裸露芯片的状态下进行筛选测试。而且，作为不合格品而被发现的集成电路芯片可以不封装，所以在封装集成电路芯片时，可以大幅度节省所消耗的材料和投资的工程费用。也就是说，直接降低已知合格管芯的制造成本。此外，由于本发明构造虽然比较简单，但还能利用能够结合现有的筛选测试装置而使用的筛选测试电路板，所以，还具有可立即实施的附带优点。
如上所述，以最佳实施例为基准对本发明进行了说明及图示，但本领域技术人员可清楚地知道，在不脱离本发明要点的情况下可对上述实施例进行各种变更和修改。

Claims (26)

1.一种用于集成电路芯片筛选测试组件的电路板，该集成电路芯片上具有多个焊盘，其特征是，所述电路板包括：
设有多个垂直贯通孔的本体，该本体为有机材料或者陶瓷材料；
在所述本体的一侧表面上形成且与所述集成电路芯片的焊盘电连接的多根金属线；
多个插脚，分别插入所述孔中而与所述金属线电连接，并从与所述电路板的形成有所述金属线的表面相对的表面突出而与外部电气端子电连接；以及
粘接性膜，其形成在所述本体的一侧表面上，所述金属线形成在粘接性膜上，粘接性膜之中具有导电金属颗粒，用于在筛选测试过程中将金属线与焊盘电连接。
2.如权利要求1所述的电路板，其特征是，所述金属线是由从铜、金和镍组成的组中选择的材料构成的。
3.如权利要求1所述的电路板，其特征是，所述孔的直径为2540-3810μm。
4.如权利要求2所述的电路板，其特征是，所述金属线由厚度为4.4～35μm的铜构成。
5.如权利要求2所述的电路板，其特征是，所述金属线由厚度为0.5～6μm的镍构成。
6.如权利要求2所述的电路板，其特征是，所述金属线由厚度为0.2～3μm的金构成。
7.一种制造已知合格管芯的方法，其特征是，包括：准备电路板的步骤，在所述电路板的一侧表面上形成多根金属线，并在另一侧表面上突出有分别与所述金属线电连接的多个导电插脚；在所述电路板的形成有所述金属线的表面上，形成具有高于所述管芯的正常工作温度的熔点的粘接性膜的步骤；利用所述粘接性膜把具有多个焊盘及分别在它们上部形成的凸点的集成电路芯片附着到所述电路板上，而使所述凸点定位于所述电路板的金属线上的步骤；筛选测试所述集成电路芯片的步骤；以及，使所述粘接性膜气化而从所述电路板上分离所述集成电路芯片的步骤。
8.如权利要求7所述的方法，其特征是，所述粘接性膜是各向异性导电膜。
9.如权利要求7所述的方法，其特征是，所述粘接性膜具有150℃或更低的玻璃转变温度。
10.如权利要求7所述的方法，其特征是，将所述集成电路芯片附着在所述电路板上的步骤包括：在使所述集成电路芯片的凸点朝向所述电路板的金属线而定位的状态下，使所述芯片位于所述粘接性膜上的步骤；以及，在不超过所述粘接性膜的玻璃转变温度的温度下，向下压所述电路板的步骤。
11.如权利要求7所述的方法，其特征是，使所述粘接性膜气化的步骤，是通过把附着有所述芯片的所述电路板暴露在温度高于粘接性膜的玻璃转变温度的惰性气体中而进行的。
12.如权利要求7所述的方法，其特征是，使所述粘接性膜气化的步骤，是利用温度高于所述粘接性膜的玻璃转变温度的高温条，使热量从附着在所述电路板上的所述芯片的背面传递到所述粘接性膜上而进行的。
13.如权利要求11所述的方法，其特征是，所述惰性气体是氮气，其温度为180～200℃。
14.如权利要求12所述的方法，其特征是，所述高温条具有200℃的温度。
15.一种制造已知合格管芯的方法，其特征是，包括：准备电路板的步骤，在所述电路板的一侧表面上形成多根金属线，并在另一侧表面上突出有分别与所述金属线电连接的多个导电插脚；在所述电路板的形成有所述金属线的表面上焊接集成电路芯片而使所述焊盘与所述电路板的金属线电气连接的步骤，所述集成电路芯片包括多个焊盘、焊接在所述焊盘上的导电性构件、以及附着在所述导电性构件上且熔点高于所述已知合格管芯的正常工作温度的含焊料金属；对所述集成电路芯片进行筛选测试的步骤；以及，熔化所述含焊料金属而从所述电路板上分离所述集成电路芯片的步骤。
16.如权利要求15所述的方法，其特征是，所述导电构件是由从Au、Pb+Sn、Cu、Au+Pb+Sn、Au+Sn、以及Cu+Pb+Sn所组成的组中选择的材料构成的。
17.如权利要求15所述的方法，其特征是，所述导电构件为球形。
18.如权利要求17所述的方法，其特征是，所述球形导电构件的高度为20～100μm。
19.如权利要求17所述的方法，其特征是，所述球形导电构件的直径为50-100μm。
20.如权利要求17所述的方法，其特征是，所述含焊料金属的组成是从62重量％Sn/34重量％Pb/2重量％Ag、62重量％Sn/34重量％Pb/2重量％In、以及63重量％Sn/37重量％Pb所构成的组中选择出的。
21.如权利要求15所述的方法，其特征是，所述含焊料金属具有170-185℃的熔点。
22.如权利要求15所述的方法，其特征是，将所述集成电路芯片附着在所述电路板上的步骤包括：在使所述集成电路芯片的含焊料金属朝着所述电路板的金属线而定位的状态下，将所述芯片安置在所述电路板上的步骤；以及
在170～185℃的温度下，以1kgf或更小的负荷向下压所述电路板的步骤。
23.如权利要求15所述的方法，其特征是，使所述含焊料金属熔化的步骤，是通过把附着有所述芯片的所述电路板暴露在温度高于含焊料金属的熔点的惰性气体中而进行的。
24.如权利要求15所述的方法，其特征是，使所述含焊料金属熔化的步骤，是利用温度高于所述含焊料金属的熔点的高温条，使热量从附着在所述电路板上的所述芯片的背面传递到所述含焊料金属上而进行的。
25.如权利要求23所述的方法，其特征是，所述惰性气体是温度为180-200℃的氮气。
26.如权利要求24所述的方法，其特征是，所述高温条的温度为200℃。
CN97114368A 1996-12-11 1997-12-11 用于集成电路芯片筛选测试组件的电路板及方法 Expired - Fee Related CN1133207C (zh)

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