JPS57106062A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS57106062A
JPS57106062A JP18186580A JP18186580A JPS57106062A JP S57106062 A JPS57106062 A JP S57106062A JP 18186580 A JP18186580 A JP 18186580A JP 18186580 A JP18186580 A JP 18186580A JP S57106062 A JPS57106062 A JP S57106062A
Authority
JP
Japan
Prior art keywords
chip
chips
power source
electric power
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18186580A
Other languages
Japanese (ja)
Inventor
Yutaka Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18186580A priority Critical patent/JPS57106062A/en
Publication of JPS57106062A publication Critical patent/JPS57106062A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To perform indication of a faulty chip precisely in a short time at a package in which IC's are mounted on the surface of a substrate and terminals are led out on the back by a method wherein electric power source layers are separated at every chips, and are led out being made as individual pins. CONSTITUTION:At the ceramic wiring substrate 2, the electric power source layers only are separated at every chips 1, 1a without being made as common, and are led to the package pins 4, 4a individually being made as layers 6, 6a. When the chip 1 is to be tested, a probe of tester is made to come in contact with a pad 10, the pin 4 is connected to an electric power source and a pin 3 is earthed through a common earth layer 7. Accordingly although the chip 1a which is not to be tested is connected through a wiring layer 8, it becomes as irrelevant. A test pattern is sent to the chip 1 through the probe to perform test. The chips are tested in order, and faulty articles are exchanged. The substrate 2 is tested beforehand through the pads 10, 10a. The earth layer 7 may be also separated at every chips and are provided with pins as occasion demands. Even when the pins are increased, stability of the electric power source is not reduced, and indication of faulty chip can be performed completely and precisely.
JP18186580A 1980-12-24 1980-12-24 Package for integrated circuit Pending JPS57106062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18186580A JPS57106062A (en) 1980-12-24 1980-12-24 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18186580A JPS57106062A (en) 1980-12-24 1980-12-24 Package for integrated circuit

Publications (1)

Publication Number Publication Date
JPS57106062A true JPS57106062A (en) 1982-07-01

Family

ID=16108186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18186580A Pending JPS57106062A (en) 1980-12-24 1980-12-24 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS57106062A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110137A (en) * 1982-12-15 1984-06-26 Hitachi Ltd Power feeding system
US4744007A (en) * 1983-03-29 1988-05-10 Nec Corporation High density LSI package for logic circuits
US4884167A (en) * 1987-11-09 1989-11-28 Nec Corporation Cooling system for three-dimensional IC package
US4942497A (en) * 1987-07-24 1990-07-17 Nec Corporation Cooling structure for heat generating electronic components mounted on a substrate
US4945980A (en) * 1988-09-09 1990-08-07 Nec Corporation Cooling unit
US4975766A (en) * 1988-08-26 1990-12-04 Nec Corporation Structure for temperature detection in a package
US4984132A (en) * 1988-08-10 1991-01-08 Hitachi, Ltd. Multilayer wiring substrate
US5014777A (en) * 1988-09-20 1991-05-14 Nec Corporation Cooling structure
US5023695A (en) * 1988-05-09 1991-06-11 Nec Corporation Flat cooling structure of integrated circuit
US5036384A (en) * 1987-12-07 1991-07-30 Nec Corporation Cooling system for IC package
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
KR100233556B1 (en) * 1996-12-11 1999-12-01 김영환 Reliability test method of semiconductor chip
US6103553A (en) * 1996-12-11 2000-08-15 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a known good die utilizing a substrate

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110137A (en) * 1982-12-15 1984-06-26 Hitachi Ltd Power feeding system
US4744007A (en) * 1983-03-29 1988-05-10 Nec Corporation High density LSI package for logic circuits
US4942497A (en) * 1987-07-24 1990-07-17 Nec Corporation Cooling structure for heat generating electronic components mounted on a substrate
US4884167A (en) * 1987-11-09 1989-11-28 Nec Corporation Cooling system for three-dimensional IC package
US5036384A (en) * 1987-12-07 1991-07-30 Nec Corporation Cooling system for IC package
US5023695A (en) * 1988-05-09 1991-06-11 Nec Corporation Flat cooling structure of integrated circuit
US4984132A (en) * 1988-08-10 1991-01-08 Hitachi, Ltd. Multilayer wiring substrate
US4975766A (en) * 1988-08-26 1990-12-04 Nec Corporation Structure for temperature detection in a package
US4945980A (en) * 1988-09-09 1990-08-07 Nec Corporation Cooling unit
US5014777A (en) * 1988-09-20 1991-05-14 Nec Corporation Cooling structure
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
KR100233556B1 (en) * 1996-12-11 1999-12-01 김영환 Reliability test method of semiconductor chip
US6103553A (en) * 1996-12-11 2000-08-15 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a known good die utilizing a substrate
US6429453B1 (en) 1996-12-11 2002-08-06 Hyundai Electronics Industries Co., Ltd. Substrate assembly for burn in test of integrated circuit chip

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