CN1128405A - 形成半导体器件微细接触的方法 - Google Patents
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Abstract
本发明提供了一种用于形成半导体器件的微细接触的方法,改善了半导体器件的可靠性并实现了半导体器件的高集成化。
Description
本发明涉及形成半导体器件的微细接触的方法,特别涉及形成其尺寸比接触掩模的实际尺度小的微细接触的方法。
半导体器件的高集成的最新发展方向包含单个单元面积的缩小。因此,提供能达到工艺容限的技术就变得很重要。
然而,以现有的技术和设备来制造高集成度的半导体器是困难的,因为现有的技术和设备提供不了能胜任的工艺容限。
下面介绍用于形成半导体器件接触的常规方法。
根据常规方法,在半导体衬底上与栅氧化膜重叠地形成多晶硅膜,做为栅电极的导电层;然后使杂质离子注入到多晶硅膜中;使用栅电极掩模,腐蚀多晶硅膜和栅氧化膜,因而形成栅电极;此后在以栅电极作为掩模的条件下,使杂质离子注入到半导体衬底中,因而限定源/漏结区;在所得结构上,形成绝缘层,提供平坦化的表面;利用接触掩模,在对应于半导体衬底有源区的绝缘膜的部分上形成光刻胶膜图形;以光刻胶膜图形作为掩模,部分腐蚀绝缘膜,因而形成接触孔;通过接触孔在预期的部位露出半导体衬底;此后,在所得结构上形成另一导电层,使它通过接触孔与半导体衬底接触。这样就形成了接触。
但依此方法,在栅电极和隐埋于接触孔内的导电层之间可能发生短路,因为接触孔的形成是通过使用根据最小设计准则而设计的接触掩模来实现的。其结果,降低了半导体器件的可靠性。为了解决这个问题,则要增加相邻栅电极间的距离,或减小用于形成接触的接触掩模的尺寸。然而,当增加相邻栅电极间距离时,半导体器件的体积就变得庞大。在此情况下,不可能实现半导体器件的高集成化。在减小接触掩模的情况下,难以获得预期的图形,这0是因为受所用设备的分辨率所限。在此情况下,半导体器件的可靠性也会显示出下降。而且,难以实现半导体器件的高集成化。
所以,本发明之目的在于提供用于形成半导体器件的微细接触的方法,能形成其尺寸小于接触掩模的实际尺度的微细接触的方法。
根据本发明,通过提供一种形成半导体器件的微细接触的方法来达到发明之目的。该方法包括以下各步骤:在一块半导体衬底上形成栅氧化膜;在栅氧化膜上形成作为栅电极的多晶硅膜;在形成多晶硅膜后所得的结构上形成第一绝缘膜;使用栅电极掩模连续腐蚀第一绝缘膜、多晶硅膜及栅氧化膜,由此形成栅电极和栅氧化膜图形,同时部分露出半导体衬底;在以第一绝缘膜作为掩模的条件下,在半导体衬底的裸露部分注入低浓度的杂质离子;在第一绝缘膜和栅电极的侧壁上形成绝缘膜调整垫;在以设置于半导体衬底上的上部结构为掩模的条件下,在半导体衬底的裸露部分注入高浓度的杂质离子,因而形成源、漏区;在源、漏区形成后所得的结构上形成预期厚度的焊盘导电层;在焊盘导电层上形成第二绝缘膜,而使结构平坦化;使用接触掩模在第二绝缘膜上形成光刻胶膜图形;使用光刻胶膜图形作掩模腐蚀第二绝缘膜,以便部分地露出焊盘导电层;去掉光刻胶膜图形;选择生长焊盘导电层的裸露部分,以形成第二导电层;用第二导电层作掩模腐蚀第二绝缘膜,以形成第二绝缘膜的图形;腐蚀焊盘导电层和第二导电层;在腐蚀第二导电层后所得的结构上形成第三绝缘膜,以使结构平坦化;完全腐蚀被第三绝缘膜平坦化的结构,直至露出第二绝缘膜图形,然后使所得结构平坦化;在平坦化的结构上形成预期厚度的第三导电层作为位线;使用位线掩模腐蚀第三导电层,因而形成与半导体衬底接触的位线。
从下面参照附图对实施方案的描述会使本发明的其它目的和方面变得更加明显。
图1是表明依本发明所用的掩模布图的平面图;以及
图2A—2D是分别表明根据本发明的实施方案来形成半导体器件微细接触的方法的连续步骤的剖面图。
图1是表明用于形成作为第一导电层的半导体衬底与作为第二导电层的位线间的接触的掩模布图的平面图。在图1中,标号“a”代表隔离区掩模;“b”代表栅电极掩模;“c”和“c”代表接触孔掩膜;而“d”代表位线掩模。接触孔掩模c具有依本发明的结构,而接触孔c′是有常规的结构。由于所用设备分辨率所限,用接触孔掩模c′,其尺寸小于基于最小设计准则尺寸,则难以获得预期的接触。当根据接触孔掩模c′作出最小设计准则时,会使芯片面积增大。
图2A—2D是分别表明根据本发明的实施方案来形成半导体器件微细接触的方法的连续步骤的剖面图。
根据此方法,制备一块半导体衬底11作为第一导电层,在其上形成元件隔绝缘膜12,如图2A所示。在所得结构上连续形成栅氧化膜13,用以形成栅电极的多晶硅膜14及第一绝缘膜17。使用栅电极掩模,连续腐蚀第一绝缘膜17,多晶硅膜14及栅氧化膜13,因而形成栅电极。多晶硅膜可由多硅化物制成。此后,在以第一绝缘膜17作掩模的条件下,使杂质离子注入到半导体衬底中,因而形成低浓度杂质注入区。然后,在第一绝缘膜17,栅电极14和栅氧化膜13的侧壁上形成绝缘膜调距垫15。随后,使高浓度杂质离子注入到低浓度杂质注入区,因而分别形成源、漏结区16。在所得结构上再形成焊盘多晶硅膜18。该焊盘多晶硅膜18可由多硅化物制成。在焊盘多晶硅膜18上再形成第二绝缘膜19,以提供一平坦化的表面。使用接触掩模(未画出),在第二绝缘膜19上形成一光刻胶膜图形20。该接触掩模是按最小设计准则形成的。
以光刻胶膜图形20作为掩模,再腐蚀第二绝缘膜19,以便露出焊盘多晶硅膜18,如图2B所示。在这个腐蚀步骤,焊盘多晶硅膜18起着腐蚀阻挡层的作用。然后,选择生长焊盘多晶硅膜18的裸露部分,以此形成第二导电层21。这时的第二导电层21是过度生长的,以致与第二绝缘膜19重叠一定的宽度。
此后,在以第二导电层21作为掩模的条件下,腐蚀第二绝缘膜19,因而形成第二绝缘膜图形19′,如图2C所示。在第二绝缘膜图形19′形成后,部分露出焊盘多晶多膜18。以第一绝缘膜17和第二绝缘膜图形19′作为腐蚀阻挡层,再完全腐蚀多晶硅膜18的裸露部分及生长过高的第二导电层21。
然后在完全图2C的步骤之后所得到的结构上形成第三绝缘膜22,以使结构能有个平坦化的表面,如图2D所示。然后完全腐蚀所得结构,直至露出第二绝缘膜图形19′。随后,实行平坦化。在所得结构的平坦化的表面上,形成用于形成位线的多晶硅膜,作为第三导电层。然后使用一位线掩模,腐蚀位线多晶硅膜,因而形成与半导体衬底11的源、漏结区16相接触的位线23。
由以上说明可知,根据本发明的方法能形成其尺寸小于根据最小设计准则制成的光刻胶胶图形的实际尺寸的微接触。所以,可以改善半导体器件的可靠性并实现半导体器件的高集成化。
虽然为了解释之目的公开了本发明的优选实施方案,但本领域的技术人员会理解到,在不脱离所附权利要求记载的本发明的范畴和精神的前提下,可以有各式各样的改型、补充和替代。
Claims (5)
1.一种形成半导体器件微细接触的方法,包括以下各步骤:
在一块半导体衬底上形成栅氧化膜;
在栅氧化膜上形成用作栅电极的多晶硅膜;
在多晶硅膜形成之后所得的结构上形成第一绝缘膜;
使用一栅电极掩模连续腐蚀第一绝缘膜、多晶硅膜及栅氧化膜,因而形成一栅电极和栅氧化膜的图形,同时部分露出半导体衬底;
在以第一绝缘膜作为掩模的条件下,向半导体衬底的裸露部分注入低浓度的杂质离子;
在第一绝缘膜和栅电极的侧壁上形成绝缘膜调距垫;
在以设置于半导体衬底的上部结构作为掩模的条件下,向半导体衬底的裸露部分注入高浓度的杂质离子,因而形成源、漏区;
在源、漏区形成之后所得到的结构上,形成预期厚度的焊盘导电层;
在焊盘导电层上形成第二绝缘膜,因而使结构平坦化;
使用一接触掩模,在第二绝缘膜上形成光刻胶膜图形;
以光刻胶膜图形作为掩模腐蚀第二绝缘膜,以致部分露出焊盘导电层;
去掉光刻胶膜图形;
选择生长焊盘导电层的裸露部分,因而形成第二导电层;
以第二导电层作为掩模腐蚀第二绝缘膜,因而形成第二绝缘膜图形;
腐蚀焊盘导电层和第二导电层;
在腐蚀第二导电层之后所得到的结构上形成第三绝缘膜,因而使结构平坦化;
全面腐蚀被第三绝缘膜平坦化的结构,直至露出第二绝缘膜图形,然后使所得结构平坦化;
在平坦化的结构上形成预期厚度的用于位线的第三导电层;以及
使用一位线掩模,腐蚀第三导电层,因而形成与半导体衬底相接触的位线。
2.根据权利要求1的方法,其中的焊盘导电层是从由多晶硅和多硅化物组成的集合中选出的一种材料。
3.根据权利要求1的方法,其中的第二导电层是过度生长的,以致与腐蚀后的第二绝缘膜的两相对横端重叠。
4.根据权利要求1的方法,其中的腐蚀焊盘导电层和第二导电层的步骤是以第二绝缘膜图形和第一绝缘膜作为腐蚀阻挡层,通过全面腐蚀完成的。
5.根据权利要求1的方法,其中的半导体器件的接触尺寸是受绝缘膜调距垫的厚度控制的。
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KR1019940027927A KR0161731B1 (ko) | 1994-10-28 | 1994-10-28 | 반도체소자의 미세콘택 형성방법 |
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US5262352A (en) * | 1992-08-31 | 1993-11-16 | Motorola, Inc. | Method for forming an interconnection structure for conductive layers |
US5312768A (en) * | 1993-03-09 | 1994-05-17 | Micron Technology, Inc. | Integrated process for fabricating raised, source/drain, short-channel transistors |
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-
1994
- 1994-10-28 KR KR1019940027927A patent/KR0161731B1/ko not_active IP Right Cessation
-
1995
- 1995-10-23 US US08/546,736 patent/US5550071A/en not_active Expired - Lifetime
- 1995-10-25 GB GB9521883A patent/GB2294587B/en not_active Expired - Fee Related
- 1995-10-25 CN CN95118265A patent/CN1043102C/zh not_active Expired - Fee Related
- 1995-10-27 DE DE19540124A patent/DE19540124C2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR960015739A (ko) | 1996-05-22 |
CN1043102C (zh) | 1999-04-21 |
DE19540124A1 (de) | 1996-05-02 |
GB9521883D0 (en) | 1996-01-03 |
GB2294587A (en) | 1996-05-01 |
US5550071A (en) | 1996-08-27 |
DE19540124C2 (de) | 1997-12-18 |
GB2294587B (en) | 1998-08-26 |
KR0161731B1 (ko) | 1999-02-01 |
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