CN112542422A - 半导体器件和形成半导体器件的方法 - Google Patents

半导体器件和形成半导体器件的方法 Download PDF

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CN112542422A
CN112542422A CN202010906289.9A CN202010906289A CN112542422A CN 112542422 A CN112542422 A CN 112542422A CN 202010906289 A CN202010906289 A CN 202010906289A CN 112542422 A CN112542422 A CN 112542422A
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China
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layer
metal
silicon
metal nitride
nitride layer
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陈彦羽
程仲良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成半导体器件的方法包括蚀刻介电层以在介电层中形成沟槽，沉积延伸至沟槽中的金属层，对金属层实施氮化工艺以将金属层的部分转换为金属氮化物层，对金属氮化物层实施氧化工艺以形成金属氮氧化物层，去除金属氮氧化物层，并且使用自底向上沉积工艺将金属材料填充至沟槽中以形成接触插塞。本申请的实施例还涉及半导体器件。

Description

半导体器件和形成半导体器件的方法
技术领域
本申请的实施例涉及半导体器件和形成半导体器件的方法。
背景技术
在集成电路的制造中，源极/漏极接触插塞被用于连接至源极和漏极区域以及晶体管的栅极。源极/漏极接触插塞通常连接至源极/漏极硅化物区域，它的形成工艺包括在层间电介质中形成接触开口，沉积延伸至接触开口中的金属层，以及然后实施退火使金属层与源极/漏极区域的硅/锗反应。然后，在剩余接触开口中形成源极/漏极接触插塞。
发明内容
本申请的一些实施例提供了一种形成半导体器件的方法，包括：蚀刻介电层以在所述介电层中形成沟槽；沉积延伸至所述沟槽中的金属层；对所述金属层实施氮化工艺以将所述金属层的上部转换为金属氮化物层；对所述金属氮化物层实施氧化工艺以形成金属氮氧化物层；去除所述金属氮氧化物层；以及使用自底向上沉积工艺将金属材料填充至所述沟槽中以形成接触插塞。
本申请的另一些实施例提供了一种半导体器件，包括：接触蚀刻停止层；第一层间电介质，位于所述接触蚀刻停止层上方；以及接触插塞，延伸至所述接触蚀刻停止层和所述第一层间电介质中，所述接触插塞包括：金属氮化物层；含硅层，位于所述金属氮化物层上方；以及均质金属材料，位于所述含硅层上方。
本申请的又一些实施例提供了一种半导体器件，包括：源极/漏极区域；第一金属硅化物区域，位于所述源极/漏极区域上方并且接触所述源极/漏极区域；以及接触插塞，位于所述第一金属硅化物区域上方并且接触所述第一金属硅化物区域，所述接触插塞包括：金属氮化物层；第二金属硅化物区域，位于所述金属氮化物层上方；以及铝区域，位于所述第二金属硅化物区域上方。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图6、图7A、图7B、图8至图11、图12A、图12B和图13至图22示出了根据一些实施例形成晶体管和各个接触插塞的中间阶段的立体图和截面图。
图23示出了根据一些实施例用于形成接触插塞的生产工具。
图24示出了根据一些实施例用于形成晶体管和各个接触插塞的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…正下方”、“在…下方”、“下部”、“覆盖在…上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了一种晶体管及其形成方法。根据一些实施例，示出了形成晶体管和相应的接触插塞的中间阶段。根据一些实施例，示出了形成晶体管和通孔的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和说明性实施例，相似的参考标号用于指示相似的元件。在所示的实施例中，鳍式场效应晶体管(FinFET)的形成用作实例以解释本发明的概念。其它类型的晶体管，诸如纳米线晶体管、纳米片晶体管、平面晶体管、全环栅(GAA)晶体管等也可以采用本发明的概念。此外，该方法可以应用于其它互连结构，诸如通孔、金属线等。尽管方法实施例可以被讨论为以特定顺序实施，但是其它方法实施例可以以任何逻辑顺序实施。
根据本发明的一些实施例，源极/漏极接触插塞和栅极接触插塞分别形成在晶体管的源极/漏极区域和栅电极上方并且接触晶体管的源极/漏极区域和栅电极。接触插塞的形成工艺包括沉积金属层，氮化金属层的表面部分以形成金属氮化物层，以及实施退火工艺以形成源极/漏极硅化物。然后将金属氮化物层氧化，使得可以除去所得的氧化物，并且金属氮化物层的一些部分留在接触开口的底部。金属氮化物层用作用于选择性沉积金属的基底，并且沉积是自底向上的。
图1至图6、图7A、图7B、图8至图11、图12A、图12B和图13至图22示出了根据本发明的一些实施例在FinFET和相应的接触插塞的形成中的中间阶段的立体图和截面图。这些附图中所示的工艺也示意性地反映在如图24所示的工艺流程400中。
在图1中，提供了衬底20。衬底20可以是半导体衬底，诸如体半导体衬底、绝缘体上半导体衬底(SOI)等，可以是掺杂的(例如，用p型或n型掺杂物质)或不掺杂的。半导体衬底20可以是晶圆10的一部分，诸如硅晶圆。通常，SOI衬底是在绝缘层上形成的半导体材料层。绝缘层可以是例如埋氧化物(BOX)层、氧化硅层等。绝缘层设置在通常为硅衬底或玻璃衬底的衬底上。也可以使用诸如多层或梯度衬底的其它衬底。在一些实施例中，半导体衬底20的半导体材料可以包括硅；锗；包括碳化硅、SiPC、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。
进一步参考图1，阱区域22形成在衬底20中。在图24所示的工艺流程400中，各个工艺被示为工艺402。根据本发明的一些实施例，阱区域22是通过将可以是硼、铟等的p型杂质注入到衬底20中而形成的p型阱区域。根据本发明的其它实施例，阱区域22是通过将可以是磷、砷、锑等的n型杂质注入到衬底20中而形成的n型阱区域。所得的阱区域22可以延伸至衬底20的顶面。n型或p型杂质浓度可以等于或小于1018cm-3，诸如在约1017cm-3和约1018cm-3之间的范围内。
参考图2，隔离区域24形成为从衬底20的顶面延伸至衬底20中。在下文中，隔离区域24可选地称为浅沟槽隔离(STI)区域。在图24所示的工艺流程400中，各个工艺被示为工艺404。衬底20在相邻的STI区域24之间的部分被称为半导体条26。为了形成STI区域24，在半导体衬底20上形成垫氧化物层28和硬掩模层30，然后图案化。垫氧化物层28可以是由氧化硅形成的薄膜。根据本发明的一些实施例，在热氧化工艺中形成垫氧化物层28，其中半导体衬底20的顶面层被氧化。垫氧化物层28充当在半导体衬底20和硬掩模层30之间的粘合层。垫氧化物层28还可充当用于蚀刻硬掩模层30的蚀刻停止层。根据本发明的一些实施例，硬掩模层30由氮化硅形成，例如，使用低压化学汽相沉积(LPCVD)。根据本发明的其它实施例，硬掩模层30通过硅的热氮化或等离子体增强化学汽相沉积(PECVD)形成。在硬掩模层30上形成光刻胶(未示出)，并且然后图案化。然后，使用图案化的光刻胶作为蚀刻掩模图案化硬掩模层30，以形成如图2所示的硬掩模30。
下一步，将图案化的硬掩模层30用作蚀刻掩模以蚀刻垫氧化物层28和衬底20，随后用介电材料填充衬底20中的所得沟槽。实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除介电材料的过量部分，并且介电材料的剩余部分为STI区域24。STI区域24可以包括衬垫电介质(未示出)，其可以是通过对衬底20的表面层进行热氧化而形成的热氧化物。衬垫电介质也可以是沉积的氧化硅层、氮化硅层等，使用例如原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)或化学汽相沉积(CVD)形成。STI区域24也可以包括在衬垫氧化物上方的介电材料，其中介电材料可以使用可流动化学汽相沉积(FCVD)、旋涂等方法形成。根据一些实施例，位于衬垫电介质上方的介电材料可以包括氧化硅。
硬掩模30的顶面和STI区域24的顶面可以基本上彼此平齐。半导体条26在相邻的STI区域24之间。根据本发明的一些实施例，半导体条26是原始衬底20的一部分，因此半导体条26的材料与衬底20的材料相同。根据本发明的可选实施例，半导体条26是通过蚀刻STI区域24之间的衬底20的部分以形成凹槽而形成的替换条，并且实施外延以在凹槽中重新生长另一种半导体材料。因此，半导体条26由与衬底20不同的半导体材料形成。根据一些实施例，半导体条26由硅锗、硅碳或III-V族化合物半导体材料形成。
参考图3，STI区域24是凹进的，使得半导体条26的顶部突出得比STI区域24的剩余部分的顶面24A高，以形成突出鳍36。在图24所示的工艺流程400中，各个工艺被示为工艺406。可以使用干蚀刻工艺实施蚀刻，其中例如将HF3和NH3用作蚀刻气体。在蚀刻工艺期间，可能产生等离子体。也可以包括氩。根据本发明的可选实施例，STI区域24的凹进使用湿蚀刻工艺实施。蚀刻化学物质可以包括例如HF。
突出鳍36可以由其它半导体材料形成或被其它半导体材料代替。例如，对于NMOS晶体管，突出鳍36可以包括或由Si、SiP、SiC、SiPC或III-V族化合物半导体(诸如InP、GaAs、AlAs、InAs、InAlAs、InGaAs等)形成。对于PMOS晶体管，突出鳍36可以包括或由Si、SiGe、SiGeB、Ge或III-V族化合物半导体(诸如InSb、GaSb、InGaSb等)形成。
在以上示出的实施例中，可以通过任何合适的方法来图案化鳍。例如，可以使用一个或多个光刻工艺图案化鳍，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺将光刻和自对准工艺相结合，从而允许创建具有例如间距小于使用单个直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层，并且使用光刻工艺图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后可以使用剩余间隔件或芯轴来图案化鳍。
参考图4，伪栅极堆叠件38形成为在(突出)鳍36的顶面和侧壁上延伸。在图24所示的工艺流程400中，各个工艺被示为工艺408。伪栅极堆叠件38可以包括伪栅极电介质40和在伪栅极电介质40上方的伪栅电极42。伪栅电极42可以例如使用多晶硅形成，并且也可以使用其它材料。伪栅极堆叠件38中的每个还可以在伪栅电极42上方包括一个(或多个)硬掩模层44。硬掩模层44可以由氮化硅、氧化硅、碳氮化硅或它们的多层形成。伪栅极堆叠件38可以跨过单个或多个突出鳍36和/或STI区域24。伪栅极堆叠件38还具有垂直于突出鳍36的长度方向的长度方向。
下一步，在伪栅极堆叠件38的侧壁上形成栅极间隔件46。在图24所示的工艺流程400中，各个工艺也被示为工艺408。根据本发明的一些实施例，栅极间隔件46由诸如氮化硅、碳氮化硅等的介电材料形成，并且可以具有包括多个介电层的单层结构或多层结构。
然后实施蚀刻工艺以蚀刻未被伪栅极堆叠件38和栅极间隔件46覆盖的突出鳍36的部分，得到图5所示的结构。在图24所示的工艺流程400中，各个工艺被示为工艺410。凹槽可以是各向异性的，并且因此鳍36的直接在伪栅极堆叠件38和栅极间隔件46正下方的部分受到保护，并且未被蚀刻。根据一些实施例，凹进的半导体条26的顶面可以低于STI区域24的顶面24A。相应地形成凹槽50。凹槽50包括位于伪栅极堆叠件38的相对侧上的部分以及在突出鳍36的剩余部分之间的部分。
下一步，通过在凹槽50中选择性地生长(通过外延)半导体材料来形成外延区域(源极/漏极区域)54，得到图6中的结构。在图24所示的工艺流程400中，各个工艺被示为工艺412。取决于所得的FinFET是p型FinFET还是n型FinFET，随着外延的进行，可以原位掺杂p型或n型杂质。例如，当所得的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)、硅硼(SiB)等。相反，当所得的FinFET是n型FinFET时，可以生长硅磷(SiP)、硅碳磷(SiCP)等。根据本发明的可选实施例，外延区域54包括III-V族化合物半导体，诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。在凹槽50中填充有外延区域54之后，外延区域54的进一步外延生长导致外延区域54水平扩展，并且可以形成刻面。外延区域54的进一步生长还可以导致相邻的外延区域54彼此融合。可能产生空隙(气隙)56。根据本发明的一些实施例，当外延区域54的顶面仍然是波浪形时，或者当合并的外延区域54的顶面已经变得平坦时，外延区域54的形成可以结束，如图6所示，这是通过在外延区域54上进一步生长来实现的。
在外延步骤之后，可以用p型或n型杂质进一步注入外延区域54以形成源极区域和漏极区域，其也用参考数字54表示。根据本发明的可选实施例，当在外延期间外延区域54原位掺杂有p型或n型杂质时，跳过注入步骤。
图7A示出了在形成接触蚀刻停止层(CESL)58和层间电介质(ILD)60之后的结构的立体图。在图24所示的工艺流程400中，各个工艺被示为工艺414。CESL 58可以由氧化硅、氮化硅、碳氮化硅、碳氧化硅、氧氮化硅、氧碳氮化硅、氧化铝、氮化铝等形成，并且可以使用CVD、ALD等形成。ILD 60可以包括使用例如FCVD、旋涂、CVD或另一种沉积方法形成的介电材料。ILD 60可以由含氧的介电材料形成，其可以是基于氧化硅的材料，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、碳化硅、高k介电材料(诸如氧化锆、氧化铪)或低k介电材料。可以实施诸如CMP工艺或机械研磨工艺的平坦化工艺以使ILD 60、伪栅极堆叠件38和栅极间隔件46的顶面彼此平齐。
图7B示出了图7A中的参考截面7B-7B，其中示出了伪栅极堆叠件38。应当理解，未示出源极/漏极区域54的右侧上的结构(诸如在区域63中)，而在一些实施例中，可以在区域63和区域63的右侧的区域中形成包括与栅极结构38相同的栅极结构和相应的栅极间隔件的结构。
下一步，蚀刻包括硬掩模层44的伪栅极堆叠件38、伪栅电极42和伪栅极电介质40，在栅极间隔件46之间形成沟槽62，如图8所示。在图24所示的工艺流程400中，各个工艺被示为工艺416。突出鳍36的顶面和侧壁暴露于沟槽62。下一步，如图9所示，在沟槽62(图8)中形成替换栅极堆叠件68。在图24所示的工艺流程400中，各个工艺被示为工艺418。替换栅极堆叠件68包括栅极电介质64和相应的栅电极66。
根据本发明的一些实施例，栅极电介质64包括界面层(IL)作为它的下部。IL形成在突出鳍36的暴露面上。IL可以包括诸如氧化硅层的氧化物层，通过突出鳍36的热氧化、化学氧化工艺或沉积工艺形成。栅极电介质64还可包括在IL上方形成的高k介电层。高k介电层包括高k介电材料，诸如氧化铪、氧化镧、氧化铝、氧化锆等。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0，而有时高达21.0或更高。高k介电层覆盖并且可以接触IL。根据本发明的一些实施例，使用ALD、CVD、PECVD、分子束沉积(MBD)等形成高k介电层。
栅电极66形成在栅极电介质64上。栅电极66可以包括多个堆叠层，它们可以形成为共形层，并且填充金属区域填充未被多个堆叠层填充的其余沟槽62。堆叠层可以包括阻挡层、位于阻挡层上方的功函层以及位于功函层上方的一个或多个金属覆盖层。填充金属区域可以由钨、钴等形成。根据可选实施例，可以不形成阻挡层，并且覆盖层可以完全充满沟槽，并且不形成填充金属区域。
图10示出了根据一些实施例的自对准硬掩模70的形成。在图24所示的工艺流程400中，各个工艺被示为工艺420。根据其它实施例，未形成自对准硬掩模70。硬掩模70的形成可以包括实施蚀刻工艺以使栅极堆叠件68凹进，使得在栅极间隔件46之间形成凹槽，并用介电材料填充凹槽，并且然后实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除介电材料的过量部分。硬掩模70可以包括或由氮化硅、氮氧化硅、氮氧化碳-碳氮化物等形成。由此形成FinFET 100。
参考图11，形成蚀刻停止层72。根据本发明的一些实施例，蚀刻停止层72由介电材料形成，该介电材料可以包括氮化硅、碳氧化硅、氮氧化硅、氧化铝等或它们的多层。ILD 74沉积在蚀刻停止层72上方。在图24所示的工艺流程400中，用于形成蚀刻停止层72和ILD 74的工艺被示为工艺424。根据一些实施例，ILD 74由选自用于形成ILD 58的同一组候选材料中的材料形成。
图12A和图12B示出了源极/漏极接触开口76和栅极接触开口78的形成。在图24所示的工艺流程400中，各个工艺被示为工艺424。源极/漏极接触开口76的形成工艺可以包括形成图案化的光刻胶(未示出)以及蚀刻ILD 74、蚀刻停止层72、ILD 60和CESL 58以露出源极/漏极区域54。栅极接触开口78的形成工艺可以包括形成另一图案化的光刻胶(未示出)以及蚀刻ILD 74、蚀刻停止层72和硬掩模70以露出栅电极66。源极/漏极接触开口76和栅极接触开口78可以通过不同的蚀刻工艺形成，或者可以使用普通的蚀刻工艺形成。根据一些实施例，源极/漏极接触开口76是细长的，并且具有垂直于源极-漏极区域方向(Y方向)的长度方向(X方向)。根据一些实施例，可以使用NF3和NH3的混合气体、HF和NH3的混合气体等来蚀刻ILD 74和58。可以使用CF4、O2和N2的混合气体、NF3和O2的混合气体、SF6和O2的混合气体等蚀刻蚀刻停止层72和CESL 58。在形成接触开口76和78之后，可以实施清洁工艺以去除在蚀刻工艺中产生的聚合物。清洁工艺可以使用氧(O2)或H2和N2的混合物实施，并且产生等离子体，然后再使用去离子水实施湿清洁工艺。
图12B示出了图12A中的参考截面12B-12B。根据一些实施例，开口76和78的宽度W1在约12nm和约20nm之间的范围内。开口76和78的长宽比(其为深度与各个宽度的比率)可以在约6和约8之间的范围内。
下一步，参考图13，形成介电间隔件80。形成工艺可以包括沉积毯式介电层，以及通过各向异性蚀刻工艺来蚀刻毯式介电层。毯式介电层可以是共形或基本共形的层，例如，水平部分和垂直部分的厚度具有小于水平厚度约10％的差。可以通过ALD、CVD等实现沉积。介电间隔件80可以由选自SiN、SiON、SiCN、SiC、SiOCN、AlON、AlN、HfOx、它们的组合和/或多层的介电材料形成。介电间隔件80可以帮助防止在随后形成的源极/漏极接触插塞和栅极接触插塞之间的泄漏。介电间隔件80的厚度可以在约1nm和约3nm之间的范围内。
参考图14，沉积金属层82，其延伸至源极/漏极接触开口76和栅极接触开口78两者中。在图24所示的工艺流程400中，各个工艺被示为工艺426。金属层82可以包括或由纯的或基本纯的(例如，超过95％)的Ti、Ta、Ni等或它们的合金形成。金属层82是非共形层，其水平部分的厚度T1大于垂直部分的厚度T2。可以在开口76和78的中间深度处测量厚度T2。根据本发明的一些实施例，比率T1/T2大于5∶1，并且可以在约5∶1和约15∶1之间的范围内。例如，厚度T1可以在约100埃和约150埃之间的范围内。厚度T2可以在约6埃和约20埃之间的范围内。根据本发明的一些实施例，通过物理汽相沉积(PVD)实施沉积。为了获得期望的比率T1/T2，可以在施加偏置功率(和偏置电压)的情况下实施沉积。例如，偏置电压可以大于约150伏，并且可以在约150伏和约300伏之间的范围内。
图15示出了氮化工艺83以形成金属氮化物层84。在图24所示的工艺流程400中，各个工艺被示为工艺428。根据一些实施例，通过在诸如氨(NH3)的含氮工艺气体中处理金属层82来实施氮化工艺。金属氮化物层84可以包括或由TiN、TaN、NiN等或它们的组合形成。可以通过热氮化工艺和/或等离子体氮化工艺实施氮化工艺。金属层82的表面层被转换成金属氮化物层84。金属层82的侧壁部分可以被完全转换。可选地，金属层82的每个侧壁部分的表面层被转换，而金属层82的侧壁部分的内部保持为金属层。金属氮化物层84的水平部分被部分转换，金属氮化物层84与金属层82的剩余部分重叠。根据可选实施例，代替沉积然后氮化金属层，在金属层82上方沉积金属氮化物层84。根据一些实施例，在源极/漏极接触开口76和栅极接触开口78的底部处，金属氮化物层84的厚度T3可以在约4nm和约6nm之间的范围内。
图16示出了通过退火进行的硅化工艺，使得金属层82与源极/漏极区域54反应形成硅化物区域86，该硅化物区域86包括硅化钛、硅化钽、硅化镍等，取决于金属层82中的金属。在图24所示的工艺流程400中，各个工艺被示为工艺430。硅化物区域86的厚度T4可以在约4nm和约6nm之间的范围内。可以通过在约500℃和约600℃之间的范围内的温度下通过退火晶圆10来实施硅化工艺，例如，通过在约10秒和约20秒之间的范围内的时间段。由于硅化工艺，在源极/漏极接触开口76的底部的金属层82的部分被完全硅化，并且因此金属氮化物层84接触硅化物区域86。在栅电极66的顶部上，金属层82仍可以具有剩余在金属氮化物层84的相应部分下面的部分。
参考图17，实施氧化工艺87以形成金属氧化物层88，它可以包括或由TiOx、TaOx、NiOx或它们的组合形成。在图24所示的工艺流程400中，各个工艺被示为工艺432。金属氧化物层88可以在其中包含氮，并且因此可以是金属氧氮化物层，金属氧氮化物被认为是金属氧化物型。例如，在栅极接触开口78中的金属氧化物层88的部分可以包括由金属层82形成的金属氧化物层和由金属氮化物层84形成的金属氧氮化物层，金属氧氮化物层位于金属氧化物层上方并且接触金属氧化物层。另一方面，在源极/漏极接触开口76中、在接触开口76和78的侧壁上以及在ILD层74上方的金属氮化物层84的部分可以全部被完全转换为金属氮氧化物。在源极/漏极接触开口76和栅极接触开口78的每个的底部，金属氮化物层84保持不被氧化。这是通过控制氧化时间和温度来实现的。
可以使用诸如氧(O2)、臭氧(O3)等含氧气体实施氧化。氧化可以通过使用上述工艺气体的热工艺实施，可以产生或不产生等离子体。氧化可以使用从上述工艺气体产生的等离子体实施，氧化期间的晶圆10的温度为室温或更高。在热和/或等离子体氧化工艺期间晶圆10的温度也可以在室温和约250℃之间的范围内，在约160℃和约250℃之间的范围内。含氧气体的流速可以在约2,000sccm和约6,000sccm之间的范围内。氧化持续时间可以在约15秒和约60秒之间的范围内。实施氧化而不施加偏置电压/功率。
在随后的工艺中，通过蚀刻去除金属氧化物层88。在图24所示的工艺流程400中，各个工艺被示为工艺434。根据一些实施例，使用氯基蚀刻气体实施蚀刻。诸如TaCl5、WCl5、WCl6、MoCl5、NbCl5等或它们的组合。蚀刻可以通过热干蚀刻工艺实施，晶圆10的温度在约300℃和约500℃之间的范围内。蚀刻可以在有或没有等离子体的情况下实施。另外，在蚀刻期间，没有引入氢(H2)，并且没有引入NH3。否则，工艺气体可能成为用于沉积金属层而不是用于蚀刻金属氧化物层88的前体。由于蚀刻，金属氧化物层88被完全去除。蚀刻是自限制的，剩余金属氮化物层84充当蚀刻停止层。因此，在源极/漏极接触开口76和栅极接触开口78的每个的底部处留下金属氮化物层84的薄层。剩余金属氮化物层84可以具有在约1nm和约3nm之间的范围内的厚度T5。金属氮化物层84也可以尽可能地薄，如果它们具有源极/漏极接触开口76和栅极接触开口78的底部的完全覆盖。
图18示出了对金属氮化物层84实施的处理工艺。在图24所示的工艺流程400中，各个工艺被示为工艺436。可以使用工艺气体实施处理，将晶圆10浸入工艺气体中。工艺气体可以包括TaCl5、NiCl4、WCl5、MoCl5等或它们的组合。在处理期间，将晶圆10加热至例如在约200℃和约500℃之间范围内的温度。不产生等离子体。处理持续时间可以大于约5秒，并且可以在约5秒和50秒之间的范围内。当TiCl4用作处理工艺气体时，TiCl4浸泡导致所得分子(诸如TiCl3分子)连接至正下方的金属氮化物层84的悬空接合。连接的分子表示为89，如图18所示。另一方面，没有处理气体分子连接至暴露的介电材料的表面，诸如介电间隔件80和介电层74。
图19还示出了使用含硅气体作为前体选择性沉积硅层90，它们可以是SiH4、Si2H6、Si3H8等或它们的组合。在图24所示的工艺流程400中，各个工艺被示为工艺438。沉积可以使用化学汽相沉积(CVD)或其它适用的方法实施。在硅层90的沉积期间，可以将晶圆10加热至例如在约400℃和约550℃之间的范围内的温度。前体的压力可以在约15托和约40托之间的范围内。沉积时间可以在约30秒和约600秒之间的范围内。硅层90可以具有在约1埃和约10埃之间的范围内的厚度，并且厚度可以在约1埃和约10埃之间的范围内，或在约1埃和约5埃之间的范围内。硅层90可以是非晶层。
在形成硅层90并且提供氢的情况下(例如，来自SiH4)，在硅层90的顶面上形成Si-H键。这为后续的金属填充提供了良好的基底，硅层90充当晶种层，用于在源极/漏极接触开口76和栅极接触开口78中选择性地沉积金属。根据可选实施例，不实施基于氯的气体处理和/或硅层90的沉积。根据一些实施例，即使不实施这些工艺，在选择适当的工艺气体的情况下，通过使用金属氮化物层84作为用于选择性沉积的基底，仍可以实现以些自底向上的效果。但是，当形成硅层90时，沉积的选择性更高。其中选择性是硅上金属沉积速率与介电材料上金属沉积速率的比率。
图20示出了金属选择性地自底向上沉积到源极/漏极接触开口76和栅极接触开口78中，使得形成金属区域92。在图24所示的工艺流程400中，各个工艺被示为工艺440。根据一些实施例，金属区域92包括或由铝、钼、钌、铱、钨、钴等或它们的组合形成。金属区域92的整体可以是均匀的。根据其中沉积铝的一些实施例，反应工艺气体包括氢化二甲基铝(DMAH)和氢(H2)。DMAH倾向于选择性地沉积铝，特别是在硅层上。沉积方法可以包括CVD等方法。沉积温度可以在约175℃和约275℃之间的范围内。反应气体的压力可以在约1托和约3托之间的范围内。所得的金属区域92可以完全填充源极/漏极接触开口76和栅极接触开口78，或可以填充为顶面略低于ILD 74顶面。例如，金属区域92的高度可以在约500埃和约1,500埃之间的范围内，取决于源极/漏极接触开口76和栅极接触开口78的深度。
硅层90充当用于沉积金属区域92的晶种层。另一方面，金属没有沉积在暴露的介电材料上，诸如介电间隔件80和ILD 74的表面上。因此，金属区域92的沉积是选择性沉积工艺，并且是自底向上沉积工艺。所得的金属区域92是无接缝的。由于铝对金属氮化物层84、介电间隔件80和ILD 74具有良好的粘附性，因此可以形成金属区域92而无需形成粘附层(阻挡层)(通常由Ti、TiN、Ta、TaN等形成)。因此，所得的接触插塞是无阻挡的。
图23示出了用于实施如图18、图19和图20所示的工艺的生产工具200。生产工具200包括用于装载和卸载晶圆的装载模块110，以及多个工艺室。工艺室包括用于蚀刻金属氧化物(氮氧化物)层88(如图17所示)的室112、用于处理金属氮化物层和沉积硅层90的室114(图19)以及用于沉积金属区域92(图20)的室116。在生产工具200中原位实施金属氧化物层的蚀刻、金属氮化物层84的处理和沉积硅层90以及金属区域92的沉积，使得在这些工艺之间不会发生真空破坏。否则，金属氮化物层84和硅层90的暴露表面可能被氧化，并且随后的沉积工艺可能不是选择性的。
在随后的工艺中，如图20所示的结构经过热工艺以回流金属区域92。在回流工艺期间，氢(H2)可用作工艺气体，使得去除一些不期望的杂质，诸如金属区域92中的碳。在回流中，晶圆10在热工艺中的温度可以在约400℃和约450℃之间的范围内。如果使用的话，金属区域92中的铝可以部分地熔化。由于回流，金属区域92具有多晶结构，并且与回流之前相比，可以有利地增大晶粒尺寸。例如，在回流工艺之前，金属区域中超过75％(晶粒计数百分比)的晶粒具有在约2nm和约8nm之间的范围内的晶粒尺寸。在回流工艺之后，超过75％的晶粒具有落在约9nm和约15nm之间的范围内的晶粒尺寸。此外，通过回流，去除了金属区域92中的接缝或空隙(如果有的话)。
取决于是否实施回流工艺以及取决于后续工艺的温度，硅层90可以(或可以不)与上面的金属区域92反应以形成金属硅化物区域91，根据一些实施例，其可以是硅化铝(AlSiY)区域。因此，标记相应的区域并且将其称为含硅区域90/91，以指示可能存在可区分的硅层90，或者可能存在金属硅化物区域91。根据一些实施例，金属硅化物区域91的厚度在约2埃和约30埃之间的范围内。
参考图21，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除金属区域92的过量部分，使得金属区域92的顶面与ILD 74的顶面共面。在图24所示的工艺流程400中，各个工艺被示为工艺442。由此形成源极/漏极接触插塞94A和栅极接触插塞94B。
根据一些实施例，源极/漏极接触插塞94A包括金属区域94、硅层90或硅化物区域91以及金属氮化物层84。金属氮化物层84覆盖并且接触硅化物区域86。通过处理(使用TiCl4)引入的元素(诸如Ti和Cl)可以在硅层90和金属氮化物层84之间的界面处。而且，硅层90或硅化物区域91可以是可区分的层，或者由于其太薄而可以不是可区分的层，并且还由于后续的热工艺可能导致它的扩散。含硅区域90/91中的硅原子百分比可以是最高的，并且原子百分比在远离含硅区域90/91的方向上减小。类似地，在含硅区域90/91中可能会观察到诸如氯的一些元素(由于TiCl4处理)，这些元素的浓度可能会远离界面区域而降低。例如，图21中的箭头96A和96B示出了氯百分比可以逐渐降低的方向。箭头96A还示出了硅原子百分比降低的方向。然而，应该注意，硅化物区域86中的硅原子百分比可达到峰值。因此，硅原子百分数可以存在两个浓度峰值，第一峰值在硅化物区域86中，第二峰值在硅层90所在的位置。第二峰值可以低于第一峰值。金属氮化物层84中的硅原子百分比可以低于两个峰值中的硅原子百分比。
根据一些实施例，栅极接触插塞94B包括金属区域94、含硅区域90/91和金属氮化物层84。钛层82可以存在或可以不存在。因此，金属氮化物层84的底面或钛层82的底面接触栅电极66。通过处理(使用TiCl4)引入的元素(诸如Ti和Cl)可以在含硅区域90/91和金属氮化物层84之间的界面处。同样，含硅区域90/91可以是可区分的层，或者由于其太薄而可能不是可区分的层，并且进一步由于随后的热工艺可能导致它的扩散。含硅区域90/91中的硅原子百分比可以是最高的，并且原子百分比在远离含硅区域90/91的方向上减小。类似地，在界面区域可能会观察到诸如氯的一些元素，这些元素的浓度可能会远离界面区域而降低。例如，图21中的箭头97示出了硅原子百分比和氯百分比可以逐渐降低的方向。
图22示出了蚀刻停止层122和介电层124的形成。根据一些实施例，蚀刻停止层122包括或由碳化硅、碳氧化硅、氮氧化硅、氧化铝等或它们的多层形成。介电层124可以是低k介电层。形成通孔130和132以延伸至介电层124和蚀刻停止层122中，并且分别接触源极/漏极接触插塞94A和栅极接触插塞94B。通孔130和132中的每个可以包括粘附/阻挡层126和填充金属区域128。粘附/阻挡层126可以由Ti、TiN、Ta、TaN等形成。填充金属区域128可以包括Ru、Ir、Mo、W、Cu等或它们的合金。
本发明的实施例具有一些有利特征。通过氧化金属氮化物层，可以从介电层的侧壁和顶面去除金属氮化物层，而可以将金属氮化物层选择性地留在接触开口的底部。这使得能够选择性地沉积硅层，从而选择性地自底向上沉积金属区域。因此，接触插塞没有接缝。
根据本发明的一些实施例，方法包括蚀刻介电层以在介电层中形成沟槽；沉积延伸至沟槽中的金属层；对金属层实施氮化工艺，以将金属层的上部转换为金属氮化物层；对金属氮化物层实施氧化工艺以形成金属氮氧化物层；去除金属氮氧化物层；以及使用自底向上沉积工艺将金属材料填充至沟槽中以形成接触插塞。在实施例中，在形成沟槽之后，露出介电层下面的源极/漏极区域。在实施例中，该方法还包括在氮化工艺之后和氧化工艺之前，实施退火工艺以使金属层的下部与源极/漏极区域反应以形成硅化物区域。在实施例中，在去除金属氮氧化物层之后，金属氮化物层的底部保留在沟槽的底部。在实施例中，该方法还包括在金属氮化物层的底部上选择性地沉积硅层，其中从硅层选择性地生长金属材料。在实施例中，该方法还包括在选择性沉积硅层之前，使用氯化钛(TiCl4)处理金属氮化物层的底部。在实施例中，对金属氮化物层实施的氧化工艺使得介电层上方的所有金属氮化物层和介电层侧壁上的所有金属氮化物层被氮化，在氧化工艺之后剩余在沟槽底部的金属氮化物层的底部。在实施例中，在相同的真空环境中原位实施去除金属氮氧化物层和填充金属材料。
根据本发明的一些实施例，器件包括接触蚀刻停止层；接触蚀刻停止层上方的第一层间电介质；以及延伸至接触蚀刻停止层和第一层间电介质中的接触插塞，接触插塞包括：金属氮化物层；位于金属氮化物层上方的含硅层；以及位于含硅层上方的均质金属材料。在实施例中，金属氮化物层包括第一金属，并且均质金属材料包括与第一金属不同的第二金属。在实施例中，含硅层包括硅化铝。在实施例中，器件在含硅层和金属氮化物层之间的界面处还包括氯。在实施例中，器件还包括在金属氮化物层正下方的硅化物区域，其中含硅层和金属氮化物层中的第一氯原子浓度高于均质金属材料和硅化物区域中的第二氯原子浓度。在实施例中，金属氮化物层不在均质金属材料的侧壁上延伸。在实施例中，均质金属材料的侧壁与第一层间电介质的侧壁接触。在实施例中，器件还包括位于第一层间电介质上方的蚀刻停止层；以及位于蚀刻停止层上方的第二层间电介质，其中接触插塞还延伸至蚀刻停止层和第二层间电介质中。在实施例中，器件还包括在金属氮化物层下面的金属层；以及在金属层正下方并且接触金属层的栅电极。
根据本发明的一些实施例，器件包括源极/漏极区域；位于源极/漏极区域上方并且接触源极/漏极区域的第一金属硅化物区域；位于第一金属硅化物区域上方并且接触第一金属硅化物区域的接触插塞，该接触插塞包括：金属氮化物层；位于金属氮化物层上方的第二金属硅化物区域；以及位于第二金属硅化物区域上方的铝区域。在实施例中，接触插塞是无阻挡的。在实施例中，该器件还包括接触蚀刻停止层；位于接触蚀刻停止层上方的层间电介质；以及包围并且接触接触插塞的介电间隔件，其中介电间隔件延伸至接触蚀刻停止层和层间电介质两者中。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
蚀刻介电层以在所述介电层中形成沟槽；
沉积延伸至所述沟槽中的金属层；
对所述金属层实施氮化工艺以将所述金属层的上部转换为金属氮化物层；
对所述金属氮化物层实施氧化工艺以形成金属氮氧化物层；
去除所述金属氮氧化物层；以及
使用自底向上沉积工艺将金属材料填充至所述沟槽中以形成接触插塞。
2.根据权利要求1所述的方法，其中，在形成所述沟槽之后，露出所述介电层下面的源极/漏极区域。
3.根据权利要求2所述的方法，还包括在所述氮化工艺之后和所述氧化工艺之前，实施退火工艺以使金属层的下部与源极/漏极区域反应以形成硅化物区域。
4.根据权利要求1所述的方法，其中，在去除所述金属氧氮化物层之后，所述金属氮化物层的底部保留在所述沟槽的底部处。
5.根据权利要求4所述的方法，还包括在所述金属氮化物层的底部上选择性地沉积硅层，其中，从所述硅层选择性地生长所述金属材料。
6.根据权利要求5所述的方法，还包括在选择性地沉积所述硅层之前，使用氯化钛(TiCl4)处理所述金属氮化物层的底部。
7.根据权利要求1所述的方法，其中，对所述金属氮化物层实施的氧化工艺使得所述介电层上方的所有金属氮化物层和所述介电层的侧壁上的所有金属氮化物层被氮化，在所述氧化工艺之后，在所述沟槽底部处的所述金属氮化物层底部剩余。
8.根据权利要求1所述的方法，其中，在相同的真空环境中原位实施去除所述金属氧氮化物层和填充所述金属材料。
9.一种半导体器件，包括：
接触蚀刻停止层；
第一层间电介质，位于所述接触蚀刻停止层上方；以及
接触插塞，延伸至所述接触蚀刻停止层和所述第一层间电介质中，所述接触插塞包括：
金属氮化物层；
含硅层，位于所述金属氮化物层上方；以及
均质金属材料，位于所述含硅层上方。
10.一种半导体器件，包括：
源极/漏极区域；
第一金属硅化物区域，位于所述源极/漏极区域上方并且接触所述源极/漏极区域；以及
接触插塞，位于所述第一金属硅化物区域上方并且接触所述第一金属硅化物区域，所述接触插塞包括：
金属氮化物层；
第二金属硅化物区域，位于所述金属氮化物层上方；以及
铝区域，位于所述第二金属硅化物区域上方。
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KR102495788B1 (ko) 2023-02-07
TWI746141B (zh) 2021-11-11
DE102020101271B4 (de) 2023-04-27
DE102020101271A1 (de) 2021-03-25
US20210090948A1 (en) 2021-03-25
US11469139B2 (en) 2022-10-11
US20220359285A1 (en) 2022-11-10
US20230386917A1 (en) 2023-11-30

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