CN1117396C - 半导体封装体及使用该封装体的半导体模块 - Google Patents

半导体封装体及使用该封装体的半导体模块 Download PDF

Info

Publication number
CN1117396C
CN1117396C CN98105360A CN98105360A CN1117396C CN 1117396 C CN1117396 C CN 1117396C CN 98105360 A CN98105360 A CN 98105360A CN 98105360 A CN98105360 A CN 98105360A CN 1117396 C CN1117396 C CN 1117396C
Authority
CN
China
Prior art keywords
mentioned
package body
semiconductor package
semiconductor
electroconductive component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN98105360A
Other languages
English (en)
Other versions
CN1201257A (zh
Inventor
森隆一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN1201257A publication Critical patent/CN1201257A/zh
Application granted granted Critical
Publication of CN1117396C publication Critical patent/CN1117396C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/055—Folded back on itself
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10462—Flat component oriented parallel to the PCB surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10484—Obliquely mounted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

谋求缩小半导体封装体的安装高度、部件的小型化及减少安装面积和体积。把在一个边(本例为右端)的大致一列上具有多个电极4的半导体元件3装到可弯曲的柔性布线基板9上，在只排列在封装体的一个边的外部连接用开口9b上安装作为外部连接用的导电性部件的焊锡球13。这样构成的半导体封装体8通过弯曲柔性布线基板9能够相对于安装基板7以水平或倾斜状态来连接。另外，在多个半导体封装体8之间夹入散热机构15，还可使其一个靠另一个地放倒重叠。

Description

半导体封装体及使用该封 装体的半导体模块
技术领域
本发明涉及半导体封装体，特别是涉及使从半导体元件的电极到外部连接用端子的长度相等、并仅从封装体的一边引出外部连接用端子的半导体封装体，以及使用该封装体的半导体模块。
背景技术
图11是示出在现有的半导体封装体、例如高速工作的DRAM中被提出和使用的SVP(Surface Vertical Package表面垂直封装)的外观的斜视图，图12是示出其内部的平面图。图中，1表示半导体封装体，2表示外部连接用引线，3表示半导体元件，4表示电极，5表示键合线，6表示管芯底座。本封装体具有外部连接用引线2仅配置在半导体封装体1的一边这样的特征。在封装体内部，电极4沿半导体元件3的一边大致排成一列，外部连接用引线2和电极4用键合线5进行电连接。由于电极4大致排列为一列，而且外部连接用引线2在半导体封装体1中仅配置在最靠近电极4的边上，故成为电布线的长度在哪个电极4中都很短并大致相等的结构。
以这样地仅在半导体封装体的一边配置外部连接用引线为特征的半导体封装体在特开平6-61289号公报、特开平5-21684号公报以及特开平7-321441号公报等中也已提出。在特开平6-61289号公报中，通过在半导体封装体的短边侧排列外部连接用引线并对于安装基板垂直地进行安装，以试图缩小安装面积。还有，在特开平5-21684号公报中，提出了仅从封装体的一边把带有引线的带(tape)延伸到外部，再将其弯曲成“L”形安装到印刷基板上的模块。另外，在特开平7-321441号公报中，提出了这样的半导体封装体，即通过把从半导体封装体的一个方向取出的柔性引线弯曲成任意的角度来充分地确保与布线基板的电极的接触面积，同时还能够对于布线基板垂直地或呈斜方向地进行安装。
近年来，从伴随着便携式电子装置的增加而产生的部件小型化、削减安装面积、体积的需求出发，正在谋求缩小现有的半导体封装体的安装高度。图13是安装图11及图12所示的现有的半导体封装体1时的侧面图。图中，7是安装用基板，H示出封装体的安装高度。现有的半导体封装体1如上述那样来构成，由于对于安装用基板7垂直地进行安装，故封装体的安装高度H增大。在特开平6-61289号公报及特开平5-21684号公报中提出的半导体模块中由于以同样方式相对于安装基板垂直地安装半导体封装体，故也存在安装高度H增大的问题。另外，在特开平7-321441号公报中提出的半导体模块虽然提出了对布线基板沿斜方向安装半导体封装体的方法，但存在由于需要用于支撑半导体封装体的支撑材料故存在部件数增多的问题。
还有，在为了缩小半导体封装体的安装体积而把多个半导体封闭体重叠地安装时，存在高速工作时发热增加，温度过于上升这样的问题，难于实用化。
发明内容
本发明是为消除上述问题点而提出的，目的在于在半导体封装体及装了多个半导体封装体的半导体模块中，得到能够缩小对于安装基板的封装体的安装高度，可实现部件小型化并削减安装面积和体积的半导体封装体以及使用了该封装体的半导体模块。
本发明的第1方面的半导体封装体具有：沿矩形半导体元件的一边配置的多个电极；与该电极电连接的一端接近于电极被配置、而另一端从外部连接用的开口部分露出的多条布线，安装在开口部分上的导电性部件；安装了半导体元件、配置了布线及导电性部件的柔性布线基板；和除去导电性部件之外把半导体元件及其周围密封的密封树脂。
本发明的第2方面的半导体封装体将外部连接用开口部分及导电性部件设置在柔性布线基板的2个面上。
本发明的第3方面的半导体封装体，作为导电性部件使用焊锡或其它金属球或粘接剂等。
本发明的第4方面的半导体模块把多个半导体封装体放倒、重叠并倾斜地安装，使它们一个靠在另一个上。
本发明的第5方面的半导体模块把多个半导体封装体相对于安装基板配置在水平方向上并重叠，并相互在上下与设置在柔性布线基板两面上的同一位置处的导电性部件连接而进行安装。
本发明的第6方面的半导体模块在多个半导体封装体相互间夹入了散热机构。
附图说明
图1是示出本发明实施例1的半导体封装体内部的平面图。
图2是示出本发明实施例1的半导体封装体内部的剖面图。
图3是示出本发明实施例1的半导体封装体的平面图。
图4是示出本发明实施例1的半导体封装体的剖面图。
图5是示出安装本发明实施例1的半导体封装体时的侧面图。
图6是示出本发明实施例1的半导体模块的侧面图。
图7是示出本发明实施例1的半导体模块的侧面图。
图8是示出本发明实施例2的半导体封装体内部的剖面图。
图9是示出本发明实施例2的半导体封装体的剖面图。
图10是示出本发明实施例2的半导体模块的侧面图。
图11是示出现有的半导体封装体外观的斜视图。
图12是示出现有的半导体封装体内部的平面图。
图13是示出安装了现有的半导体封装体时的侧面图。
具体实施方式
实施例1
图1～图4示出本发明实施例1的半导体封装体，图1及图2是示出半导体封装体内部的平面图及剖面图，图3及图4是示出用密封树脂密封后的半导体封装体的平面图及剖面图。图中，3是半导体元件，4是电极，5是键合线，8是半导体封装体，9是柔性布线基板，9a是内部连接用开口，9b是外部连接用开口，10是布线，11是管芯粘接材料，12是密封树脂，13是作为外部连接用的导电性部件的焊锡球，14是切断线。
利用附图说明本实施例的半导体封装体8的构成。半导体元件3具有沿其一边(本例是右端)排成一列的多个电极4，用管芯粘接材料11粘接在可弯曲的柔性布线基板9上。柔性布线基板9具有只从封装体的一边伸出到外部的布线10，布线10从靠近电极4的位置并大致排列为一条直线的内部连接用开口9a和外部连接用开口9b处露出。电极4和内部连接用开口9a之间用键合线5进行连接。图2(a)示出内部连接用开口9a和外部连接用开口9b都配置在柔性布线基板9上表面的情况，图2(b)示出内部连接用开口9a配置在柔性布线基板9的上表面，外部连接用开口9b配置在柔性布线基板9的下表面的情况。
其次，上述那样构成的半导体元件3、键合线5、内部连接用开口9a如图3所示用密封树脂12覆盖住。随后，如图4(a)、(b)所示那样在外部连接用开口9b上安放外部连接用的焊锡球13，用切断线14分离。这样制做的半导体封装体8如图5(a)、(b)所示那样用焊锡球连接到安装用基板7上。图中，h表示封装体的安装高度。若依据本实施例，则通过弯曲柔性布线基板9就能够使封装体的安装高度h低于现有高度。另外，还能够如图6所示的半导体模块那样把多个半导体封装体8放倒重叠使它们一个靠在另一个上而倾斜地安装，这种情况也能够降低安装高度h。
还有，图7是在图6所示的半导体模块中各半导体封装体8之间配置例如散热板等散热机构15的情况。在把多个半导体封装体8一个靠着另一个地安装时，通过在半导体封装体8之间配置散热机构15，可防止来自高速工作的半导体3的高速工作时的发热而引起的温度过度上升。散热机构15在与作为外部连接端子的焊锡球13相反的方向(图中箭头方向)上延伸，能够利用装有该半导体模块的例如计算机等电子装置的风扇(未图示)进行风冷。另外，也可把该散热机构15连接到电子装置的框体上进行散热。
如以上所述，若依据本实施例的半导体封装体8，则由于把半导体元件3装到柔性布线基板9上，因而通过弯曲该柔性布线基板9，能够相对于安装基板7以倾斜状态安装半导体封装体8，能够降低封装体的安装高度h，故可以大幅度地缩小安装体积。
实施例2
下面，根据附图说明本发明的实施例2。图8是示出作为本发明实施例2的半导体封装体的内部的剖面图，图9是示出用密封树脂密封后的状态的剖面图。图中，与图2、图4相同和相当的部分上标注相同的符号，省略其说明。在上述实施例1中，仅在柔性布线基板9的一个面上设置作为外部连接用的导电性部件的焊锡球13，而在本实施例中，在柔性布线基板9的两个面上开有外部连接用开口9b(图8)，把焊锡球13装在两个面上(图9)。
图10示出使用了依据本实施例的半导体封装体的半导体模块。本模块通过把设在柔性布线基板9的两个面上的同一位置处的焊锡球13上下连接，将多个半导体封装体相对于安装基板7在水平方向上进行配置并重叠地进行安装。在如上构成的半导体模块中，在把安装高度h保持为很低的状态下，能够安装多个封装体。另外，通过在封装体之间夹入散热机构15，能够防止来自高速工作的半导体元件3的高速工作时的发热引起的温度过度上升。散热机构15在与作为外部连接端子的焊锡球13相反的方向上延伸(图中箭头方向)，能够利用装有该半导体模块的例如计算机等电子装置的风扇(未图示)进行风冷。另外，也可把该散热机构15连接到电子装置的框体上进行散热。
还有，在上述实施例1及2中，用键合线5连接半导体元件3的电极4和柔性布线基板9的内部连接用开口9a，而也可以采用键合线以外的梁式引线和凸点这样的连接方法。另外，作为外部连接用的导电性部件使用了焊锡球13，但也可以使用其它金属或导电性粘接剂。
还有，电极4、内部连接用开口9a以及外部连接用开口9b分别配置在一条直线上，从电极4到外部连接用开口9b的长度大致保持为一定，然而，如果电极4的排列不在直线上，则分别使内部连接用开口9a和外部连接用开口9b与电极4的排列相一致地移动，也能够使从电极4到外部连接用开口9b的长度保持为一定。另外，作为布线10示出了仅一层的例子，但也可以是多层布线。进而，在本发明的半导体封装体8上还能够设置用于进行与安装基板7的定位的凸起等。
如以上所述，若依据本发明的半导体封装体及半导体模块，则由于把半导体元件装在柔性布线基板上并仅在封装体的一个边配置外部连接用导电性部件，因而通过弯曲柔性布线基板能够相对于安装基板以水平或倾斜状态连接半导体封装体，能够降低封装体的安装高度h，故可以大幅度地缩小安装体积。
还有，由于在多个半导体封装体相互之间设置了散热机构，因此能够防止来自半导体元件的高速工作时的发热引起的温度过度上升。

Claims (6)

1.一种半导体封装体，其特征在于具有：
沿矩形半导体元件的一个边配置的多个电极；
与上述电极电连接的一端接近于上述电极而配置、另一端从外部连接用开口部分露出的多条布线；
装在上述开口部分中的导电性部件；
装了上述半导体部件并配置了上述布线和上述导电性部件的柔性布线基板；和
除去上述导电性部件之外，把上述半导体元件及其周围密封起来的密封树脂。
2.权利要求1所述的半导体封装体，其特征在于：
将外部连接用的开口部分以及导电性部件设置在柔性布线基板的2个面上。
3.权利要求1所述的半导体封装体，其特征在于：
导电性部件是焊锡或其它金属球或粘接剂等。
4.一种半导体模块，其特征在于：
把多个半导体封装体放倒重叠使它们一个靠另一个地倾斜地进行安装，所述半导体封装体具有：
沿矩形半导体元件的一个边配置的多个电极；
与上述电极电连接的一端接近于上述电极而配置、另一端从外部连接用开口部分露出的多条布线；
装在上述开口部分中的导电性部件；
装了上述半导体部件并配置了上述布线和上述导电性部件的柔性布线基板；和
除去上述导电性部件之外，把上述半导体元件及其周围密封起来的密封树脂。
5.一种半导体模块，其特征在于：
把多个半导体封装体相对于安装基板配置在水平方向上并重叠，相互在上下与设在柔性布线基板两个面上的同一位置处的导电性部件连接而进行安装，所述半导体封装体具有：
沿矩形半导体元件的一个边配置的多个电极；
与上述电极电连接的一端接近于上述电极而配置、另一端从外部连接用开口部分露出的多条布线；
装在上述开口部分中的导电性部件；
装了上述半导体部件并配置了上述布线和上述导电性部件的柔性布线基板；和
除去上述导电性部件之外，把上述半导体元件及其周围密封起来的密封树脂。
6.权利要求5所述的半导体模块，其特征在于：多个半导体封装体相互之间夹入了散热机构。
CN98105360A 1997-06-02 1998-03-02 半导体封装体及使用该封装体的半导体模块 Expired - Fee Related CN1117396C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9143724A JPH10335580A (ja) 1997-06-02 1997-06-02 半導体パッケージおよびこれを用いた半導体モジュール
JP143724/97 1997-06-02
JP143724/1997 1997-06-02

Publications (2)

Publication Number Publication Date
CN1201257A CN1201257A (zh) 1998-12-09
CN1117396C true CN1117396C (zh) 2003-08-06

Family

ID=15345532

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98105360A Expired - Fee Related CN1117396C (zh) 1997-06-02 1998-03-02 半导体封装体及使用该封装体的半导体模块

Country Status (6)

Country Link
US (1) US6163070A (zh)
JP (1) JPH10335580A (zh)
KR (1) KR100262723B1 (zh)
CN (1) CN1117396C (zh)
DE (1) DE19801493A1 (zh)
TW (1) TW371357B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2794678B2 (ja) 1991-08-26 1998-09-10 株式会社 半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
DE19900803A1 (de) * 1999-01-12 2000-07-20 Siemens Ag Integrierter Schaltkreis
JP4051531B2 (ja) * 1999-07-22 2008-02-27 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6418033B1 (en) * 2000-11-16 2002-07-09 Unitive Electronics, Inc. Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
JP2002204053A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 回路実装方法、回路実装基板及び半導体装置
JP3603890B2 (ja) 2002-03-06 2004-12-22 セイコーエプソン株式会社 電子デバイス及びその製造方法並びに電子機器
DE10259221B4 (de) * 2002-12-17 2007-01-25 Infineon Technologies Ag Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
DE10308095B3 (de) * 2003-02-24 2004-10-14 Infineon Technologies Ag Elektronisches Bauteil mit mindestens einem Halbleiterchip auf einem Schaltungsträger und Verfahren zur Herstellung desselben
EP1471778A1 (en) * 2003-04-24 2004-10-27 Infineon Technologies AG Memory module having space-saving arrangement of memory chips and memory chip therefor
DE10339890A1 (de) * 2003-08-29 2005-03-31 Infineon Technologies Ag Halbleiterbauelement
JP4199724B2 (ja) 2004-12-03 2008-12-17 エルピーダメモリ株式会社 積層型半導体パッケージ
KR100590477B1 (ko) 2004-12-22 2006-06-19 삼성전자주식회사 마더보드의 가장자리를 이용한 메모리 모듈과 마더보드의접속 구조 및 이에 적합한 구조의 메모리 모듈
US20110051385A1 (en) * 2009-08-31 2011-03-03 Gainteam Holdings Limited High-density memory assembly
US10321580B2 (en) * 2016-07-29 2019-06-11 International Business Machines Corporation Integrated circuit package assembly comprising a stack of slanted integrated circuit packages
CN108022887B (zh) * 2016-11-01 2019-10-18 深圳市中兴微电子技术有限公司 一种柔性封装结构及其制备方法、可穿戴设备

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3931238A1 (de) * 1989-09-19 1991-03-28 Siemens Ag Vielfach-chip-modul und verfahren zu dessen herstellung
US5057907A (en) * 1990-06-11 1991-10-15 National Semiconductor Corp. Method and structure for forming vertical semiconductor interconnection
JPH0465135A (ja) * 1990-07-05 1992-03-02 Matsushita Electric Ind Co Ltd 半導体装置およびその実装構造体
JPH0513666A (ja) * 1991-06-29 1993-01-22 Sony Corp 複合半導体装置
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
JPH05315521A (ja) * 1992-05-12 1993-11-26 Oki Electric Ind Co Ltd 半導体装置
JPH0661289A (ja) * 1992-08-07 1994-03-04 Mitsubishi Electric Corp 半導体パッケージ及びこれを用いた半導体モジュール
FR2694840B1 (fr) * 1992-08-13 1994-09-09 Commissariat Energie Atomique Module multi-puces à trois dimensions.
JP2565091B2 (ja) * 1993-07-01 1996-12-18 日本電気株式会社 半導体装置およびその製造方法
JPH0794551A (ja) * 1993-09-25 1995-04-07 Nec Corp 半導体装置
JPH07321441A (ja) * 1994-05-24 1995-12-08 Hitachi Ltd 電子回路装置
JP2616565B2 (ja) * 1994-09-12 1997-06-04 日本電気株式会社 電子部品組立体
JP2780649B2 (ja) * 1994-09-30 1998-07-30 日本電気株式会社 半導体装置
US5598033A (en) * 1995-10-16 1997-01-28 Advanced Micro Devices, Inc. Micro BGA stacking scheme
JP3224978B2 (ja) * 1995-10-27 2001-11-05 富士通株式会社 半導体装置
US6011694A (en) * 1996-08-01 2000-01-04 Fuji Machinery Mfg. & Electronics Co., Ltd. Ball grid array semiconductor package with solder ball openings in an insulative base
JP3644662B2 (ja) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール

Also Published As

Publication number Publication date
CN1201257A (zh) 1998-12-09
KR100262723B1 (ko) 2000-08-01
JPH10335580A (ja) 1998-12-18
TW371357B (en) 1999-10-01
US6163070A (en) 2000-12-19
DE19801493A1 (de) 1998-12-03
KR19990006272A (ko) 1999-01-25

Similar Documents

Publication Publication Date Title
CN1117396C (zh) 半导体封装体及使用该封装体的半导体模块
CN1302542C (zh) 模块部件
CN1109362C (zh) 功率晶体管模块的组装结构
CN1227956C (zh) 柔性布线板及其制造方法和带有柔性布线板的显示装置
US5747363A (en) Method of manufacturing an integrated electro-optical package
CN1258098A (zh) 背面电极型电子部件和将其装于印刷电路板上的电子组件
US6768191B2 (en) Electronic component with stacked electronic elements
CN1552099A (zh) 模块部件
US6556268B1 (en) Method for forming compact LCD packages and devices formed in which first bonding PCB to LCD panel and second bonding driver chip to PCB
EP3576143A1 (en) Film package and package module including the same
CN1268246A (zh) 树脂密封型半导体装置及其制造方法
CN1870256A (zh) 连接主装置元件的带自动键合封装
CN1215919A (zh) 半导体装置
CN1901179A (zh) 带布线基板以及利用该基板的薄膜上芯片封装
CN1574309A (zh) 堆栈型半导体装置
CN1317827A (zh) 半导体器件和采用半导体器件的液晶模块
CN1893063A (zh) 堆叠型封装
CN1977394A (zh) 发光二极管模块
CN1585591A (zh) 半导体芯片安装用挠性布线基板及半导体芯片的安装方法
CN1299230A (zh) 低侧面的互联结构
CN1521841A (zh) 半导体器件
CN1231507A (zh) 集成电路芯片、集成电路结构体、液晶装置和电子装置
US5703326A (en) Connection of electrical leads in electroluminescent light by means of parallel connection to a plurality of conductors
CN1149673C (zh) 带载组合件
CN1708206A (zh) 芯片部件安装体和半导体装置

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20030806

Termination date: 20100302