CN1893063A - 堆叠型封装 - Google Patents

堆叠型封装 Download PDF

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CN1893063A
CN1893063A CNA2006101031784A CN200610103178A CN1893063A CN 1893063 A CN1893063 A CN 1893063A CN A2006101031784 A CNA2006101031784 A CN A2006101031784A CN 200610103178 A CN200610103178 A CN 200610103178A CN 1893063 A CN1893063 A CN 1893063A
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substrate
vertical rod
stacked
chip
encapsulation
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CN100524740C (zh
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姜泰敏
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本发明的堆叠型半导体基板使用刚性的、C形的引导基板，该引导基板固定适当堆叠的半导体基板，并且提供了堆叠的半导体和封装的接触表面之间的信号路径。该C形的引导基板消除了由于现有技术的引导线所导致的短路。

Description

堆叠型封装
技术领域
本发明涉及堆叠型半导体封装。更特别地，本发明涉及在芯片和基板之间提供了简化的电连接的堆叠型封装。
背景技术
通常，半导体成品的尺寸和重量部分地由封装决定。随着电子产品已经不断微型化，在电子产品中安装半导体器件的空间已经被进一步缩小。另一方面，由于电子产品变得越来越进步且具有多功能，当前的趋势是增加半导体器件的种类和数量以支持多功能、高性能的电子产品。针对该趋势，已经为半导体器件开发了小、薄、轻的堆叠型封装以增加单位体积的安装效率。
图1示出了现有技术的堆叠型封装。如可以看到的，多个封装、器件或芯片12彼此堆叠。通过沉积在基板11上表面上以及每个连续的芯片12之间的粘结剂15，将芯片12保持在彼此适当的位置。如图1所示，引线13在芯片12和基板11的接触点之间延伸，并且适当地接合来将芯片12电连接到基板11。芯片12和引线13然后被使用环氧树脂模制化合物(EMC)14覆盖模制，以在芯片12和引线13上方提供保护盖或保护层。在基板11的底面或下表面上的焊球17使得该堆叠型封装10能够安装在印刷电路板(未示出)上。参考标号16指代芯片12表面上的接触凸点，通过这些凸点一个芯片12可以电连接到另一个芯片，但是如上构造的堆叠型封装10需要足够的引线13以将芯片12连接到基板11。不幸的是，随着引线13的数量增加，它们纠缠的可能性增加了，短路的可能性增加，而由此导致器件堆叠失效。
发明内容
考虑到上述问题，本发明的目的是提供一种改进的堆叠型基板，该堆叠型基板除其它方面之外可以防止或减小在封装中堆叠在一起的芯片的短路故障。
为了实现本发明的这些目的，提供了一种堆叠型封装，其包括：基板；多个引导基板对，一对引导基板堆叠在另一对引导基板之上，从而每对引导基板设置在所述基板的一个表面的相对侧从而彼此相对；多个芯片，每个芯片设置在引导基板对之间；以及设置在所述基板的另一个表面上的焊球。
每对引导基板包括一对彼此相对的水平杆以及连接到水平杆的垂直杆，引导基板通常具有字母“C”的形状，其中水平杆具有形成在每个水平杆的相对表面上的接触垫，垂直杆具有形成在所述垂直杆中的通孔。
而且，在一个实施例中，垂直杆具有形成在所述通孔内表面上的导电层。
带有通孔的垂直杆具有安装在所述垂直杆的一侧上的卡环，以及具有从所述垂直杆另一侧上的导电层形成的卡扣突起。
每个芯片具有与所述引导基板的接触垫接触的芯片垫。
附图说明
结合附图，从下面的详细说明，本发明的上述和其它目的、特征和优点将变得更加清楚，在附图中：
图1是示出了传统的堆叠型封装的剖面图；
图2是示出了根据本发明的实施例的堆叠型封装的剖面图；
图3是示出图2所示的堆叠型封装中引导基板和芯片的组合的部分剖面图。
具体实施方式
下面将参考附图对本发明的优选实施例进行说明。
图2是示出了根据本发明的实施例的堆叠型封装的剖面图，且图3是示出图2所示的堆叠型封装中引导基板和芯片的组合的部分剖面图。
这里，用于密封和保护芯片的环氧树脂模制化合物(EMC)是本领域中公知的，因此为了清楚和简洁起见，说明书和附图中省略了对EMC的说明。
参考图2和3，堆叠型封装100包括基板110、多个引导基板120、多个芯片130和焊球140。
引导基板120是成对的，并且一对堆叠在另一对上，从而每一对引导基板120设置在基板110的表面的两侧或两端以彼此相对或面对。半导体芯片130布置在每对引导基板120之间。引导基板120成对地制备和多层堆叠。这样，几个芯片130可以堆叠在彼此顶上，只要在它们被堆叠时设置在引导基板120对之间即可。
如图3所示，每个引导基板120具有类似或使人联想到字母“C”的形状。在图3所示的实施例中，成对的水平杆120a与垂直杆120b一体形成，并且与垂直杆120b正交地延伸。垂直杆120b被定制并且水平杆120a连接到垂直杆120b，使得水平杆120a之间的间距或分隔允许芯片130可以插入到水平杆120a之间的间距中。水平杆120a的长度与垂直杆120b的长度赋予引导基板120类似或暗示字母“C”的形状。
一个或两个水平杆120a提供有一个或多个接触垫121。如图3所示，该接触垫基本上呈半球形，并且如图所示接近水平杆120a的远端。其它实施例具有其它形状的接触垫。接触垫121固定插入到C形状的引导基板120中的芯片130，并且与在芯片130下表面上提供的相应的芯片垫或表面131电接触，但是其也可以设置在芯片130的上表面上或在两个表面上。
垂直杆120b具有形成在其中的通孔或管122，界定通孔122的内表面具有形成于其上的导电层123。通孔122中的导电层123提供了彼此堆叠的芯片130之间的电连接。
如图所示，卡环150安装在具有通孔122的开口的垂直杆120b的一端上，并且铜层123从垂直杆120b的另一端延伸出来从而形成卡扣突起124。当多个引导基板120彼此堆叠时，卡环150和卡扣突起124用于引导基板120的组合，引导基板120彼此耦合使得卡扣突起124固定地插入到卡环150中。
每个芯片130插入在相对的引导基板120之间，并且与其它引导基板120相组合。每个芯片具有在其表面上的芯片垫131，芯片垫131与引导基板120的接触垫121接触，从而芯片垫131将芯片130与引导基板120电接触。
在具有上述结构的堆叠型封装中，芯片130固定到引导基板120，并且基板和芯片130之间的电连接通过使用接触垫121来实现，接触垫121设置在引导基板120上，而没有使用如制造堆叠型基板的传统方法中所使用的引线。使用如图2和3所示的结构，可以避免现有技术中的堆叠型基板中所使用的引线纠缠所导致的短路，这将防止芯片和/或封装的故障。
在如上所述的根据本发明的堆叠型封装中，引导基板用于堆叠在其上的芯片，接触垫还设置在引导基板上以进行芯片和引导基板之间的电接触，由此防止由于芯片和基板之间的电连接介质所导致的短路，防止了封装的故障，并且提高了封装的可靠性。
虽然出于说明的目的已经说明了本发明的优选实施例，但是本领域的普通技术人员将理解可以有各种变形、增加和替换，而不脱离权利要求所公开的本发明的精神和范围。

Claims (5)

1、一种堆叠型封装，包括：
基板；
多个引导基板对，一对堆叠在另一对之上，使得每对引导基板设置在所述基板的一个表面的相对侧上从而彼此相对；
多个芯片，每个芯片设置在引导基板对之间；以及
设置在所述基板的另一个表面上的焊球。
2、根据权利要求1的堆叠型封装，其中，每对引导基板包括成对的水平杆，所述水平杆附着到垂直杆并且从所述垂直杆延伸，所述水平杆从所述垂直杆的延伸和长度赋予所述引导基板字母“C”的形状，至少一个水平杆具有形成在所述水平杆的第一表面上的接触垫，所述垂直杆具有形成在所述垂直杆中的通孔。
3、根据权利要求1的堆叠型封装，其中，所述垂直杆具有形成在所述通孔内表面上的导电层。
4、根据权利要求3的堆叠型封装，其中，带有通孔的垂直杆具有安装在所述垂直杆的一侧上的卡环，以及具有从所述垂直杆另一侧上的导电层形成的卡扣突起。
5、根据权利要求2的堆叠型封装，其中，每个芯片具有与所述引导基板的接触垫接触的芯片垫。
CNB2006101031784A 2005-07-07 2006-07-07 堆叠型封装 Expired - Fee Related CN100524740C (zh)

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CN102074537B (zh) * 2008-05-15 2013-02-13 南茂科技股份有限公司 芯片封装单元
US8674482B2 (en) 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
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JP2007019484A (ja) 2007-01-25
KR20070006112A (ko) 2007-01-11
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US7391106B2 (en) 2008-06-24
US20070007652A1 (en) 2007-01-11
CN100524740C (zh) 2009-08-05

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