JP4845600B2 - 積層型パッケージ - Google Patents
積層型パッケージ Download PDFInfo
- Publication number
- JP4845600B2 JP4845600B2 JP2006158464A JP2006158464A JP4845600B2 JP 4845600 B2 JP4845600 B2 JP 4845600B2 JP 2006158464 A JP2006158464 A JP 2006158464A JP 2006158464 A JP2006158464 A JP 2006158464A JP 4845600 B2 JP4845600 B2 JP 4845600B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- vertical bar
- guide
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Combinations Of Printed Boards (AREA)
Description
110 基板
120 ガイド基板
120a 水平バー
120b 垂直バー
121 コンタクトパッド
122 ビアホール
123 銅層
124 スナップ突起
130 チップ
131 チップパッド
140 ソルダーボール
150 スナップリング
Claims (2)
- 基板と、
前記基板の一方の面の両側端部に、対向させて一対ずつ積層された複数のガイド基板と、
対向する一対の前記ガイド基板間の各々に固定された複数のチップと、
前記基板の他方の面に設けられたソルダーボールとを備え、
前記ガイド基板が、対向する一対の水平バーと前記水平バーを連結する垂直バーとが一体に形成された“コ”の字形状であり、
前記水平バーの対向する面の各々にコンタクトパッドが形成され、
前記垂直バーの内部にビアホールが形成され、
前記ビアホールを形成する前記垂直バーの内壁面に銅層が形成され、
前記ビアホールが形成された前記垂直バーの一端の面にはスナップリングが装着され、
前記垂直バーの他端の面には前記銅層に接続されて形成されたスナップ突起が設けられていることを特徴とする積層型パッケージ。 - 前記チップに前記コンタクトパッドと接触するようにチップパッドが設けられることを特徴とする請求項1に記載の積層型パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050061175A KR100668857B1 (ko) | 2005-07-07 | 2005-07-07 | 적층형 패키지 |
KR10-2005-0061175 | 2005-07-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007019484A JP2007019484A (ja) | 2007-01-25 |
JP4845600B2 true JP4845600B2 (ja) | 2011-12-28 |
Family
ID=37597728
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006158464A Expired - Fee Related JP4845600B2 (ja) | 2005-07-07 | 2006-06-07 | 積層型パッケージ |
Country Status (4)
Country | Link |
---|---|
US (1) | US7391106B2 (ja) |
JP (1) | JP4845600B2 (ja) |
KR (1) | KR100668857B1 (ja) |
CN (1) | CN100524740C (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5177625B2 (ja) | 2006-07-11 | 2013-04-03 | 独立行政法人産業技術総合研究所 | 半導体チップの電極接続構造および導電部材、並びに半導体装置およびその製造方法 |
KR101125144B1 (ko) * | 2007-03-20 | 2012-03-23 | 가부시키가이샤 니혼 마이크로닉스 | 적층형 패키지 요소, 적층형 패키지 요소의 단자 형성방법, 적층형 패키지, 및 적층형 패키지의 형성방법 |
JPWO2008142764A1 (ja) * | 2007-05-18 | 2010-08-05 | 株式会社日本マイクロニクス | 積層型パッケージ、及び、積層型パッケージの形成方法 |
US7990171B2 (en) * | 2007-10-04 | 2011-08-02 | Samsung Electronics Co., Ltd. | Stacked semiconductor apparatus with configurable vertical I/O |
CN102074537B (zh) * | 2008-05-15 | 2013-02-13 | 南茂科技股份有限公司 | 芯片封装单元 |
US7973310B2 (en) * | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
US8674482B2 (en) * | 2008-11-18 | 2014-03-18 | Hong Kong Applied Science And Technology Research Institute Co. Ltd. | Semiconductor chip with through-silicon-via and sidewall pad |
WO2010057339A1 (en) * | 2008-11-19 | 2010-05-27 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Semiconductor chip with through-silicon-via and sidewall pad |
TWI466278B (zh) * | 2010-04-06 | 2014-12-21 | Kingpak Tech Inc | 晶圓級影像感測器構裝結構及其製造方法 |
CN103000608B (zh) * | 2012-12-11 | 2014-11-05 | 矽力杰半导体技术(杭州)有限公司 | 一种多组件的芯片封装结构 |
CN103199071A (zh) * | 2013-03-29 | 2013-07-10 | 日月光半导体制造股份有限公司 | 堆迭式封装结构及其制造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5963427A (en) * | 1997-12-11 | 1999-10-05 | Sun Microsystems, Inc. | Multi-chip module with flexible circuit board |
KR200182574Y1 (ko) * | 1997-12-30 | 2000-06-01 | 김영환 | 적층형 패키지 |
JP2000216330A (ja) | 1999-01-26 | 2000-08-04 | Seiko Epson Corp | 積層型半導体装置およびその製造方法 |
JP2001085600A (ja) * | 1999-09-16 | 2001-03-30 | Seiko Epson Corp | 半導体チップ、マルチチップパッケージ、半導体装置、並びに電子機器 |
JP3879351B2 (ja) | 2000-01-27 | 2007-02-14 | セイコーエプソン株式会社 | 半導体チップの製造方法 |
JP2002329835A (ja) * | 2001-05-02 | 2002-11-15 | Sony Corp | 導通接続部品、その製造方法及び半導体装置 |
JP2003007964A (ja) * | 2001-06-22 | 2003-01-10 | Mitsubishi Electric Corp | 積層半導体装置およびその製造方法 |
JP4208840B2 (ja) * | 2002-12-17 | 2009-01-14 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
-
2005
- 2005-07-07 KR KR1020050061175A patent/KR100668857B1/ko not_active IP Right Cessation
-
2006
- 2006-06-07 JP JP2006158464A patent/JP4845600B2/ja not_active Expired - Fee Related
- 2006-06-09 US US11/449,990 patent/US7391106B2/en not_active Expired - Fee Related
- 2006-07-07 CN CNB2006101031784A patent/CN100524740C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20070006112A (ko) | 2007-01-11 |
JP2007019484A (ja) | 2007-01-25 |
CN100524740C (zh) | 2009-08-05 |
US7391106B2 (en) | 2008-06-24 |
CN1893063A (zh) | 2007-01-10 |
US20070007652A1 (en) | 2007-01-11 |
KR100668857B1 (ko) | 2007-01-16 |
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