CN1585591A - 半导体芯片安装用挠性布线基板及半导体芯片的安装方法 - Google Patents
半导体芯片安装用挠性布线基板及半导体芯片的安装方法 Download PDFInfo
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Abstract
一种半导体芯片安装用挠性布线基板。该挠性布线基板(10)具有,在绝缘基片(11)上与半导体芯片的输出端子电连接的形成规定图形的布线(12a、12b)。而且形成有由同一形式的布线(12a)形成了一个图形的第一布线区域(12A)和由同一形式的布线(12b)形成了一个图形的第二布线区域(12B)。此挠性布线基板(10)在不同布线形式的相邻布线区域(12A、12B)之间,形成有用于消除因布线形式的差异所造成的连接不良的图形过渡区域(13)。由此,当在形成有不同布线形式的多种由同一形式的布线形成一个图形的布线区域的挠性基板上进行半导体芯片的输出端子的连接时,可消除布线与输出端子之间的连接不良。
Description
技术领域
本发明涉及一种挠性布线基板、半导体芯片安装用性布线基板、显示装置、半导体芯片安装方法。
背景技术
对于便携式电话机或PDA(Personal Digital Assistant:便携式信息终端设备)等要求小型、轻量、高性能化的电子设备,要求其提高电子部件在印刷电路板上的安装密度。特别是对于安装在这种电子设备上的薄型扁平屏幕显示装置,希望其显示画面尽可能大,所以要求提高配置在其周边的驱动布线部件的安装密度,为了满足该要求,通过将挠性布线基板的布线直接与半导体芯片的输出端子连接,将半导体芯片安装在挠性布线基板上的COF(薄膜芯片Chip On Film),近年来得到了广泛应用。
在该COF中,需要对应半导体芯片的输出端子(焊盘)的图形而在挠性布线基板上形成布线图形。作为此时的挠性布线基板的图形形成技术,多采用下述专利文献1记载的被称为半添加法或全添加法的技术。
根据图1说明该现有技术,首先,如该图(a)所示,在挠性绝缘基片100的表面上形成成为引线镀层的晶种层101,然后如该图(b)所示,为了形成所期望的布线图形,在晶种层101的表面上形成使用光致抗蚀剂材料等的掩模图形102。并且,如该图(c)所示,利用电镀法在露出晶种层101的区域覆盖镍、铜等导电性材料,形成布线图形103,根据需要,在这些布线图形103的表面上,利用电镀法或溅射法或蒸镀等成膜法形成使用金等异种金属的表面导电层104。并且,如该图(d)所示,通过去除掩模图形102和位于其底部的晶种层101,在绝缘基片100上形成具有由晶种层部分101A、布线图形103、表面导电层104构成的所期望的布线图形的挠性布线基板。
另一方面,半导体芯片的输出端子(焊盘)的排列图形虽然是根据驱动对象的电子设备的端子排列和半导体芯片内部的电路块的结构决定的,但一般不排列成相同图形的端子形式,而多数情况是排列大小不同的焊盘,而且是排列成相同大小的焊盘相对集中、形成大小焊盘不均匀的状态。
专利文献1 2000-286536号公报
在安装了具有上述的不同大小焊盘的半导体芯片的COF中,为了高精度地将焊盘与挠性布线基板上的布线连接,需要对应焊盘的大小形成不同布线宽度的布线图形。这种布线图形的形成,在以驱动电流的大小将大大影响设备性能的电子设备为对象的情况下,将成为重要的设计项目。特别是近年来作为自发光型平板显示器而被注目的有机EL显示装置,由于驱动电流的大小直接影响显示性能,所以在与其连接的挠性布线基板上必须设计上述布线图形。
但是,采用现有技术所示的布线图形形成技术来形成这种不同宽度的布线图形时,明显存在以下的问题。
即,如果通过电镀形成不同宽度的布线图形,则产生在宽度较宽的布线上覆盖的布线材料厚、在宽度较窄的布线上覆盖的布线材料薄的现象。其原因是在进行电镀时,宽度较宽的布线与宽度较窄的布线相比,因电阻形成的电位下降小,但如果布线图形中产生这种厚度差,则在通过各向异性导电膜利用热压接来将挠性布线基板的布线图形与半导体芯片的焊盘连接时,存在着在相邻布线之间的形成阶梯的部分的周边容易产生压接不良的问题。
下面,结合图2所示示例进行更具体地说明。在挠性布线基板1上,形成由与宽度较宽的布线1a相同形式的布线形成一个图形的第1布线区域1A,并且形成由与宽度较窄的布线1b相同形式的布线形成一个图形的第2布线区域1B。另一方面,在半导体芯片2上,形成由与宽度较宽的焊盘2a相同形式的焊盘形成一个图形的第1焊盘区域2A,并且形成由与宽度较窄的焊盘2b相同形式的焊盘形成一个图形的第2焊盘区域2B。布线1a和焊盘2a或布线1b和焊盘2b分别具有大致相同的宽度且具有相同图形,通过各向异性导电膜3相互对接,在加热状态下施加压力P进行热压接。
此处,在第1布线区域1A和第2布线区域1B的相邻部位,如上所述,根据布线宽度而产生布线厚度差异,成为在布线接触面形成有阶梯差的状态。如果在该状态下进行热压接,在形成阶梯差的部分的周边部分A,由于该阶梯差的影响,不能施加上充足的压力,在该周边部分A产生压接不良,发生连接不良的问题。
为了消除该问题,只要使第1布线区域1A的布线1a和第2布线区域1B的布线1b的厚度相同即可,但是为了使不同形式的布线厚度成为相同厚度需要特殊的加工处理,致使挠性布线基板的成本升高,并且还有对微细的布线图形实施加工处理相当困难的问题。
发明内容
本发明将解决这种问题作为课题之一。即,本发明的目的是,向对各种不同布线形式形成了多个利用相同形式的布线形成一个图形的布线区域的挠性布线基板连接半导体芯片的输出端子时,不使布线和输出端子之间产生连接不良,针对具有不同大小的输出端子的半导体芯片,通过形成与其相适应的布线图形来获得高精度的连接,由此,消除因连接电阻的偏差造成的驱动电流的不均,确保电子设备、特别是驱动电流的大小直接影响显示性能的有机EL显示装置的良好性能等。
为了达到上述目的,本发明至少具备以下各发明的结构。
本发明提供一种挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于,对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域。
本发明还提供一种半导体芯片的安装方法,通过将半导体芯片的规定图形的输出端子和与挠性布线基板的所述输出端子对应的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于,使用对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板,使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接。
附图说明
图1是现有技术(挠性布线基板的图形形成技术)的说明图。
图2是说明现有技术的问题的说明图。
图3是表示本发明实施方式的挠性布线基板的说明图。
图4是表示本发明实施方式的半导体芯片安装用挠性布线基板的说明图。
图5是表示本发明其他实施方式的半导体芯片安装用挠性布线基板的说明图。
图6是表示本发明其他实施方式的半导体芯片安装用挠性布线基板的说明图。
图7是表示作为设置有本发明实施方式的半导体芯片安装用挠性布线基板的电子设备的一例的显示装置的俯视图。
图中:10挠性布线基板;11绝缘基片;12a、12b、12c、12d布线;12e、12f虚拟布线;12A、12B布线区域;13图形过渡区域;20半导体芯片;21a、21b、21c焊盘(输出端子);21A、21B焊盘区域;30各向异性导电膜;40显示装置;40A引出电极;50PWB。
具体实施方式
以下,参照附图说明本发明的实施方式。图3是表示本发明的一实施方式的挠性布线基板的说明图。挠性布线基板10具有在绝缘基片11上与半导体芯片的输出端子电连接的规定图形的布线12a、12b。并且,形成有由相同形式的布线12a形成了一个图形的第1布线区域12A,形成有由相同形式的布线12b形成了一个图形的第2布线区域12B。作为布线区域12A、12B,不限于图示的两种形式,只要按照每个不同的布线形式形成多个布线区域即可。
在图示示例中,布线形式的差异是基于布线宽度的布线厚度的差异,布线12a是宽度较宽的厚布线,布线12b是宽度较窄的薄布线。因此,在布线区域12A和布线区域12B的相邻部位,根据布线宽度在布线厚度上产生差异,成为在布线的接触面形成有阶梯差t的状态。
在这种挠性布线基板10中,在本发明的实施方式中是在布线形式不同的相邻的布线区域12A、12B之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域13。
作为该图形过渡区域13,在图3所示实施方式中,形成具有比相邻的布线区域12A、12B的各布线间距P1、P2都宽的布线间隔P的区域。
图4表示在这种挠性布线基板10的布线12a、12b电连接作为半导体芯片20的输出端子的焊盘21a、21b的半导体芯片安装用挠性布线基板。
此处,半导体芯片20具有大小不同的焊盘21a、21b,形成由与宽度较宽的焊盘21a相同形式的焊盘形成了一个图形的第1布线区域21A,并且形成由与宽度较窄的焊盘21b相同形式的焊盘形成了一个图形的第2布线区域21B。因此,挠性布线基板10的布线12a、12b的布线形式形成为对应焊盘21a、21b的大小具有不同的布线宽度的状态。并且,该布线12a和焊盘21a或布线12b和焊盘21b分别通过各向异性导电膜30相互对接,通过在加热状态下加压并进行热压接。另外,此处利用隔着各向异性导电膜30的热压接来进行布线12a和焊盘21a或布线12b和焊盘21b的电连接,但不限于此,也可以利用共晶接合或环氧树脂接合、金属接合等其他接合来实施电连接。
根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,通过形成上述的图形过渡区域13,使位于相邻部位的布线12a和布线12b形成为相互隔开间隔P,利用该间隔P吸收阶梯差t,所以各布线区域12A、12B的所有布线12a、12b可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、21b良好连接。
图5是表示本发明的其他实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的说明图。对和上述实施方式相同的部分赋予相同符号,并省略一部分重复说明。在该实施方式中,使图形过渡区域13成为形成有具有相邻的布线区域12A、12B的各布线形式的中间形式的布线12c、12d的区域。此处,示出了在图形过渡区域13形成两个布线12c、12d的示例,但只要至少形成对应焊盘21b的一个布线即可。
并且,该布线12c、12d是布线区域12A、12B的布线12a、12b的中间形式,所以此处形成宽度和厚度为布线12a和布线12b的中间尺寸的布线。
根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,利用形成于图形过渡区域13的中间形式的布线12c、12d分阶段地吸收阶梯差t的影响,所以各布线区域12A、12B以及图形过渡区域13的所有布线12a、12b、12c、12d可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、21b良好连接。
图6是表示本发明的其他实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的说明图。对和上述实施方式相同的部分赋予相同符号,并省略一部分重复说明。在该实施方式中,使图形过渡区域13成为形成有信号传输中不使用的虚拟布线12e、12f的区域。
即,在半导体芯片20侧形成在形式不同的焊盘区域21A和21B之间不进行布线连接的虚拟端子即焊盘21c,由此使与其对应形成的图形过渡区域13的布线12e、12f成为虚拟布线。
根据该实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板,使形成于因阶梯差t的影响容易形成压接不良的图形过渡区域13的虚拟布线12e、12f和与其对应的焊盘12c处于不使用状态,所以实际使用的各布线区域12A、12B的所有布线12a、12b可以在没有阶梯差t的影响的情况下与半导体芯片20的焊盘21a、21b良好连接。
下面,说明采用了上述的各实施方式的挠性布线基板10或在该挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板的半导体芯片的安装方法。使用所述的各实施方式的挠性布线基板10,使半导体芯片20的焊盘21a、21b的图形与布线区域12A、12B的各布线12a、12b的图形对应,在布线12a、12b和焊盘21a、21b之间隔着各向异性导电膜30,对挠性布线基板10和半导体芯片20进行热压接。
此时,挠性布线基板10的布线区域12A、12B的布线图形可以根据半导体芯片20的焊盘图形,利用上述的半添加法或全添加法来形成。
并且,象上述的图3或图4所示实施方式的挠性布线基板10那样,在将图形过渡区域13形成为间隔P的情况下,在形成布线图形时,只要隔开布线形式不同的相邻部位的间隔来形成间隔P即可。此时,半导体芯片20侧的焊盘图形可以根据具有间隔P的布线图形来设计焊盘图形,或者可以不考虑间隔P来形成焊盘图形自身,使对应间隔P的部位的焊盘成为虚拟端子。
另外,象上述的图5所示实施方式的挠性布线基板10那样,在图形过渡区域13形成中间形式的布线12c、12d的情况下,在形成布线图形时,可以通过在布线形式不同的相邻部位形成中间宽度的掩模图形来形成布线12c、12d。
另外,象上述的图6所示实施方式的挠性布线基板10那样,在图形过渡区域13形成虚拟布线12e、12f时,可以仅使挠性布线基板10侧的布线图形自身单纯地对应半导体芯片20的焊盘图形来形成。通过连接挠性布线基板10和半导体芯片20,形成作为与成为半导体芯片20的虚拟端子的焊盘21c对应的布线的虚拟布线12e、12f。
这种挠性布线基板10侧的布线图形的变更可以通过形成布线图形时的掩模图形的设计来简单进行,所以本发明的实施方式的半导体芯片的安装方法与现有技术相比,在成本方面不会产生大的负担。
图7是表示设置有安装了上述实施方式的半导体芯片的挠性布线基板的电子设备的一例的显示装置的俯视图。此处,表示将向挠性布线基板10安装了半导体芯片20的半导体芯片安装用挠性布线基板(COF)连接有机EL显示装置、液晶显示装置(LCD)、电场放射显示装置(FED)、等离子显示装置(PDP)等的平板显示装置40的一例。该半导体芯片安装用挠性布线基板可以连接形成于显示装置40的一边的引出电极40A,并且可以连接PWB(硬质基板)50等的其他电路部件。
根据这种设置有本实施方式的半导体芯片安装用挠性布线基板的显示装置,在COF中采用与半导体芯片的焊盘形式相符的挠性布线基板的布线形式,可以高精度地连接各焊盘和布线,所以能够向显示装置提供所设定的没有偏差的驱动电流。由此,特别是在驱动电流的大小直接影响显示性能的有机EL显示装置中,能够获得良好的显示性能。
如上所述,根据本发明的实施方式,在向按照每个不同布线形式形成有多个由相同形式的布线形成了一个图形的布线区域的挠性布线基板连接半导体芯片的输出端子时,可以消除布线与输出端子之间的连接不良。并且,针对具有不同大小的输出端子的半导体芯片,通过形成与其相适应的布线图形,可以获得高精度的连接。另外,由此消除因连接电阻的偏差造成的驱动电流的不均,确保特别是驱动电流的大小直接影响显示性能的有机EL显示装置的良好的显示性能。
Claims (13)
1.一种挠性布线基板,具有与半导体芯片的输出端子电连接的规定图形的布线,其特征在于,
对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域。
2.根据权利要求1所述的挠性布线基板,其特征在于,所述图形过渡区域是具有比相邻的所述布线区域的各布线间距的任一个都宽的布线间隔的区域。
3.根据权利要求1所述的挠性布线基板,其特征在于,所述图形过渡区域是至少形成有一个具有相邻的所述布线区域的各布线形式的中间形式的布线的区域。
4.根据权利要求1所述的挠性布线基板,其特征在于,所述图形过渡区域是形成有在信号传输中不使用的虚拟布线的区域。
5.根据权利要求1~4中任意一项所述的挠性布线基板,其特征在于,所述布线形式的差异是基于布线宽度的布线厚度的差异。
6.一种半导体芯片安装用挠性布线基板,其特征在于,该半导体芯片安装用挠性布线基板将权利要求1~5中任意一项所述的挠性布线基板的布线与半导体芯片的输出端子电连接,所述半导体芯片具有大小不同的输出端子,所述布线形式对应所述输出端子的大小,具有不同的布线宽度。
7.一种显示装置,设置有权利要求6所述的半导体芯片安装用挠性布线基板。
8.一种半导体芯片安装方法,通过将半导体芯片的规定图形的输出端子和与挠性布线基板的所述输出端子对应的图形的布线电连接,将所述半导体芯片安装在所述挠性布线基板上,其特征在于,
使用对每种不同布线形式形成多个由相同形式的所述布线形成一个图形的布线区域,在布线形式不同的相邻的所述布线区域之间,形成用于消除因布线形式的差异造成的连接不良的图形过渡区域的挠性布线基板,使所述输出端子的图形与所述布线区域的各布线图形相互对应,进行电连接。
9.根据权利要求8所述的半导体芯片安装方法,其特征在于,在所述布线与所述输出端子之间隔着各向异性导电膜进行所述各布线与所述输出端子的电连接。
10.根据权利要求8或9所述的半导体芯片安装方法,其特征在于,所述图形过渡区域是具有比相邻的所述布线区域的各布线间距宽的布线间隔的区域。
11.根据权利要求8或9所述的半导体芯片安装方法,其特征在于,所述图形过渡区域是至少形成有一个具有相邻的所述布线区域的各布线形式的中间形式的布线的区域。
12.根据权利要求8或9所述的半导体芯片安装方法,其特征在于,所述图形过渡区域是形成有在信号传输中不使用的虚拟布线的区域。
13.根据权利要求8~12中任意一项所述的半导体芯片安装方法,其特征在于,所述布线形式的差异是基于对应所述输出端子的大小而形成的布线宽度的布线厚度的差异。
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JP2003203478A JP4083638B2 (ja) | 2003-07-30 | 2003-07-30 | フレキシブル配線基板、半導体チップ実装フレキシブル配線基板、表示装置、半導体チップ実装方法 |
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US (1) | US7193157B2 (zh) |
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CN105427784A (zh) * | 2014-09-16 | 2016-03-23 | 乐金显示有限公司 | 驱动芯片封装件及包括该驱动芯片封装件的显示装置 |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4485460B2 (ja) * | 2004-12-16 | 2010-06-23 | 三井金属鉱業株式会社 | フレキシブルプリント配線板 |
JP4602150B2 (ja) * | 2005-04-20 | 2010-12-22 | シャープ株式会社 | 駆動回路基板と表示パネルの接続方法 |
US8232655B2 (en) * | 2008-01-03 | 2012-07-31 | International Business Machines Corporation | Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack |
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Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000100851A (ja) * | 1998-09-25 | 2000-04-07 | Sony Corp | 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法 |
JP2000286536A (ja) | 1999-03-30 | 2000-10-13 | Nippon Mektron Ltd | 可撓性回路基板の製造法 |
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US6940178B2 (en) * | 2001-02-27 | 2005-09-06 | Chippac, Inc. | Self-coplanarity bumping shape for flip chip |
US6940176B2 (en) * | 2002-05-21 | 2005-09-06 | United Microelectronics Corp. | Solder pads for improving reliability of a package |
US6750549B1 (en) * | 2002-12-31 | 2004-06-15 | Intel Corporation | Variable pad diameter on the land side for improving the co-planarity of ball grid array packages |
-
2003
- 2003-07-30 JP JP2003203478A patent/JP4083638B2/ja not_active Expired - Lifetime
-
2004
- 2004-07-21 KR KR1020040056782A patent/KR101072336B1/ko active IP Right Grant
- 2004-07-29 CN CNB2004100703107A patent/CN100455160C/zh not_active Expired - Lifetime
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CN106686883B (zh) * | 2017-02-10 | 2019-04-23 | 深圳市华星光电技术有限公司 | 印刷电路板和液晶显示器 |
Also Published As
Publication number | Publication date |
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JP4083638B2 (ja) | 2008-04-30 |
KR20050014673A (ko) | 2005-02-07 |
US7193157B2 (en) | 2007-03-20 |
US20050039945A1 (en) | 2005-02-24 |
JP2005050891A (ja) | 2005-02-24 |
CN100455160C (zh) | 2009-01-21 |
KR101072336B1 (ko) | 2011-10-11 |
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