CN111512417A - 用含金属的顶涂层对材料膜层进行构图以增强极紫外光刻(euv)的感光度 - Google Patents
用含金属的顶涂层对材料膜层进行构图以增强极紫外光刻(euv)的感光度 Download PDFInfo
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Abstract
光刻构图方法包括:在半导体衬底上形成多层构图材料膜叠层,该构图材料膜叠层包括在一个或多个附加层上形成的抗蚀剂层;以及在抗蚀剂层上形成含金属的顶涂层。该方法进一步包括使多层构图材料膜叠层暴露于通过含金属的顶涂层的构图辐射以在抗蚀剂层中形成期望的图案,去除含金属的顶涂层,对在抗蚀剂层中形成的图案显影,根据显影的图案蚀刻至少一层底层,并去除抗蚀剂层的剩余部分。可以例如通过在抗蚀剂层上的原子层沉积或旋涂沉积,或通过从抗蚀剂层的自分离来形成含金属的顶涂层。
Description
背景技术
本发明涉及半导体集成电路的制造,更具体地说,涉及使用光刻工艺的半导体集成电路特征的构图。
作为全球正在进行的努力的一部分以缩小集成电路器件尺寸,已经基于诸如193纳米(193nm)之类的深紫外(DUV)辐射波长进行的多种单图案和多图案光刻工艺,尽管将这样的布置进一步扩展到10nm以下生产节点处的特征构图可能是有问题的,但这种方法仍被广泛使用。期望使用诸如13.5nm的波长的极紫外(EUV)光刻工艺的最新发展有助于在10nm以下的生产节点上对特征进行精确的构图,但是在EUV工艺的实际实施中仍然存在很大的困难。例如,EUV辐射源的输出功率受到限制,因此需要较长的晶圆曝光时间。非常需要提供一种减轻这种缺陷的机制。
发明内容
本发明的实施例提供了在EUV光刻工艺中与构图材料膜叠层一起使用的含金属的顶涂层。这样的布置可以显著增加构图材料膜叠层的EUV灵敏度,从而减少所需的晶片曝光时间和/或EUV辐射源的功率要求。这继而可以导致晶片生产率的显著提高和集成电路制造成本的相应降低。
在本发明的一个实施例中,一种光刻构图方法包括在半导体衬底上形成多层构图材料膜叠层,该膜叠层包括在一个或多个附加层上形成的抗蚀剂层,以及在抗蚀剂层上形成含金属的顶涂层。该方法进一步包括使膜叠层暴露于通过顶涂层的构图辐射以在抗蚀剂层中形成期望的图案,去除顶涂层,对形成在抗蚀剂层中的图案显影,根据显影的图案而蚀刻至少一层底层,并去除抗蚀剂层的剩余部分。可以例如通过在抗蚀剂层上的原子层沉积或旋涂沉积或通过从抗蚀剂层的自分离来形成顶涂层。
在本发明的另一实施例中,一种半导体结构包括:半导体衬底;以及在该衬底上形成的多层构图材料膜叠层,该膜叠层包括在诸如硬掩模层和有机平坦化层的一个或多个附加层上形成的抗蚀剂层。该结构还包括在抗蚀剂层上形成的含金属的顶涂层。顶涂层可以包括可能以一种或多种金属氧化物的形式的过渡金属和后过渡金属中的至少一种。顶涂层还可包含一种或多种准金属。可以配置顶涂层以使其可溶于用于对在抗蚀剂层中形成的图案显影的显影剂溶液或其他流体中。
在本发明的另一实施例中,配置含金属的材料以在形成于半导体基板上的多层构图材料膜叠层的抗蚀剂层上形成含金属的顶涂层。构图材料叠层包括抗蚀剂层和一个或多个在其上形成抗蚀剂层的附加层。含金属的材料被配置为通过在抗蚀剂层上沉积和从抗蚀剂层自分离中的一种来形成顶涂层。含金属的材料可以包括过渡金属和后过渡金属中的至少一种,可能以一种或多种金属氧化物的形式。含金属的材料还可包含一种或多种准金属。含金属的材料包括被构造为包含在用于形成抗蚀剂层的抗蚀剂混合物中的自分离的氟功能化金属添加剂。
附图说明
图1示出了在本发明的实施例中在半导体衬底上形成有机平坦化层之后的半导体结构的截面图;
图2示出了在本发明的实施例中在平坦化层上形成硬掩模层之后的结构的截面图;
图3示出了在本发明的实施例中的在硬掩模层上形成抗蚀剂层之后的结构的截面图;
图4示出了在本发明的实施例中在抗蚀剂层上形成含金属的顶涂层之后的结构的截面图;
图5示出了在本发明的实施例中结合穿过顶涂层的抗蚀剂层的构图的暴露于EUV辐射下的结构的截面图;
图6示出了在本发明的实施例中在抗蚀剂层中的图案显影之后的结构的截面图;
图7示出了在本发明实施例中的根据在抗蚀剂层中形成的图案在蚀刻硬掩模层之后的结构的截面图;
图8示出了在本发明实施例中的在去除抗蚀剂层的剩余部分之后示出蚀刻的硬掩模层的结构的截面图。
具体实施方式
本文在EUV光刻工艺以及相关的构图材料膜叠层和含金属的顶涂层的上下文下描述了本发明的实施方案。然而,应理解,本发明的应用不限于这些布置,并且本发明可广泛地应用于多种不同的光刻工艺、膜叠层、顶涂层以及其他特征和功能。例如,本发明的其他实施例不限于与任何特定的单图案或多图案EUV光刻工艺一起使用,而是可以应用于多种其他类型的光刻工艺,包括单图案和多图案两者的DUV光刻工艺。同样,在本发明的其他实施例中,可以改变在膜叠层内使用的层的特定布置。而且,在本发明的其他实施方案中,顶涂层的特定组分及其形成方式可以改变。对于本领域技术人员而言,所公开的布置中的这些以及许多其他变型将是显而易见的。
本发明的实施方式涉及在多层构图材料叠层的抗蚀剂层上形成含金属的顶涂层,以便在EUV光刻工艺中增加构图材料膜叠层的EUV灵敏度。可以通过在抗蚀剂层上沉积,通过从抗蚀剂层的自分离或使用其他技术(包括沉积和自分离技术的组合)来形成顶涂层。通过在膜叠层中提供增加的EUV灵敏度,本发明的实施例可以减少所需的晶片曝光时间和/或EUV辐射源的功率要求。这继而可以导致晶片生产率的显着提高和集成电路制造成本的相应降低。
图1至图8示出了EUV光刻工艺的一部分,该工艺包括在本发明的实施例中在构图材料膜叠层的抗蚀剂层上形成含金属的顶涂层。EUV光刻工艺与集成电路制造一起应用于半导体晶片。附图示出了晶片的一部分在其作为EUV光刻工艺的一部分而经历顺序的处理操作时的各个截面图。应当理解,这些附图中所示的各种元件和其他特征是为了图示的清楚和简单而简化的,并且不一定按比例绘制。
还应注意,本文中提及在另一层或结构“之上”或“上”的一个层或结构的形成旨在被广义地解释,并且不应被解释为排除一个或多个中间层或结构的存在。
首先参考图1,半导体结构100代表具有半导体衬底102的半导体晶片的一部分。衬底102的至少一部分可以由硅(Si)形成,并且可以具有大约500至1000微米(μm)的厚度。衬底102本身可以包括多个层,尽管在图中它被示为单层,再次声明是为了说明的清晰和简单。半导体结构100还包括有机平坦化层(OPL)104。OPL104可以形成为大约60nm的厚度,尽管在此示出了该尺寸和其他尺寸作为说明性示例,并且不应解释为限制性的。OPL 104可以是本文称为“多层构图材料膜叠层”的最下层,尽管在本发明的其他实施例中这样的叠层不需要包括OPL 104。
如图2所示,在OPL 104上形成硬掩模层106,从而得到结构200。硬掩模层106可以由硅基材料形成,例如氧化硅、氮化硅或氮氧化硅,尽管可以使用多种其他无机或有机材料。可用于形成硬掩模层106的无机材料的其他示例包括含金属的材料,例如氧化钛或氮化钛。可以使用许多其他金属氧化物、金属氮化物和/或金属氧氮化物,以及其他类型的含金属材料。硬掩模层106在此是叠层的第二层,覆盖OPL104。硬掩模层106的厚度可以在大约3nm至15nm的范围内。
现在转到图3,在硬掩模层106上形成抗蚀剂层108,从而得到结构300。该结构300包括多层构图材料膜叠层110,其包括OPL 104、硬掩模层106和抗蚀剂层108。抗蚀剂层包括适于使用EUV辐射源和相应的光掩模进行构图的光敏材料。尽管可以使用其他类型的抗蚀剂材料,但是抗蚀剂层108可以包括有机EUV光刻胶,并且更特别地包括有机化学放大的光刻胶。抗蚀剂层108的厚度可以在约10nm至30nm的范围内。
在本发明的其他实施例中,叠层110可以包括位于抗蚀剂层108下方的附加或替代层。因此,图中所示的特定叠层110仅以说明性示例的方式呈现。给定的这种叠层通常将包括在一个或多个附加层上形成的抗蚀剂层。本示例中的一个或多个附加层包括OPL 104和硬掩模层106。
如图4所示,在叠层110的抗蚀剂层108上形成含金属的顶涂层112,从而得到结构400。可以使用沉积工艺(例如作为原子层沉积(ALD)工艺或旋转沉积工艺)在抗蚀剂层上形成顶涂层。顶涂层112示例性地形成为相对薄的层,以避免由于高的长宽比而导致构图塌陷的任何危险。
例如,可以使用ALD工艺来沉积顶涂层至约2nm至5nm的厚度。这样的ALD工艺可以利用低温沉积条件。这可以涉及利用沉积温度,该沉积温度小于施加到抗蚀剂层108的施加后烘烤(PAB)工艺的温度。例如,用于抗蚀剂层108的PAB工艺的温度可以是150℃,在此,在ALD工艺中用于形成含金属的顶涂层112的沉积温度将基本上低于150℃。例如,可以使用50℃的低温沉积。这些和其他低温沉积工艺允许在在各种不同的抗蚀剂材料上进行涂覆,并有助于在抗蚀剂层108的表面上形成可定制的涂层厚度。
如本文所用,术语“含金属的顶涂层”旨在被广义地解释为涵盖各种涂层或其他类型的层或多层的布置,其可以作为光刻构图工艺的一部分形成在抗蚀剂层上。
如上所述,还可以使用旋涂沉积工艺来形成顶涂层112。例如,可以在将PAB工艺施加到抗蚀剂层108之后使用旋涂沉积工艺来形成顶涂层112,作为金属氧化物纳米颗粒的旋涂层。
可以使用与在EUV光刻中形成底部抗反射涂层(BARC)所使用的那些工艺相似的工艺来形成顶涂层112。这种BARC工艺通常用于形成具有高均匀性的薄膜涂层。可用于形成顶涂层112的沉积工艺的其他示例包括化学气相沉积(CVD)和物理气相沉积(PVD)。
可以使用沉积以外的技术来形成顶涂层112。例如,可以利用自抗蚀剂层108的自分离工艺,在抗蚀剂层108上形成图4的结构400中的顶涂层112。在这种类型的布置中,在用于形成抗蚀剂层108的抗蚀剂混合物中提供自离材料,该抗蚀剂混合物用于形成抗蚀剂层108,然后对抗蚀剂层108进行指定的工艺以使自分离材料从抗蚀剂层自分离以形成顶涂层112。例如,自分离材料可以包括氟功能化金属添加剂。使自分离材料从抗蚀剂层108自分离以形成顶涂层112的指定工艺示例性地包括PAB工艺。
结合到抗蚀剂混合物中以通过自分离形成顶涂层112的自分离材料被认为是本发明的示例实施例,包含这种自分离材料的抗蚀剂混合物也被认为是本发明的示例实施方式。
可用于通过自分离形成顶涂层的自分离材料的实例包括可掺入抗蚀剂混合物中的具有氟代醇功能化的添加剂材料,以及基于金属侧基或金属骨架的聚合物。
顶涂层112可以包括含有过渡金属和过渡后金属中的至少一种的金属组合物。例如,顶涂层可以包含至少一种过渡金属,例如(Hf)、锆(Zr)、钽(Ta)、钨(W)、铬(Cr)、钴(Co)、铁(Fe)和铂(Pt)中的至少一种。另外地或可替代地,顶涂层112可以包括至少一种过渡后金属,例如锡(Sn)。顶涂层112还可掺入至少一种准金属,例如锑(Sb)。
上面提到的金属和准金属是在本文中通常被称为“高Z”原子的例子,其中Z表示原子的原子序数,并且可替代地,在其他实施例中,高Z原子可用于含金属的顶涂层112。
用于顶涂层的金属组合物可以是金属氧化物的形式,其浓度小于顶涂层112的约30%。例如,顶涂层112可以通过氧化锡(SnOx)在50℃下低温沉积形成。在本文的上下文和其他类似的上下文中,浓度百分比量是指摩尔百分比(mol%)。
可用于通过从抗蚀剂层108的自分离而形成顶涂层112的组合物的实例包括具有六氟丙酮(HFA)的共聚物,以及含锡(Sn)的单体单元的或其他类型的含金属单体单元。
作为更具体的例子,适用于形成含金属的顶涂层112的具有HFA的共聚物具有以下化学式,其中R表示氢(H)或甲基或烷基:
在以上示例中,X表示单位数。对于典型的聚合物与金属单元的结合,HFA以及可能的一种或多种其他单元,HFA的百分比将为约5%至15%,以支持顶涂层112与抗蚀剂层108的自分离,百分比亮再次指摩尔百分比(mol%)。
作为另一个例子,适用于形成顶涂层112的含锡(Sn)的单体单元具有以下化学式:
在该实例中,n表示存在的单元数,并且R表示烷基。
同样,上述材料配方仅是示例,并且在形成顶涂层112中,可以使用具有不同化学组成的多种其他材料,包括与HFA的其他共聚物,其他含金属的单体单元和其他类型的组合物。
顶涂层112可以被配置为通过增加抗蚀剂层108中二次电子的产生来增加叠层110的EUV灵敏度。在这样的示例中,通过允许其在曝光期间捕获更多的EUV光子,顶涂层112增强了抗蚀剂层108吸收EUV辐射的能力。
例如,抗蚀剂层108的抗蚀剂材料可以通过对顶涂层112的组分的选择性渗透和随后的反应而经历增强的灵敏度。作为更具体的示例,在上述沉积SnOx顶涂层的情况下,SnOx颗粒可能渗入抗蚀剂层108或成为抗蚀剂层108的一部分。
包括含金属的顶涂层的本发明的这些和其他实施例可以显著提高EUV灵敏度,而不会牺牲构图的特征分辨率或不利地影响例如线边缘粗糙度(LER)和线宽粗糙度(LWR)的构图质量指标。
现在参考图5,将叠层110暴露于通过顶涂层112的EUV构图辐射下,以在抗蚀剂层108中形成所需的图案。所得结构500包括构图的抗蚀剂层,在图中用参考数字108'表示。
然后,去除顶涂层112,并对构图的抗蚀剂层108'进行显影,得到如图6所示的结构600。例如,可以通过剥离去除顶涂层112,之后,构图的抗蚀剂层使用显影剂溶液显影108'。构图的抗蚀剂层108'的显影导致显影的抗蚀剂层108',其中根据图案去除抗蚀剂层的一部分。
替代地,顶涂层112可以由可溶于显影剂溶液中的材料制成,该显影剂溶液用于对在抗蚀剂层108'中形成的图案显影。例如,顶涂层112可以被配置为在抗蚀剂显影期间可溶于基础和/或水中。在这种类型的布置中,作为对在抗蚀剂层108'中形成的图案显影的工艺的一部分,去除顶涂层112。再次,构图的抗蚀剂层108'的显影导致显影的抗蚀剂层108″,其中根据图案去除抗蚀剂层的一部分。
因此,曝光后的顶涂层112可以在单独的步骤中被剥离,或者如果被配置为具有固有的可溶性功能,则可以作为抗蚀剂显影工艺的一部分被去除。
如图7所示,根据显影后的图案蚀刻位于显影后的抗蚀剂层108″下方的硬掩模层106,以产生结构700。这部分工艺导致如图所示的图案从显影后的抗蚀剂层108″转移到构图的硬掩模层106′。可以使用诸如反应离子蚀刻(RIE)或湿蚀刻的工艺来执行蚀刻。
然后,如图8所示,除去显影后的抗蚀剂层108″的其余部分,得到结构800。然后为了在半导体晶片上形成期望的集成电路结构,对结构800进行本领域技术人员公知的附加工艺操作。例如,如先前结合图1至图8所描述的工艺的一部分可以使用不同的图案掩模重复,以便根据附加的图案特征进一步配置硬掩模层。
在本发明的其他实施例中,可以使用其他类型的多层构图材料膜叠层。例如,在本发明的一些实施例中,省略了硬掩模层,并且根据显影的抗蚀剂层108″的图案蚀刻衬底102的一层或多层。如本领域技术人员将理解的,可以使用本文公开的技术来实现使用在抗蚀剂层上形成的含金属的顶涂层的这些和许多其他光刻构图布置。
本发明的实施例可以包括半导体结构,该半导体结构包括半导体衬底和在衬底上形成的多层构图材料膜叠层,其中该叠层包括在一个或多个附加层(例如硬掩模层和有机平坦化层)上形成的抗蚀剂层。该结构还包括在抗蚀剂层上形成的含金属的顶涂层。顶涂层可以包括过渡金属和后过渡金属中的至少一种,可能以一种或多种金属氧化物的形式。顶涂层还可包含一种或多种准金属。可以配置顶涂层以使其可溶于用于对在抗蚀剂层中形成的图案显影的显影剂溶液中。
本发明的其他实施例可以包括含金属的材料,该含金属的材料被配置为在形成在半导体衬底上的多层构图材料膜叠层的抗蚀剂层上形成含金属的顶涂层。该叠层包括抗蚀剂层和在其上形成抗蚀剂层的一个或多个附加层。含金属的材料被配置为通过在抗蚀剂层上沉积以及从抗蚀剂层自分离中的一种来形成顶涂层。含金属的材料可以包括过渡金属和后过渡金属中的至少一种,可能以一种或多种金属氧化物的形式。含金属的材料还可包含一种或多种准金属。含金属的材料可包含被配置为包含在用于形成抗蚀剂层的抗蚀剂混合物中的自分离的氟功能化的金属添加剂。
本发明的进一步的实施例可以包括多层构图材料膜叠层,其包括形成在一个或多个附加层(例如,硬掩模层和有机平坦化层)上的抗蚀剂层。在抗蚀剂层上形成含金属的顶涂层,并且顶涂层可以被认为是叠层的一部分。该叠层可以在半导体衬底上或其他类型的衬底、层或材料上形成。
本发明的另外的实施例包括光刻工具和其他类型的光刻图案形成设备,其被配置为执行诸如上面结合半导体集成电路的制造所描述的光刻工艺。例如,在13.5nm波长下工作的EUV光刻工具(例如ASML NXE:3300B或NXE:3350B)可以被修改以执行上述类型的EUV光刻工艺,包括使用本文公开的技术形成含金属的顶涂层。同样,基于在DUV波长或其他波长处的构图辐射,可以使用其他类型的光刻工艺和相关的光刻工具,因此本文公开的技术不限于与EUV光刻工艺或EUV光刻工具一起使用。
可以使用本文公开的EUV光刻工艺形成的集成电路结构的示例包括纳米片金属氧化物半导体场效应晶体管(MOSFET)器件。本文所公开的含金属的顶涂层的使用可以通过增加叠层的EUV灵敏度来促进这种器件的制造,从而促进形成低于10nm的特征。对于特征尺寸的替代范围(例如低于50nm的特征)也提供了类似的改进。可以使用EUV光刻工艺来制造各种各样的其他类型的集成电路器件,该工艺包括图1至8所示步骤的至少一部分的一次或多次迭代。
在以上描述中,提供了用于不同元件的各种材料和尺寸。除非另有说明,否则这些材料仅以举例的方式给出,并且实施例不仅仅限于所给出的具体示例。类似地,除非另有说明,否则所有尺寸均以示例的方式给出,并且本发明的实施例不仅仅限于所给出的特定尺寸或范围。
应当理解,上述各种层、结构和/或区域不一定按比例绘制。另外,为了便于说明,在给定附图中可能未明确示出通常用于形成半导体器件或结构的一种或多种层、结构和区域。这并不意味着从实际的半导体结构中省略未明确示出的任何层、结构和区域。
此外,应理解,本文讨论的本发明的实施方案不限于本文所示和描述的特定工艺步骤。特别地,关于半导体工艺步骤,要强调的是,本文提供的描述并不旨在涵盖可用于形成功能性半导体集成电路器件的所有工艺步骤。而是,出于描述的经济目的,本文没有故意地描述通常在形成半导体器件中使用的某些处理步骤,例如湿法清洁和退火步骤。
如本文中所使用的关于厚度、宽度、百分比、范围等的术语“大约”或“基本上”旨在表示接近或近似但并非精确。例如,本文所用的术语“大约”或“基本上”表示可能存在小的误差范围,例如仅作为示例,1%或小于所述量。而且,在附图中,一个层、结构和/或区域相对于另一层、结构和/或区域的所示比例不一定旨在表示实际比例。
根据上述技术的半导体器件及其形成方法可用于各种应用、硬件和/或电子系统中,包括但不限于个人计算机、通信网络、电子商务系统、便携式通信设备(例如蜂窝电话和智能电话)、固态媒体存储设备,功能电路等。鉴于本文提供的教导,本领域的普通技术人员将能够考虑本发明的实施例的其他实现和应用。
在本发明的一些实施例中,上述技术与半导体集成电路器件的制造结合使用,该半导体集成电路器件示例性地包括(作为非限制性示例)CMOS器件、MOSFET器件和/或FinFET器件、和/或结合或利用CMOS,MOSFET和/或FinFET技术的其他类型的半导体集成电路器件。
因此,本文所述的一个或多个半导体结构的至少一部分可以在集成电路中实现。制造商可以以原始晶片形式(即,具有多个未封装芯片的单个晶片)、裸露裸片或封装形式来分布所得的集成电路芯片。在后一种情况下,芯片安装在单芯片封装中(例如塑料载体、引线固定在母板或其他更高级别的载体上),或者安装在多芯片封装中(例如具有表面互连或掩埋互连其中一个或两者兼有的陶瓷载体)。在任何情况下,该芯片然后都与其他芯片、分立电路元件和/或其他信号处理设备集成在一起,作为(a)中间产品(例如母板)或(b)最终产品的一部分。最终产品可以是任何包含集成电路芯片的产品,范围从玩具和其他低端应用到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
已经出于说明的目的给出了对本发明的各种实施例的描述,但是这些描述并非意图是穷举性的或限于所公开的本发明的实施例。在不脱离本发明范围的情况下,许多修改和变化对本领域普通技术人员将是显而易见的。选择这里使用的术语是为了最好地解释本发明的原理,对市场上发现的技术的实际应用或技术上的改进,或者使本领域的其他普通技术人员能够理解这里公开的本发明的实施例。
Claims (19)
1.一种光刻构图方法,包括:
在半导体衬底上形成多层构图材料膜叠层,所述构图材料膜叠层包括在一个或多个附加层上形成的抗蚀剂层;
在所述抗蚀剂层上形成含金属的顶涂层;
使所述多层构图材料膜叠层暴露于通过所述含金属的顶涂层的构图辐射,以
在所述抗蚀剂层中形成期望的图案;
去除所述含金属的顶涂层;
对形成在所述抗蚀剂层中的所述图案显影;
根据所述显影的图案蚀刻至少一层底层;以及
去除所述抗蚀剂层的剩余部分;
其中在所述抗蚀剂层上形成所述含金属的顶涂层包括利用从所述抗蚀剂层的自分离工艺形成所述含金属的顶涂层。
2.如权利要求1所述的方法,其中,所述构图材料膜叠层的所述一个或多个附加层包括以下至少之一:
硬掩模层;以及
有机平坦化层。
3.如权利要求2所述的方法,其中根据所述显影的图案蚀刻至少一层底层包括蚀刻所述硬掩模层。
4.如权利要求1所述的方法,其中在所述抗蚀剂层上形成所述含金属的顶涂层包括利用沉积工艺在所述抗蚀剂层上形成所述含金属的顶涂层。
5.如权利要求4所述的方法,其中,用于形成所述含金属的顶涂层的所述沉积工艺包括原子层沉积工艺。
6.如权利要求4所述的方法,其中,用于形成所述含金属的顶涂层的所述沉积工艺包括旋涂工艺。
7.如权利要求1所述的方法,其中利用从所述抗蚀剂层的自分离工艺形成所述含金属的顶涂层包括:
在用于形成所述抗蚀剂层的抗蚀剂混合物中提供自分离材料;
利用所述抗蚀剂混合物以形成所述抗蚀剂层;以及
对所述抗蚀剂层进行指定的工艺,以使所述自分离材料从所述抗蚀剂层自分离,从而形成所述含金属的顶涂层。
8.如权利要求7所述的方法,其中使所述自所述分离材料从所述抗蚀剂层自分离以形成所述含金属的顶涂层的指定工艺包括施加后烘烤工艺。
9.如权利要求1所述的方法,其中所述含金属的顶涂层包括至少一种过渡金属,并且所述至少一种过渡金属包括铪(Hf)、锆(Zr)、钽(Ta)、钨(W)、铬(Cr)、钴(Co)、铁(Fe)和铂(Pt)中的至少一种。
10.如权利要求1的方法,其中所述含金属的顶涂层包含至少一种后过渡金属,并且所述至少一种后过渡金属包含锡(Sn)。
11.如权利要求1的方法,其中所述含金属的顶涂层还包含至少一种准金属,并且所述至少一种准金属包含锑(Sb)。
12.如权利要求1所述的方法,其中所述含金属的顶涂层可溶于用于对在所述抗蚀剂层中形成的图案显影的显影剂溶液中。
13.如权利要求1所述的方法,其中去除所述含金属的顶涂层包括作为对在所述抗蚀剂层中显影所述图案的一部分,去除所述含金属的顶涂层。
14.一种半导体结构,包括:
半导体衬底;
在所述半导体衬底上形成的多层构图材料膜叠层,所述构图材料膜叠层包括在一个或多个附加层上形成的抗蚀剂层;以及
在所述抗蚀剂层上形成的含金属的顶涂层。
15.如权利要求14所述的半导体结构,其中所述含金属的顶涂层可溶于用于对在所述抗蚀剂层中形成的图案显影的显影剂溶液中。
16.一种含金属的材料,其被配置为形成如权利要求14所述的半导体结构的含金属的顶涂层,所述含金属的材料被配置为通过在所述抗蚀剂层上沉积以及从所述抗蚀剂层自分离两者之一形成所述含金属的顶涂层。
17.如权利要求16所述的含金属的材料,其中,所述含金属的材料包括过渡金属和后过渡金属中的至少一种。
18.如权利要求16所述的含金属的材料,其中所述含金属的材料包括金属氧化物。
19.如权利要求16所述的含金属的材料,其中,所述含金属的材料包括自分离的氟功能化的金属添加剂,其被配置为包含在用于形成所述抗蚀剂层的抗蚀剂混合物中。
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DE112018005569B4 (de) | 2021-06-10 |
US20190259601A1 (en) | 2019-08-22 |
JP2021508071A (ja) | 2021-02-25 |
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WO2019123067A1 (en) | 2019-06-27 |
GB2583206B (en) | 2022-09-07 |
US20190189428A1 (en) | 2019-06-20 |
CN111512417B (zh) | 2024-03-12 |
US11177130B2 (en) | 2021-11-16 |
GB202007913D0 (en) | 2020-07-08 |
US10347486B1 (en) | 2019-07-09 |
GB2583206A (en) | 2020-10-21 |
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