CN111244067B - 半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法 - Google Patents

半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法 Download PDF

Info

Publication number
CN111244067B
CN111244067B CN201811559391.5A CN201811559391A CN111244067B CN 111244067 B CN111244067 B CN 111244067B CN 201811559391 A CN201811559391 A CN 201811559391A CN 111244067 B CN111244067 B CN 111244067B
Authority
CN
China
Prior art keywords
metal
package
metal column
substrate
frequency chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811559391.5A
Other languages
English (en)
Other versions
CN111244067A (zh
Inventor
蔡宗哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CN111244067A publication Critical patent/CN111244067A/zh
Application granted granted Critical
Publication of CN111244067B publication Critical patent/CN111244067B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6666—High-frequency adaptations for passive devices for decoupling, e.g. bypass capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明公开一种半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法，其中，具有封装内隔室屏蔽的半导体封装包含一基板，在该基板的一顶表面上至少设置有一高频芯片以及易受高频讯号干扰的一电路组件；一第一接地环，在该基板的该顶表面上，环绕着该高频芯片；一第一金属柱强化胶体墙，设在该第一接地环上，环绕着该高频芯片；一第二接地环，在该基板的该顶表面上，环绕着该电路组件；一第二金属柱强化胶体墙，设在该第二接地环上，环绕着该电路组件；一成型模料，至少覆盖该高频芯片及该电路组件；以及一导电层，设于该成型模料上，并且与该第一金属柱强化胶体墙及/或该第二金属柱强化胶体墙接触。

Description

半导体封装、具有封装内隔室屏蔽的半导体封装及其制作 方法
技术领域
本发明涉及半导体技术领域，特别涉及一种半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法。
背景技术
可携式电子设备，例如移动电话，通常利用多组件半导体模块在单个模制封装中提供高度的电路整合。多组件半导体模块可包括例如半导体晶粒和安装在电路板上的多个电子组件。安装有半导体晶粒和电子组件的电路板系在模封制程中完成封装，形成包覆成型的半导体封装结构。
为了确保手机等设备在不同环境中正确操作能达到所需的性能水平，通常还要对包覆成型的半导体封装进行屏蔽，使其免受电磁干扰(EMI)的影响。上述电磁干扰是由于电磁(例如射频(RF))辐射和电磁传导而在电气系统中产生的不利于组件效能的影响。
随着芯片模块，例如，系统级封装(SiP)的体积越来越小，组件之间的距离也跟着缩小，也使得模块内的电路对EMI更敏感，因此有必要在模块内组件之间设置电磁干扰屏蔽。然而，现有技术要在模块内形成屏蔽，制程上十分复杂且成本高昂。因此，目前该技术领域面临的挑战是在不增加封装尺寸及制程复杂度的情况下为包覆成型的半导体封装提供有效的EMI屏蔽，并且不会显著增加封装成本。
发明内容
本发明的主要目的在提供一种具有封装内隔室屏蔽的半导体封装及其制作方法，以解决上述先前技艺的不足与缺点。
本发明实施例一方面披露一种具有封装内隔室屏蔽的半导体封装，包含：一基板，在该基板的一顶表面上至少设置有一高频芯片，以及易受高频讯号干扰的一电路组件；一第一接地环，在该基板的该顶表面上，环绕着该高频芯片；一第一金属柱强化胶体墙，设在该第一接地环上，环绕着该高频芯片；一第二接地环，在该基板的该顶表面上，环绕着该电路组件；一第二金属柱强化胶体墙，设在该第二接地环上，环绕着该电路组件；一成型模料，至少覆盖该高频芯片及该电路组件；以及一导电层，设于该成型模料上，并且与该第一金属柱强化胶体墙及/或该第二金属柱强化胶体墙接触。
根据本发明一实施例，该第一金属柱强化胶体墙包含复数个第一金属柱，其中各该复数个第一金属柱的一端固定在该第一接地环上，另一端则悬空，该复数个第一金属柱围绕着该高频芯片。
根据本发明一实施例，该第二金属柱强化胶体墙包含复数个第二金属柱，其中各该复数个第二金属柱的一端固定在该第二接地环上，另一端则悬空，该复数个第二金属柱围绕着该电路组件。
根据本发明一实施例，该第一金属柱强化胶体墙或该第二金属柱强化胶体墙另包含一胶体，附着在该第一或该第二金属柱的表面上。根据本发明一实施例，该成型模料的组成与该胶体的组成不同。
另一方面，本发明实施例披露一种具有封装内隔室屏蔽的半导体封装的制作方法。首先提供一基板，在该基板的一顶表面上至少设置有一高频芯片，以及易受高频讯号干扰的一电路组件，其中该基板的该顶表面上另设有一第一接地环，环绕着该高频芯片，以及一第二接地环，环绕着该电路组件。在该第一接地环上形成一第一金属柱强化胶体墙，环绕着该高频芯片。在该第二接地环上形成一第二金属柱强化胶体墙，环绕着该电路组件。形成一成型模料，至少覆盖该高频芯片及该电路组件。于该成型模料上形成一导电层，使该导电层与该第一金属柱强化胶体墙及/或该第二金属柱强化胶体墙接触。
根据本发明一实施例，另包含：形成复数个第一金属柱，其中各该复数个第一金属柱的一端固定在该第一接地环上，另一端则悬空，该复数个第一金属柱围绕着该高频芯片。
根据本发明一实施例，另包含：形成复数个第二金属柱，其中各该复数个第二金属柱的一端固定在该第二接地环上，另一端则悬空，该复数个第二金属柱围绕着该电路组件。
根据本发明一实施例，另包含：形成一胶体，附着在该第一或该第二金属柱的表面上。
本发明另一方面提供一半导体封装，包含一基板，在该基板的一顶表面上至少设置有一半导体芯片；一接地环，在该基板的该顶表面上，环绕着该半导体芯片；一金属柱强化胶体墙，设在该接地环上，环绕着该半导体芯片；以及一成型模料，紧紧设置在该金属柱强化胶体墙围绕的范围内，并覆盖该半导体芯片。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1至图5为依据本发明一实施例所绘示的一种具有封装内隔室屏蔽的半导体封装的制作方法示意图；
图6及图7例示设置在半导体芯片之间的重迭处的金属柱的部份上视示意图；
图8及图9为依据本发明另一实施例所绘示的一种具有封装内隔室屏蔽的半导体封装的制作方法示意图；
图10及图11为依据本发明其它实施例所绘示的单芯片封装侧视示意图。
附图标号说明：
Figure BDA0001911982240000031
Figure BDA0001911982240000041
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明，若本发明实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本发明实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为，包括三个并列的方案，以“A和/或B”为例，包括A方案、或B方案，或A和B同时满足的方案。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本发明要求的保护范围之内。
本公开披露一种具有封装内隔室屏蔽(In-Package Shielding)的半导体封装，例如，系统级封装(Systemin a Package，SiP)，及其制作方法。SiP系指将多个功能芯片，包括处理器、内存等功能芯片及其他组件，例如被动组件，整合在单一封装内，而能实现一完整的功能。如前所述，随着电子系统变得越来越小以及SiP封装内电子组件的密度越来越高，因此容易产生系统内的电磁干扰(EMI)，尤其一些高频芯片封装结构，例如，射频芯片、GPS芯片、蓝芽芯片等高频芯片透过SiP封装为一体式结构，容易产生封装内电子组件之间的电磁干扰。本发明于是提出一种制程简化、低成本且有效的半导体封装的制作方法，能够具体解决现有技术面临的问题。
图1至图5为依据本发明一实施例所绘示的一种具有封装内隔室屏蔽的半导体封装1的制作方法示意图。如图1所示，首先提供一基板100，例如，一电路板或一封装基板。根据本发明一实施例，例如，基板100可以是双层基板(例如，具有核心层和两个金属层的基板)，但不限于此。基板100可包括陶瓷材料、层压绝缘材料或其他合适类型的材料。尽管未在图1中示出，基板100还可以包括在其顶表面100a和底表面100b和通孔上的图案化金属层或迹线(trace)。此外，在基板100顶表面100a和底表面100b上可以另设有一防焊层120(又称为绿漆)。
根据本发明一实施例，在基板100的顶表面100a上可以设置有多个彼此靠近的半导体芯片10～12。例如，半导体芯片10可以是电源管理芯片(power management IC，PMIC)，半导体芯片11可以是射频芯片(RFIC)，半导体芯片12可以是功率放大器芯片(poweramplifier IC，PAIC)，但不限于此。
熟习该项技艺者应理解以上半导体芯片10～12的种类仅为例示说明。为达到不同的电路功能，基板100上还可以设置其他不同的半导体芯片或组件，例如，处理器、闪存(flash memory)或动态随机存取内存(dynamic random access memory，DRAM)、控制芯片等。根据本发明一实施例，在基板100的顶表面100a上至少设置有一高频芯片，例如，半导体芯片11，以及易受高频讯号干扰的电路组件或芯片，例如，半导体芯片12。
根据本发明一实施例，例如，半导体芯片10及12可以是以打线接合(wirebonding)方式设置在基板100的顶表面100a上，半导体芯片11可以是以覆晶接合(flipchip bonding)方式设置在基板100的顶表面100a上，但不限于此。根据本发明一实施例，半导体芯片10～12可以是裸晶(bare die)形式或者芯片封装(chip package)形式。
例如，半导体芯片10的主动面上可以设置有多个输出/输入垫(input/outputpad，I/O pad)101，经由打线102电连接至基板100的顶表面100a上的相应接合垫202(通常又称金手指)。根据本发明一实施例，打线102可以是金线或铜线等，而接合垫202的表面通常设置有可焊接镀层(solderable coating)，例如，镍金层或铜金层等。例如，半导体芯片12可以透过打线122电连接至基板100的顶表面100a。
根据本发明一实施例，在基板100的顶表面100a上可以另设置有多个被动组件13。例如，被动组件13可以是电容组件、电感组件、电阻组件等，但不限于此。根据本发明一实施例，被动组件13可以是利用表面黏着技术(surface-mount technology，SMT)设置在基板100的顶表面100a上，但不限于此。根据本发明一实施例，被动组件13可以设置在半导体芯片10～12之间的基板100的顶表面100a上。
根据本发明一实施例，例如，在半导体芯片11及12的周围的基板100的顶表面100a上，分别设置有接地环211及212，其中，接地环211环绕着半导体芯片11，而接地环212环绕着半导体芯片12。根据本发明一实施例，接地环211及212可以是连续的环状图案，但不限于此。在其他实施例中，接地环211及212可以是连续的环状图案或者是排列成环状的接垫图案。
例如，接地环211及212可以是由基板100内的图案化金属层所构成，其表面具有可焊接镀层，例如，镍金层或铜金层等。接地环211及212可以进一步透过通孔与一接地层(图未示)电连接。根据本发明一实施例，接地环211及212可以有部分重迭或共享部分，例如，在半导体芯片11及12的之间的重迭处213，但不限于此。在其他实例中，接地环211及212可以是彼此独立的环状图案。
根据本发明一实施例，在接地环211上设置有多个金属柱311，而在接地环212上设置有多个金属柱312。根据本发明一实施例，金属柱311、312可以是包含铜、银、金、铝、镍、钯、其任何组合或合金，或任何合适的导电材料。例如，金属柱311、312可以是铜柱或铜镍合金柱，但不限于此。根据本发明一实施例，金属柱311至少排列成一列，且金属柱312至少排列成一列，但不限于此。根据本发明一实施例，在前述的半导体芯片11及12的之间的重迭处213，金属柱311与金属柱312之间是彼此交错的排列，如图1中右侧放大侧视图所示，如此以达到较佳的电磁干扰屏蔽效果。
根据本发明一实施例，金属柱311、312可以是利用打线方式形成的，其中各金属柱311、312一端固定在接地环211、212上，另一端则是悬空的，如图1所示，各金属柱311、312笔直的朝向上，如同围篱般分别围绕着半导体芯片11及12。根据本发明一实施例，金属柱311、312具有一约略相同的高度h，其中高度h高于后续预定形成的成型模料的目标厚度(研磨后)。图1虽绘示金属柱311、312分别围绕着半导体芯片11及12，然而，熟习该项技艺者应理解，金属柱311、312可以分别围绕着半导体芯片11及12的部分周边，例如，半导体芯片11及12的单边或双边等，而不是完全围绕，例如，在另一实施例中，金属柱311、312仅设置在半导体芯片11及12的之间的重迭处213。
请参阅图6及图7，其例示设置在半导体芯片11及12之间的重迭处213的金属柱311、312的部份上视示意图。如图6所示，金属柱311的线径d1与金属柱312的线径d2可以彼此相等或不相等。金属柱311之间的间距P1、金属柱312之间的间距P2及金属柱311、312之间的间距P3，彼此可以相等或不相等。金属柱311、312之间的横向距离S可以是大于或等于0。根据本发明一实施例，例如，金属柱311、312之间的横向距离S可以是介于欲屏蔽电磁波的波长的约十分之一约到百分之一的范围内，但不限于此。可以选择金属柱311、312的横向距离S的值以为特定频率或频率范围提供EMI屏蔽。
举例来说，如图7所示，金属柱311的线径d1与金属柱312的线径d2可以彼此相等，例如，大于或等于15微米，而金属柱311之间的间距P1与金属柱311、312之间的间距P3彼此相等，例如，约等于30微米。需理解的是，上述参数，包括金属柱311的线径d1、金属柱312的线径d2、金属柱311之间的间距P1、金属柱312之间的间距P2及金属柱311、312之间的间距P3，均可以视实际设计需求而调整。
根据本发明一实施例，金属柱311、312可以是与半导体芯片10及12的打线接合步骤同时进行并且可以在同一打线机台中完成。此外，根据本发明一实施例，金属柱311、312的线径可以与半导体芯片10及12上的打线102及打线122的线径相同，也可以不相同。例如，金属柱311、312的线径可以大于半导体芯片10及12上的打线102及打线122的线径。此外，金属柱311、312的材料可以与半导体芯片10及12上的打线102及打线122的材料相同，也可以不相同。
如图2所示，在完成金属柱311、312的设置后，接着进行一喷胶制程，利用一喷头40将一胶体401沿着接地环211及212喷洒在金属柱311、312上，其中使胶体401附着在金属柱311、312的表面上并填入金属柱311、312之间的空隙。根据本发明一实施例，胶体401可以是热固性树脂、热塑性树脂、UV固化树脂等，但不限于此。根据本发明一实施例，胶体401可以是导电胶，例如，银胶或铝胶。根据本发明一实施例，胶体401可以包含有导电颗粒，例如，铜、银、金、铝、镍、钯、其任何组合或合金、石墨烯，或任何合适的导电材料。根据本发明一实施例，胶体401还可以包含有填充物(filler)，例如，石英颗粒、钻石颗粒等。根据本发明一实施例，胶体401还可以包含有溶剂或添加剂(例如，交联剂、催化剂或改质剂)等。
后续，可以进行一固化制程，例如，加热或UV照射，使得黏附在金属柱311、312表面上的胶体401达到固化或者半固化的程度。胶体401可以强化金属柱311、312，使其在制程中不会倒塌，此外，也可以提升电磁干扰的屏蔽效果及散热效能。在完成固化制程之后，即在基板100的顶表面100a上形成金属柱强化胶体墙(metal-pillar reinforced glue walls)411及412，其中金属柱强化胶体墙411包含环绕着半导体芯片11的金属柱311及经过固化或半固化的胶体401，金属柱强化胶体墙412包含环绕着半导体芯片12的金属柱312及经过固化或半固化的胶体401。
根据本发明其它实施例，若金属柱311的线径d1与金属柱312的线径d2较粗，例如，大于或等于25微米，或者，大于或等于35微米，此时，也可以省略喷胶制程。此外，在其他实施例中，也可以选择在图2中所示的在接地环上设置金属柱之后，才进行图1中所示在基板的顶表面上设置半导体芯片(包括芯片接合、打线或覆晶接合等)步骤。
如图3所示，接着进行一模封制程，在基板100的顶表面100a上形成一成型模料500。根据本发明一实施例，成型模料500可以包含树脂材料，例如，热固性树脂、热塑性树脂、UV固化树脂等，但不限于此。根据本发明一实施例，成型模料500的组成与胶体401的组成不同，例如，胶体401的组成中可以包含有导电颗粒，而成型模料500的组成中则通常不含有导电颗粒。然而，本发明并不限于此，在其它实施例中，成型模料500的组成与胶体401的组成可以相同，或者使成型模料500与胶体401的热膨胀系数、应力或弹性系数等物性能够互相匹配。
根据本发明一实施例，成型模料500溢出金属柱强化胶体墙411及412而覆盖在金属柱强化胶体墙411及412以外的区域，包括半导体芯片10、打线102、122及被动组件13均被成型模料500包封住。根据本发明一实施例，成型模料500可以利用各种合适的方法形成，例如，压缩模制(compression molding)，但不限于此。根据本发明一实施例，上述模封制程可以进一步包含一固化制程，例如，热固化制程。此时，如图3所示，成型模料500在经过热固化后，可以具有一第一厚度t1，其中第一厚度t1大于金属柱311、312的高度h及金属柱强化胶体墙411及412的高度。
如图4所示，在完成模封制程之后，接着可以进行一研磨制程，将成型模料500的厚度从第一厚度t1缩减至一第二厚度t2，使得金属柱强化胶体墙411及412的顶面被显露出来，而且金属柱311、312的上端面也被显露出来。此时，成型模料500的上表面与金属柱强化胶体墙411及412的顶面是约略齐平的。
最后，如图5所示，在成型模料500上的预定区域，形成一导电层520。根据本发明一实施例，导电层520可以位于半导体芯片11及12和金属柱强化胶体墙411及412的正上方。导电层520可包括导电涂层，例如，导电墨水，其可包括铜、银或其他导电金属。在另一实施例中，导电层520可包括铜、铝或其他合适金属的层。导电层520直接接触到金属柱311、312的显露出的上端面，并透过金属柱311、312构成接地组态。
需理解的是，图5中的导电层520的覆盖范围及图案仅为例示说明，本发明不应以此为限。在其它实施例中，成型模料500上的全部表面包括上表面及侧表面)可以被导电层520覆盖。在一些实施例中，导电层520可以仅覆盖半导体芯片11或12。此时，导电层520会与第一金属柱强化胶体墙411或412及部分的成型模料500的上表面接触。
结构上，如图4及图5所示，本发明实施例披露一种具有封装内隔室屏蔽的半导体封装1，包含：一基板100，在基板100的一顶表面100a上至少设置有一高频芯片，例如半导体芯片11，以及易受高频讯号干扰的一电路组件12，例如半导体芯片11。一接地环211，在基板100的顶表面100a上，环绕着高频芯片，例如半导体芯片11。一金属柱强化胶体墙411，设在接地环211上，环绕着高频芯片。一接地环212，在基板100的顶表面100a上，环绕着电路组件。一金属柱强化胶体墙412，设在接地环212上，环绕着电路组件。一成型模料500，至少覆盖高频芯片及电路组件；以及一导电层520，设于成型模料500上，并且与金属柱强化胶体墙411及/或该金属柱强化胶体墙412接触。
根据本发明一实施例，金属柱强化胶体墙411包含复数个金属柱311，其中各金属柱311的一端固定在接地环211上，另一端则悬空，复数个金属柱311围绕着高频芯片。
根据本发明一实施例，金属柱强化胶体墙412包含复数个金属柱312，其中各金属柱312的一端固定在接地环212上，另一端则悬空，复数个金属柱312围绕着电路组件。
根据本发明一实施例，金属柱强化胶体墙411或金属柱强化胶体墙412另包含一胶体401，附着在金属柱311或金属柱312的表面上。根据本发明一实施例，成型模料500的组成与胶体401的组成不同。
请参阅图8及图9，其为依据本发明另一实施例所绘示的一种具有封装内隔室屏蔽的半导体封装的制作方法示意图，其中相同的层、组件或材料仍沿用相同的符号来表示。如图8所示，类似的，半导体封装2在基板100的顶表面100a上可以设置有多个彼此靠近的半导体芯片10～12。例如，半导体芯片10可以是电源管理芯片(PMIC)，半导体芯片11可以是射频芯片(RFIC)，半导体芯片12可以是功率放大器芯片(PAIC)，但不限于此。根据本发明一实施例，在基板100的顶表面100a上至少设置有一高频芯片，例如，半导体芯片11，以及易受高频讯号干扰的电路组件或芯片，例如，半导体芯片12。
根据本发明一实施例，例如，半导体芯片10及12可以是以打线接合方式设置在基板100的顶表面100a上，半导体芯片11可以是以覆晶接合方式设置在基板100的顶表面100a上，但不限于此。根据本发明一实施例，半导体芯片10～12可以是裸晶形式或者芯片封装形式。
根据本发明一实施例，在基板100的顶表面100a上可以另设置有多个被动组件13。例如，被动组件13可以是电容组件、电感组件、电阻组件等，但不限于此。根据本发明一实施例，被动组件13可以是利用表面黏着技术(SMT)设置在基板100的顶表面100a上，但不限于此。根据本发明一实施例，被动组件13可以设置在半导体芯片10～12之间的基板100的顶表面100a上。
根据本发明一实施例，例如，在半导体芯片10～12的周围的基板100的顶表面100a上，分别设置有接地环210、211及212，其中，接地环210环绕着半导体芯片10，接地环211环绕着半导体芯片11，而接地环212环绕着半导体芯片12。根据本发明一实施例，接地环210～212可以是连续的环状图案，但不限于此。在其他实施例中，接地环210～212可以是连续的环状图案或者是排列成环状的接垫图案。
根据本发明一实施例，在接地环210上设置有多个金属柱310，在接地环211上设置有多个金属柱311，而在接地环212上设置有多个金属柱312。根据本发明一实施例，金属柱310～312可以是包含铜、银、金、铝、镍、钯、其任何组合或合金，或任何合适的导电材料。例如，金属柱310～312可以是铜柱或铜镍合金柱，但不限于此。根据本发明一实施例，金属柱310～312至少排列成一列，但不限于此。
根据本发明一实施例，金属柱310～312可以是利用打线方式形成的，其中各金属柱310～312一端分别固定在接地环210～212上，另一端则是悬空的，如图1所示，各金属柱310～312笔直的朝向上，如同围篱般分别围绕着半导体芯片10～12。图8绘示金属柱310～312分别完全连续的围绕着半导体芯片10～12。
接着进行一喷胶制程，利用一喷头40将一胶体401沿着接地环210～212喷洒在金属柱310～312上，其中使胶体401附着在金属柱310～312的表面上并填入金属柱310～312之间的空隙。根据本发明一实施例，胶体401可以是热固性树脂、热塑性树脂、UV固化树脂等，但不限于此。根据本发明一实施例，胶体401可以是导电胶，例如，银胶或铝胶。根据本发明一实施例，胶体401可以包含有导电颗粒，例如，铜、银、金、铝、镍、钯、其任何组合或合金、石墨烯，或任何合适的导电材料。根据本发明一实施例，胶体401还可以包含有填充物(filler)，例如，石英颗粒、钻石颗粒等。根据本发明一实施例，胶体401还可以包含有溶剂或添加剂(例如，交联剂、催化剂或改质剂)等。
后续，可以进行一固化制程，例如，加热或UV照射，使得黏附在金属柱310～312表面上的胶体401达到固化或者半固化的程度。胶体401可以强化金属柱310～312，使其在制程中不会倒塌，此外，也可以提升电磁干扰的屏蔽效果及散热效能。在完成固化制程之后，即在基板100的顶表面100a上形成金属柱强化胶体墙410～412，其中金属柱强化胶体墙410包含环绕着半导体芯片10的金属柱310及经过固化或半固化的胶体401，金属柱强化胶体墙411包含环绕着半导体芯片11的金属柱311及经过固化或半固化的胶体401，金属柱强化胶体墙412包含环绕着半导体芯片12的金属柱312及经过固化或半固化的胶体401。
根据本发明其它实施例，若金属柱310～312的线径较粗，例如，大于或等于25微米，或者，大于或等于35微米，此时，也可以省略喷胶制程。或者，只有部分的金属柱310～312有被喷胶。
如图9所示，接着进行一模封制程，分别在基板100的顶表面100a上的金属柱强化胶体墙410～412内形成成型模料501～503。根据本发明一实施例，成型模料501～503可以包含树脂材料，例如，热固性树脂、热塑性树脂、UV固化树脂等，但不限于此。根据本发明一实施例，成型模料501～503的组成与胶体401的组成不同，例如，胶体401的组成中可以包含有导电颗粒，而成型模料501～503的组成中则通常不含有导电颗粒。然而，本发明并不限于此，在其它实施例中，成型模料501～503的组成与胶体401的组成可以相同，或者使成型模料501～503与胶体401的热膨胀系数、应力或弹性系数等物性能够互相匹配。
根据本发明一实施例，成型模料501～503不会溢出金属柱强化胶体墙410～412，故不会覆盖金属柱强化胶体墙411及412以外的区域。换言之，成型模料501覆盖住半导体芯片10和打线102，成型模料502覆盖住半导体芯片11，成型模料503覆盖住半导体芯片12打线122。金属柱强化胶体墙411及412以外的区域，包括被动组件13不会被成型模料500包封住，而可以显露出来。根据本发明一实施例，成型模料501～503可以利用各种合适的方法形成，例如，压缩模制或点胶制程，但不限于此。根据本发明一实施例，上述模封制程可以进一步包含一固化制程，例如，热固化制程。由于仅部分重要的组件是被成型模料501～503包封保护住，故基板100的受到成型模料501～503的应力影响可以减小，进而改善半导体封装2的翘曲(warpage)问题。后续，可以再进行如图4及图5所示的研磨制程及导电层涂布制程，不另赘述。
根据本发明另一实施例，本公开另揭露一种单芯片封装。如图10及图11所示，在基板100的顶表面100a上设有单颗半导体芯片10，例如，处理器等。在基板100的底表面100b上设有连接件108，例如，球栅数组(ball grid array,BGA)锡球。半导体芯片10可以透过以打线接合方式设置在基板100的顶表面100a上(如图10所示的打线102)，或者半导体芯片10可以透过以覆晶接合方式设置在基板100的顶表面100a上(如图11)。在基板100的顶表面100a上，同样设有一接地环210，环绕着半导体芯片10。在接地环210上设有一金属柱强化胶体墙410，环绕着半导体芯片10。金属柱强化胶体墙410包含复数个金属柱310，其中各金属柱310的一端固定在接地环210上，另一端则悬空，且复数个金属柱310围绕着半导体芯片10。金属柱强化胶体墙410另包含一胶体401，附着在金属柱310的表面上。在金属柱强化胶体墙410内设有一成型模料501。根据本发明一实施例，成型模料501的组成与胶体401的组成不同，例如，胶体401的组成中可以包含有导电颗粒，例如铜、银、金、铝、镍、钯、其任何组合或合金、石墨烯。成型模料501的组成中则不含有导电颗粒。然而，本发明并不限于此，在其它实施例中，成型模料501的组成与胶体401的组成可以相同，或者使成型模料501与胶体401的热膨胀系数、应力或弹性系数等物性能够互相匹配。成型模料501不会溢出金属柱强化胶体墙410，故不会覆盖金属柱强化胶体墙410以外的区域。成型模料501可以利用各种合适的方法形成，例如，压缩模制或点胶制程，但不限于此。由于仅半导体芯片10是被成型模料501包封保护住，故基板100的受到成型模料501的应力影响可以减小，进而改善翘曲问题。后续，可以再进行如图4及图5所示的研磨制程及导电层涂布制程，不另赘述。
相较于现有技术，本发明至少具有以下优点：(1)能与现有制程兼容，且制程步骤简化因此成本相对较低；(2)可以最小化半导体封装或模块的尺寸；(3)在基板上形成金属柱强化胶体墙或隔室屏蔽结构具有高度弹性；(4)能达到高产能量产(high UPH massproduction)；以及(5)透过调整金属柱的排数(tier)、线径及/或间隔等，可以弹性的应用到各种所欲遮蔽电磁辐射的频率范围。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是在本发明的发明构思下，利用本发明说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本发明的专利保护范围内。

Claims (16)

1.一种具有封装内隔室屏蔽的半导体封装，其特征在于，包括：
一基板，在该基板的一顶表面上至少设置有一高频芯片，以及易受高频讯号干扰的一电路组件；
一第一接地环，在该基板的该顶表面上，环绕着该高频芯片；
一第一金属柱强化胶体墙，设在该第一接地环上，环绕着该高频芯片；
一第二接地环，在该基板的该顶表面上，环绕着该电路组件；
一第二金属柱强化胶体墙，设在该第二接地环上，环绕着该电路组件；
一成型模料，至少覆盖该高频芯片及该电路组件，所述成型模料不会覆盖所述第一金属柱强化胶体墙及所述第二金属柱强化胶体墙以外的区域；以及
一导电层，设于该成型模料上，并且与该第一金属柱强化胶体墙及/或该第二金属柱强化胶体墙接触；
该第一金属柱强化胶体墙包含复数个第一金属柱，其中各该复数个第一金属柱的一端固定在该第一接地环上，另一端则悬空，该复数个第一金属柱围绕着该高频芯片；
该第二金属柱强化胶体墙包含复数个第二金属柱，其中各该复数个第二金属柱的一端固定在该第二接地环上，另一端则悬空，该复数个第二金属柱围绕着该电路组件；
在该高频芯片及该电路组件的之间的重迭处，该第一金属柱与该第二金属柱之间是彼此交错的排列。
2.如权利要求1所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该第一金属柱强化胶体墙或该第二金属柱强化胶体墙另包含一胶体，附着在该第一或该第二金属柱的表面上。
3.如权利要求2所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该胶体包含热固性树脂、热塑性树脂或UV固化树脂。
4.如权利要求2所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该胶体系为一导电胶。
5.如权利要求2所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该胶体包含有导电颗粒。
6.如权利要求5所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该导电颗粒包含铜、银、金、铝、镍、钯、其任何组合或合金、石墨烯。
7.如权利要求5所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该成型模料的组成与该胶体的组成不同。
8.如权利要求1所述的具有封装内隔室屏蔽的半导体封装，其特征在于，该成型模料的上表面与该第一及该第二金属柱强化胶体墙的顶面是齐平的。
9.一种具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，包含：
提供一基板，在该基板的一顶表面上至少设置有一高频芯片，以及易受高频讯号干扰的一电路组件，其中该基板的该顶表面上另设有一第一接地环，环绕着该高频芯片，以及一第二接地环，环绕着该电路组件；
在该第一接地环上形成一第一金属柱强化胶体墙，环绕着该高频芯片；
在该第二接地环上形成一第二金属柱强化胶体墙，环绕着该电路组件；
形成一成型模料，至少覆盖该高频芯片及该电路组件，所述成型模料不会覆盖所述第一金属柱强化胶体墙及所述第二金属柱强化胶体墙以外的区域；以及
于该成型模料上形成一导电层，使该导电层与该第一金属柱强化胶体墙及/或该第二金属柱强化胶体墙接触；
形成复数个第一金属柱，其中各该复数个第一金属柱的一端固定在该第一接地环上，另一端则悬空，该复数个第一金属柱围绕着该高频芯片；
形成复数个第二金属柱，其中各该复数个第二金属柱的一端固定在该第二接地环上，另一端则悬空，该复数个第二金属柱围绕着该电路组件；
在该高频芯片及该电路组件的之间的重迭处，该第一金属柱与该第二金属柱之间是彼此交错的排列。
10.如权利要求9所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，另包含：
形成一胶体，附着在该第一或该第二金属柱的表面上。
11.如权利要求10所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该胶体包含热固性树脂、热塑性树脂或UV固化树脂。
12.如权利要求10所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该胶体系为一导电胶。
13.如权利要求10所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该胶体包含有导电颗粒。
14.如权利要求13所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该导电颗粒包含铜、银、金、铝、镍、钯、其任何组合或合金、石墨烯。
15.如权利要求13所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该成型模料的组成与该胶体的组成不同。
16.如权利要求9所述的具有封装内隔室屏蔽的半导体封装的制作方法，其特征在于，该成型模料的上表面与该第一及该第二金属柱强化胶体墙的顶面是齐平的。
CN201811559391.5A 2018-11-28 2018-12-19 半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法 Active CN111244067B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107142358 2018-11-28
TW107142358A TWI744572B (zh) 2018-11-28 2018-11-28 具有封裝內隔室屏蔽的半導體封裝及其製作方法

Publications (2)

Publication Number Publication Date
CN111244067A CN111244067A (zh) 2020-06-05
CN111244067B true CN111244067B (zh) 2022-05-24

Family

ID=65138839

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811559391.5A Active CN111244067B (zh) 2018-11-28 2018-12-19 半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法

Country Status (6)

Country Link
US (1) US10847480B2 (zh)
EP (1) EP3660897A1 (zh)
JP (1) JP6737914B2 (zh)
KR (1) KR102270465B1 (zh)
CN (1) CN111244067B (zh)
TW (1) TWI744572B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200107201A (ko) * 2019-03-06 2020-09-16 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US11089673B2 (en) * 2019-07-19 2021-08-10 Raytheon Company Wall for isolation enhancement
CN114158256A (zh) * 2020-06-17 2022-03-08 株式会社藤仓 无线模块
CN114068493A (zh) * 2020-07-31 2022-02-18 华为技术有限公司 一种封装模组及其封装方法、电子设备
CN113809049A (zh) * 2021-09-17 2021-12-17 中国电子科技集团公司第五十八研究所 一种高屏蔽性和隔离度的射频芯片封装结构及封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107535081A (zh) * 2015-05-11 2018-01-02 株式会社村田制作所 高频模块
CN107808854A (zh) * 2016-09-09 2018-03-16 东和株式会社 电子电路装置及电子电路装置的制造方法
WO2018101382A1 (ja) * 2016-12-02 2018-06-07 株式会社村田製作所 高周波モジュール
JPWO2018164158A1 (ja) * 2017-03-08 2019-12-19 株式会社村田製作所 高周波モジュール

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256590A (en) 1989-11-24 1993-10-26 Mitsubishi Denki Kabushiki Kaisha Method of making a shielded semiconductor device
JPH04199667A (ja) 1990-11-29 1992-07-20 Fujitsu Ltd パッケージとその半田付け方法
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5354951A (en) 1993-03-15 1994-10-11 Leader Tech, Inc. Circuit board component shielding enclosure and assembly
SE9701006L (sv) * 1997-03-19 1998-09-20 Electrolux Ab Hållare för en dammsugarpåse
US6194655B1 (en) 1999-03-01 2001-02-27 Leader Tech, Inc. Circuit board component shielding enclosure and assembly having opposing covers interfitted with upper and lower portions of enclosure
WO2002071547A1 (en) 2001-03-02 2002-09-12 Koninklijke Philips Electronics N.V. Module and electronic device
US6465280B1 (en) 2001-03-07 2002-10-15 Analog Devices, Inc. In-situ cap and method of fabricating same for an integrated circuit device
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
WO2005099331A1 (ja) * 2004-03-30 2005-10-20 Matsushita Electric Industrial Co., Ltd. モジュール部品およびその製造方法
EP1594163A1 (en) 2004-05-03 2005-11-09 Commissariat A L'energie Atomique A screened electrical device and a process for manufacturing the same
US7629674B1 (en) * 2004-11-17 2009-12-08 Amkor Technology, Inc. Shielded package having shield fence
KR20080023996A (ko) 2006-09-12 2008-03-17 주식회사 하이닉스반도체 반도체 패키지
SG161252A1 (en) 2007-03-13 2010-05-27 Towa Corp Method of compression molding for electronic part and apparatus therefor
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
JP2009070882A (ja) 2007-09-11 2009-04-02 Kyushu Institute Of Technology 半導体チップパッケージ及びその製造方法
US9123663B2 (en) * 2008-06-10 2015-09-01 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer grounded through metal pillars formed in peripheral region of the semiconductor
JP2010056180A (ja) 2008-08-26 2010-03-11 Sanyo Electric Co Ltd 回路モジュール
US20100110656A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
KR101712216B1 (ko) 2008-12-10 2017-03-03 스미토모 베이클리트 컴퍼니 리미티드 반도체 봉지용 수지 조성물, 반도체 장치의 제조 방법 및 반도체 장치
JP2010225620A (ja) 2009-03-19 2010-10-07 Panasonic Corp 回路モジュール
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8199518B1 (en) * 2010-02-18 2012-06-12 Amkor Technology, Inc. Top feature package and method
JP5619466B2 (ja) 2010-04-13 2014-11-05 デクセリアルズ株式会社 硬化性樹脂組成物、接着性エポキシ樹脂ペースト、ダイボンド剤、非導電性ペースト、接着性エポキシ樹脂フィルム、非導電性エポキシ樹脂フィルム、異方性導電ペースト及び異方性導電フィルム
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
TWI523158B (zh) * 2010-10-11 2016-02-21 日月光半導體製造股份有限公司 雙面封裝結構及應用其之無線通訊系統
US8759950B2 (en) 2011-05-05 2014-06-24 Intel Corporation Radio- and electromagnetic interference through-silicon vias for stacked-die packages, and methods of making same
KR20130010359A (ko) * 2011-07-18 2013-01-28 삼성전자주식회사 반도체 장치용 기판 및 그를 포함한 반도체 장치
KR101798571B1 (ko) * 2012-02-16 2017-11-16 삼성전자주식회사 반도체 패키지
JP5627619B2 (ja) 2012-02-28 2014-11-19 Ｔｏｗａ株式会社 樹脂封止装置及び樹脂封止体の製造方法
JPWO2013183671A1 (ja) 2012-06-08 2016-02-01 日立化成株式会社 半導体装置の製造方法
US20140048914A1 (en) * 2012-08-14 2014-02-20 Bridge Semiconductor Corporation Wiring board with embedded device and electromagnetic shielding
US10091918B2 (en) 2012-12-11 2018-10-02 Qualcomm Incorporated Methods and apparatus for conformal shielding
CN104870585B (zh) 2012-12-21 2017-06-20 道康宁公司 用于压缩模制或层合的热熔型固化性有机硅组合物
US9419667B2 (en) * 2013-04-16 2016-08-16 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
KR101698289B1 (ko) 2013-11-07 2017-01-19 아사히 가라스 가부시키가이샤 이형 필름, 및 반도체 패키지의 제조 방법
WO2015068807A1 (ja) 2013-11-07 2015-05-14 旭硝子株式会社 離型フィルム、および半導体パッケージの製造方法
JP6156085B2 (ja) 2013-11-14 2017-07-05 株式会社デンソー モールドパッケージの製造方法
KR102163707B1 (ko) 2013-11-14 2020-10-08 에스케이하이닉스 주식회사 전자기간섭 차폐층을 갖는 반도체 패키지 및 테스트 방법
US10586771B2 (en) * 2013-12-16 2020-03-10 Utac Headquarters Pte, Ltd Conductive shield for semiconductor package
TWI553807B (zh) * 2014-06-13 2016-10-11 思鷺科技股份有限公司 封裝結構
JP5944445B2 (ja) 2014-07-18 2016-07-05 Ｔｏｗａ株式会社 樹脂封止電子部品の製造方法、突起電極付き板状部材、樹脂封止電子部品、及び突起電極付き板状部材の製造方法
US9826630B2 (en) 2014-09-04 2017-11-21 Nxp Usa, Inc. Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof
JP6444707B2 (ja) 2014-11-28 2018-12-26 Ｔｏｗａ株式会社 電子部品、その製造方法及び製造装置
WO2016111512A1 (en) * 2015-01-09 2016-07-14 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
CN208000908U (zh) 2015-03-26 2018-10-23 苹果公司 系统级封装模块
CN107710406B (zh) 2015-06-04 2020-10-16 株式会社村田制作所 高频模块
US9913385B2 (en) 2015-07-28 2018-03-06 Bridge Semiconductor Corporation Methods of making stackable wiring board having electronic component in dielectric recess
US10304811B2 (en) * 2015-09-04 2019-05-28 Hong Kong Beida Jade Bird Display Limited Light-emitting diode display panel with micro lens array
US9786838B2 (en) 2015-10-13 2017-10-10 Everspin Technologies, Inc. Packages for integrated circuits and methods of packaging integrated circuits
US20170117229A1 (en) 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with trench features to provide internal shielding between electronic components
US9721903B2 (en) 2015-12-21 2017-08-01 Apple Inc. Vertical interconnects for self shielded system in package (SiP) modules
TW201724648A (zh) 2015-12-22 2017-07-01 矽品精密工業股份有限公司 電子封裝件
JP6623747B2 (ja) 2015-12-25 2019-12-25 日立化成株式会社 配線基板の製造方法
KR20170079381A (ko) * 2015-12-30 2017-07-10 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
US9953929B2 (en) 2016-03-18 2018-04-24 Intel Corporation Systems and methods for electromagnetic interference shielding
JP5988003B1 (ja) 2016-03-23 2016-09-07 Tdk株式会社 電子回路パッケージ
US9685413B1 (en) 2016-04-01 2017-06-20 Intel Corporation Semiconductor package having an EMI shielding layer
US20170287870A1 (en) * 2016-04-01 2017-10-05 Powertech Technology Inc. Stacked chip package structure and manufacturing method thereof
US9907179B2 (en) 2016-04-25 2018-02-27 Tdk Corporation Electronic circuit package
US9935075B2 (en) * 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10076023B2 (en) 2016-09-30 2018-09-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
JP6654994B2 (ja) 2016-10-31 2020-02-26 Ｔｏｗａ株式会社 回路部品の製造方法
JP2018142611A (ja) 2017-02-27 2018-09-13 信越化学工業株式会社 半導体装置の製造方法
TWM547185U (zh) 2017-04-10 2017-08-11 吳明哲 選擇性電磁遮蔽封裝體結構
KR20190014865A (ko) 2017-08-04 2019-02-13 주식회사 바른전자 반도체 패키지의 제조방법
US10861761B2 (en) 2017-09-29 2020-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaged wafer and method for forming the same
US10535612B2 (en) * 2017-12-15 2020-01-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11984439B2 (en) * 2018-09-14 2024-05-14 Intel Corporation Microelectronic assemblies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107535081A (zh) * 2015-05-11 2018-01-02 株式会社村田制作所 高频模块
CN107808854A (zh) * 2016-09-09 2018-03-16 东和株式会社 电子电路装置及电子电路装置的制造方法
WO2018101382A1 (ja) * 2016-12-02 2018-06-07 株式会社村田製作所 高周波モジュール
JPWO2018164158A1 (ja) * 2017-03-08 2019-12-19 株式会社村田製作所 高周波モジュール

Also Published As

Publication number Publication date
JP6737914B2 (ja) 2020-08-12
KR20200064859A (ko) 2020-06-08
KR102270465B1 (ko) 2021-06-29
EP3660897A1 (en) 2020-06-03
US20200168566A1 (en) 2020-05-28
US10847480B2 (en) 2020-11-24
JP2020088366A (ja) 2020-06-04
TW202021079A (zh) 2020-06-01
CN111244067A (zh) 2020-06-05
TWI744572B (zh) 2021-11-01

Similar Documents

Publication Publication Date Title
CN111244067B (zh) 半导体封装、具有封装内隔室屏蔽的半导体封装及其制作方法
KR100782774B1 (ko) Ｓｉｐ 모듈
US8012868B1 (en) Semiconductor device having EMI shielding and method therefor
US11239179B2 (en) Semiconductor package and fabrication method thereof
US7851894B1 (en) System and method for shielding of package on package (PoP) assemblies
US8129824B1 (en) Shielding for a semiconductor package
US10923435B2 (en) Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance
JP6931694B2 (ja) パッケージ内コンパートメントシールドを備える半導体パッケージ及びその製造方法
KR101563910B1 (ko) 반도체 패키지 및 이의 제조 방법
US11923319B2 (en) Semiconductor package including sheilding cover that covers molded body
US20200168557A1 (en) Semiconductor package and fabrication method thereof
US10896880B2 (en) Semiconductor package with in-package compartmental shielding and fabrication method thereof
KR102237783B1 (ko) 반도체 패키지 및 그것의 제조 방법
KR102378155B1 (ko) 패키지 내 구획 차폐물 및 능동 전자기 적합성 차폐물을 갖는 반도체 패키지
US11211340B2 (en) Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding
TW202034471A (zh) 半導體封裝及其製作方法
KR20240049511A (ko) 반도체 디바이스 상에 차폐 층을 형성하는 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant