CN110691457A - 电路板和电路组件 - Google Patents
电路板和电路组件 Download PDFInfo
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- CN110691457A CN110691457A CN201910593038.7A CN201910593038A CN110691457A CN 110691457 A CN110691457 A CN 110691457A CN 201910593038 A CN201910593038 A CN 201910593038A CN 110691457 A CN110691457 A CN 110691457A
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Abstract
本发明提供能够实现散热性的提高的电路板和电路组件。本发明的一个方式涉及的电路板具有芯基材、第一外装基材、第二外装基材。上述芯基材具有金属制的芯层,该金属制的芯层具有能够支承安装部件的第一主面和与上述第一主面相反侧的第二主面。上述第一外装基材与上述第一主面相对地配置,且具有收纳搭载于上述第一主面的安装部件的凹部。上述第二外装基材与上述第二主面相对地配置,且具有包括与上述第二主面连接的通路的散热层。
Description
技术领域
本发明涉及散热性优异的电路板和电路组件。
背景技术
随着信息通信产业的扩大,对于电子设备的需求越来越多样化,对于开发和量产开始的早期化的需求也提高。例如,专利文献1中公开了内置有面发光型半导体激光、面发光型受光元件、电子设备等的部件内置基板。
现有技术文献
专利文献
专利文献1:日本特开2004-163722号公报
发明内容
发明所要解决的技术问题
近年来,关于搭载于高功能的电子设备的电路板,正进行着高密度安装化、小型薄型化、进而功能模块的组件化,为了防止部件的发热导致的劣化和误动作而需求电路板的有效的散热对策。
鉴于以上的情况,本发明的目的在于:提供能够实现散热性的提高的电路板和电路组件。
用于解决问题的技术方案
为了实现上述目的,本发明的一个方式涉及的电路板具有芯基材、第一外装基材、第二外装基材。
上述芯基材具有金属制的芯层,该金属制的芯层具有能够支承安装部件的第一主面和与上述第一主面相反侧的第二主面。
上述第一外装基材与上述第一主面相对地配置,且具有收纳搭载于上述第一主面的安装部件的凹部。
上述第二外装基材与上述第二主面相对地配置,且具有包括与上述第二主面连接的通路的散热层。
在上述电路板中,由于具有经由通路与支承安装部件的芯层热连接的散热层,因此能够提高芯层的散热性,从而能够防止安装部件的发热导致的劣化和误动作。
上述通路可以包括与上述第二主面上的多个部位连接的多个通路部。由此,从芯层向散热层的传热更有效。
上述第一外装基材可以具有能够收纳安装部件的凹部和第一配线层。上述第一配线层包括:与收纳于上述凹部的安装部件电连接的连接端子;和具有比上述连接端子大的面积,且与能够搭载于上述第一外装基材上的测温元件的至少一个电极连接的集热用端子。
由此,能够有效地收集芯层的发热,所以能够提高使用了测温元件的芯基材的测温精度。
上述第二外装基材还可以具有第二配线层。上述第二配线层与上述散热层相对地配置,且与上述芯层和上述散热层电绝缘。
由此,能够将芯层和第二配线层连接于不同的电位源。
上述第一外装基材可以是多层配线基材。
上述芯基材还可以具有包括收纳上述芯层的开口部的挠性配线部件。
本发明的一个方式涉及的电路组件具有发热性元件、芯基材、第一外装基材和第二外装基材。
上述芯基材具有金属制的芯层,该金属制的芯层具有能够搭载上述发热性元件的第一主面和与上述第一主面相反侧的第二主面。
上述第一外装基材与上述第一主面相对地配置,具有收纳上述发热性元件的凹部,且具有与上述发热性元件电连接的第一配线层。
上述第二外装基材与上述第二主面相对地配置,且具有包括与上述第二主面连接的通路的散热层。
上述电路组件还可以具有测温元件。上述第一配线层可以具有:与上述发热性元件电连接的连接端子;和具有比上述连接端子大的面积,且与上述测温元件的至少一个电极连接的集热用端子。
上述发热性元件可以是半导体发光元件。
上述第二外装基材还可以具有第二配线层。上述第二配线层与上述散热层相对地配置,与上述芯层和上述散热层电绝缘。
发明效果
如上所述,根据本发明,能够实现散热性的提高。
附图说明
图1是表示具有本发明的一个实施方式涉及的电路板的电路组件的概略俯视图。
图2是图1的A-A线概略截面图。
图3是表示上述电路板的一个应用例的概略侧面图。
图4是表示上述电路板的集热用端子的另外方式的概略俯视图。
图5是表示上述电路板的主要部分的另外结构例的概略侧截面图。
附图标记说明
1…电路组件
10…第一基板主体
20…第二基板主体
21…第一外装基材
22…第二外装基材
23…芯基材
100…电路板
110…开口部
210…凹部
212…第一配线层
215…第一连接端子
217、217a、217b…第二连接端子(集热用端子)
222…通路
223…散热层
224…第二配线层
230…芯层
231…第一主面
232…第二主面
D1…发光元件
D2…测温元件
具体实施方式
以下,参照附图对本发明的实施方式进行说明。
图1是表示具有本发明的一个实施方式涉及的电路板100的电路组件1的概略俯视图,图2是图1的A-A线概略截面图。
在各图中,X轴、Y轴和Z轴表示相互正交的3轴方向,Z轴相当于电路板100的厚度方向。
[电路板的结构]
本实施方式的电路板100具有第一基板主体10、第二基板主体20、第三基板主体30。
第一基板主体10由将第二基板主体20和第三基板主体30之间进行机械连接以及电连接的挠性配线基材11构成,在电路板100中构成柔性部。第二基板主体20和第三基板主体30在电路板100中构成刚性部。第二基板主体20构成为能够搭载发光元件D1和测温元件D2等各种电子部件的支承基板,第三基板主体30与未图示的电子设备的控制基板连接。此外,电路板100典型地与第三基板主体30一体构成,也可以作为与第三基板主体30经由连接器等连接部件连接的另外部件而构成。
(第一基板主体)
构成第一基板主体10的挠性配线基材11典型地在X轴方向为长度方向,在Y轴方向为宽度方向,长度方向的一端部(第一端部11a)构成第二基板主体20的芯基材的一部分,另一端部(第二端部11b)构成第三基板主体30的一部分。
挠性配线基材11由具有树脂制芯、设置于其两面的配线层、覆盖配线层的绝缘层的层叠体构成。树脂制芯例如由聚酰亚胺或聚对苯二甲酸乙二醇酯等的单层或多层的挠性塑料膜构成。配线层典型地由铜或铝等金属材料构成。另外,绝缘层由具有粘接层的聚酰亚胺等挠性塑料膜构成。配线层的一部分经由设置于树脂制芯的适当位置的通孔或通路相互电连接。挠性配线基材11的配线层不限于2层,也可以是1层或3层以上。
(第二基板主体)
第二基板主体20具有第一外装基材21、第二外装基材22、芯基材23的层叠结构。
(芯基材)
芯基材23包括金属制的芯层230。芯层230由金属材料构成,典型地由铜或其合金、铝或其合金、铁或其合金构成,金属的种类不限定于此。其中,优选导热率较高的材料,例如铜或其合金。
芯层230由具有能够支承安装部件(发光元件D1)的第一主面231和其相反侧的第二主面232的金属板构成。芯层230的平面形状没有特别限定,典型地是矩形,但不限于此,也可以是圆形、椭圆形、五角形等多角(边)形等。芯层230具有:作为用于对第二基板主体20赋予确保高的平面性或平坦性的刚性的芯材(增强层)的功能;和作为吸收发光元件D1驱动时产生的热的散热片的功能。芯层230的厚度没有特别限定,例如为100μm以上且400μm以下。芯层230的厚度可以与挠性配线基材11相同,也可以比其厚或比其薄。
芯层230被收纳在设置于挠性配线基材11的第一端部11a的开口部110。开口部110形成为与芯层230的形状对应的形状,在本例中形成为矩形(参照图1)。因此,挠性配线基材11的第一端部11a形成为矩形的框状。开口部110具有比芯层230大的面积,在开口部110的内周面与芯层230的外周面之间充填有粘接性的树脂材料112(参照图2)。由此,构成挠性配线基材11的第一端部11a和芯层230一体接合而成的芯基材23。
第一外装基材21和第二外装基材22具有与挠性配线基材11的第一端部11a的形状对应的矩形的平面形状,以比芯层230的第一和第二主面231、232大的面积形成(参照图1)。第一外装基材21与芯层230的第一主面231相对地配置,第二外装基材22与芯层230的第二主面232相对地配置。
(第一外装基材)
第一外装基材21由绝缘层211(第一绝缘层)和配线层212(第一配线层)交替层叠而成的配线基材构成,在本实施方式中,由具有2层以上的配线层的多层配线基材构成,也可以由单层的配线基材构成。绝缘层211典型地由玻璃环氧系树脂、双马来酸酐缩亚胺三嗪树脂(BT树脂)等树脂材料构成,配线层212由铜或铝等金属材料构成。配线层212在第一外装基材21的内层和表层图案化成规定的形状。
第一外装基材21具有收纳搭载于芯层230的第一主面231的安装部件(发光元件D1)的凹部(或收纳部)210。凹部210是以使芯层230的第一主面231向外部露出的深度形成的矩形的开口部(参照图1)。凹部210的大小和位置没有特别限定,只要是能够收纳发光元件D1的大小,且是芯层230的配置区域,就没有特别限定。另外,所收纳的元件的数量也不限于一个,也可以是多个。凹部210的深度如图2所示,以比发光元件D1的高度(厚度)尺寸大的深度形成,当然不限于此。
发光元件D1典型地使用半导体发光元件。作为半导体发光元件,可以列举发光二极管、激光二极管等,在本实施方式中采用VCSEL(Vertical Cavity Surface EmittingLASER:垂直揩振器面发光激光),以相对于芯层230的第一主面231在垂直方向上射出光的方式收纳于凹部210。
此外,搭载于凹部210的元件不限于发光元件D1,可以采用图像传感器、功率半导体元件(例如晶体管或二极管)等其他的半导体元件或半导体封装部件,特别适合的是发热性元件。
在本实施方式中,发光元件D1在正面(图2中上面)具有阴极,在背面(图2中下面)具有阳极。阴极经由单个或多个接合线(bondingwire)214与第一连接端子215电连接,阳极经由导电层213与芯层230的第一主面231电连接。第一连接端子215构成第一外装基材21的配线层212的一部分,配置于凹部210的外侧的第一外装基材21的表面。导电层213例如由焊料、银膏、导电性粘接剂构成。发光元件D1也可以不经由导电层213例如以倒装片方式搭载于第一主面231上。
发光元件D1的电极的位置不限于上述的例子,也可以采用在元件的表面侧配置有阳极和阴极的元件结构。在该情况下,阳极和阴极分别与规定的连接端子进行引线接合。在该情况下,元件的背面侧也经由导电层与芯层230接合。由此,可以形成从元件向芯层230的热的传递路径。
位于第一外装基材21的表层的配线层212如图1所示,包括与发光元件D1连接的第一连接端子215和与测温元件D2连接的一对第二连接端子217、218。第一连接端子217经由多根接合线214与发光元件D1的阴极电连接。一对第二连接端子217、218与测温元件D2的两外部电极进行焊料连接。
测温元件D2可以采用能够电检测温度变化的半导体元件例如热敏电阻。测温元件D2测定发光元件D1的驱动引起的发热量,在检测到规定以上的温度时,作为用于停止或限制发光元件D1的动作的温度管理用元件发挥功能。
在本实施方式中,第二连接端子217、218隔着绝缘层211与芯层230相对置,其中一个端子217具有比另一个端子218大的面积。另外,第二连接端子217、218中的一个端子217可以以与第一连接端子215相同的面积形成,但在本实施方式中,构成为以比第一连接端子215大的面积形成的集热用端子(参照图1)。由此,提高该端子217产生的从芯层230的受热效率,所以能够提高测温元件D2带来的发光元件D1的周围温度的测定精度,能够有效地保护发光元件D1,以免其由于发热而导致劣化、损伤。集热用的第二连接端子217优选配置于凹部210的附近。由此,提高发光元件D1的温度的检测精度。第二连接端子217的形状也不限于图1所示的例子(后述)。
(第二外装基材)
第二外装基材22具有:覆盖芯层230的第二主面232的绝缘层221和包括与第二主面232连接的通路222的散热层223。通路222形成于绝缘层221的内部,包括与第二主面232上的多个部位连接的多个通路部V。散热层223作为将由芯层230吸收的发光元件D1的热量传递到芯层230的外部的散热线路发挥功能。另外,散热层223作为经由芯层230与发光元件D1的阳极连接的电力供给线路发挥功能。
散热层223由形成于绝缘层221的表面的全面状的导体图案形成。通路222和散热层223由相同的金属材料构成,典型地为铜镀层。即在覆盖芯层230的第二主面232的绝缘层221的适当位置形成多个贯通孔后,以充填这些贯通孔的方式形成铜镀层。镀敷法没有特别限定,可以是电解镀敷法,也可以是无电解镀敷法。将绝缘层221上的铜镀层以适当的形状形成图案,由此形成散热层223。通路222由多个通路部V构成,因此与由单一的大面积的层构成通路222的情况相比,能够稳定形成规定厚度(高度)的通路。
第二外装基材22还具有第二配线层224。第二配线层224配置于覆盖散热层223的绝缘层221之上。第二配线层224例如构成为与接地电位连接的接地线路。即,第二配线层224构成为与芯层230和散热层223电隔离(绝缘)的配线层。
第二配线层224可以由铜箔等金属膜构成,也可以由较厚的金属板构成。第二配线层224可以例如经由导电性粘接剂与未图示的壳体部接合。
[电路板的作用]
在如上构成的本实施方式的电路板100中,第二基板主体20的芯基材23具有金属制的芯层230,该芯层230的一个主面(第一主面231)构成为支承发光元件D1的支承面,因此与芯层为树脂制的情况相比,能够提高作为发热性元件的发光元件D1的散热性。另外,因芯层230为金属制,所以变形大,能够维持高的平面度。因此,能够抑制发光元件D1的面精度的偏差且能够稳定确保所希望的发光特性。
另外,在本实施方式的电路板100中,具有经由通路222与芯层230连接的散热层223,因此能够经由散热层223将芯层230的热量排放到外部。由此,能够实现发光元件D1的散热性的进一步提高,所以能够有效抑制发光元件D1的发热所导致的劣化。
而且,搭载测温元件D2的第二连接端子217作为集热用端子以较大的面积形成,因此能够可靠地检测出芯层230的温度上升。由此,发光元件D1的温度的推定变得容易,能够提高防止因发光元件D1的热量导致的劣化的效果。此外,对于另一个第二连接端子218也同样,可以以比第一连接端子215大的电极面积形成。
另外,散热层223与作为接地线路的第二配线层224电绝缘,因此,能够确保发光元件D1的稳定驱动。即,由于搭载电路组件1的电子设备的接地线路共用连接于接地电位上,所以根据设备的动作的时期有时在接地电位上产生变动。在这种情况下,因发光元件D1的电力供给线路(散热层223、芯层230)与接地线路(第二配线层224)隔离,因此能够使发光元件D1更稳定地动作。
在本实施方式的电路组件1中,发光元件D1可以构成为测距传感器和脸部识别设备。在该情况下,如图3所示,在第二基板主体20上搭载有接收从发光元件D1射出的光在对象物T上的反射光的受光传感器D3。在该情况下,可以在发光元件D1的光射出部还搭载分割光轴的衍射光栅等光学元件。由此,可以利用单一的发光设备获取多个反射光图案。
[变形例]
以上,对本发明的实施方式进行了说明,但本发明不限定于上述的实施方式,当然可以增加各种变更。
例如,在以上的实施方式中,作为电路板100,列举具有刚性部和柔性部的所谓刚柔基板为例进行了说明,但也可以由单一的刚性基板构成。在该情况下,金属制的芯层内置于玻璃环氧基板等通用的树脂基板的内部。
另外,在构成芯基材23的金属制的芯层230上可以形成能够收纳IC、无源部件等电子部件的空腔或层间连接用的贯通孔(通孔)。
另外,也可以适当设定搭载测温元件D2的集热用的第二连接端子217的电极形状,例如,可以以图4的A、B所示的方式构成。
图4的A所示的第二连接端子217a以环状形成于收纳发光元件D1的凹部210的周围。图4的B所示的第二连接端子217b还表示由环状的一部分形成的例子。在这些任一方式中,通过将第二连接端子217a、217b配置于作为发热源的发光元件D1的附近,由此能够提高从芯层230的集热性。
此外,在为刚柔基板的情况下,测温元件D1可以配置于发光元件与柔性部之间的任意区域。该区域与其他区域相比,由于热难以散出,因此通过测量比较容易充满热的区域的温度,能够提高发光元件D1的温度的推定精度。
另外,在以上的实施方式中,将发光元件D1经由导电层213与芯层230的第一主面231接合,但不限于此。例如,如图5所示的电路组件(第二基板主体),发光元件D1也可以隔着不锈钢等金属板31搭载于凹部210的底部。凹部210的底部只要是芯层230的第一主面231,则金属板31作为连接发光元件D1与芯层230之间的热传递层以及电极层发挥功能。另一方面,如图5所示,凹部210的底部由绝缘层211构成的情况下,通过在金属板31与芯层230之间设置金属制的通路32,能够将发光元件D1与芯层230之间进行电连接以及热连接。此外,在发光元件D1与金属板31之间优选存在焊料、银膏、导电性粘接剂等的导电层,或者也可以将发光元件D1以倒装片的方式接合在金属板31上。
Claims (11)
1.一种电路板,其特征在于,具有:
芯基材,其具有金属制的芯层,该金属制的芯层具有能够支承安装部件的第一主面和与所述第一主面相反侧的第二主面;
第一外装基材,其与所述第一主面相对地配置;和
第二外装基材,其与所述第二主面相对地配置,且具有包括与所述第二主面连接的通路的散热层。
2.如权利要求1所述的电路板,其特征在于:
所述通路包括与所述第二主面上的多个部位连接的多个通路部。
3.如权利要求1所述的电路板,其特征在于:
所述第一外装基材具有:
能够收纳安装部件的凹部;和
第一配线层,其包括:与收纳于所述凹部的安装部件电连接的第一连接端子;和具有比所述第一连接端子大的面积,且与能够搭载在所述第一外装基材上的测温元件的至少一个电极连接的第二连接端子。
4.如权利要求3所述的电路板,其特征在于:
所述第二连接端子是与所述测温元件的一对电极连接的一对端子,
所述一对端子中的一个端子具有比另一个端子大的面积。
5.如权利要求1所述的电路板,其特征在于:
所述第二外装基材还具有第二配线层,
所述第二配线层与所述散热层相对地配置,且与所述芯层和所述散热层电绝缘。
6.如权利要求1所述的电路板,其特征在于:
所述第一外装基材为多层配线基材。
7.如权利要求1所述的电路板,其特征在于:
所述芯基材还具有包括收纳所述芯层的开口部的挠性配线部件。
8.一种电路组件,其特征在于,具有:
发热性元件;
芯基材,其具有金属制的芯层,该金属制的芯层具有能够搭载所述发热性元件的第一主面和与所述第一主面相反侧的第二主面;
第一外装基材,其与所述第一主面相对地配置,具有收纳所述发热性元件的凹部,且具有与所述发热性元件电连接的第一配线层;和
第二外装基材,其与所述第二主面相对地配置,且具有包括与所述第二主面连接的通路的散热层。
9.如权利要求8所述的电路组件,其特征在于:
还具有测温元件,
所述第一配线层包括:与所述发热性元件电连接的第一连接端子;和具有比所述第一连接端子大的面积,且与所述测温元件的至少一个电极连接的第二连接端子。
10.如权利要求8所述的电路组件,其特征在于:
所述发热性元件为半导体发光元件。
11.如权利要求8所述的电路组件,其特征在于:
所述第二外装基材还具有与所述散热层相对地配置且与所述芯层和所述散热层电绝缘的第二配线层。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002231862A (ja) * | 2001-02-05 | 2002-08-16 | Fujitsu Quantum Devices Ltd | 半導体装置及びチップキャリア |
US20030002260A1 (en) * | 2001-05-22 | 2003-01-02 | Takehiko Hasebe | Electronic apparatus |
JP2005276950A (ja) * | 2004-03-23 | 2005-10-06 | Matsushita Electric Ind Co Ltd | 半導体チップの実装基板、半導体装置、半導体チップの実装基板の製造方法 |
CN1701437A (zh) * | 2002-11-21 | 2005-11-23 | 株式会社日立制作所 | 电子装置 |
JP2007158279A (ja) * | 2005-12-09 | 2007-06-21 | Hitachi Ltd | 半導体装置及びそれを用いた電子制御装置 |
JP2016076510A (ja) * | 2014-10-02 | 2016-05-12 | 太陽誘電株式会社 | 回路モジュール |
US20160338202A1 (en) * | 2015-05-11 | 2016-11-17 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
JP2017152692A (ja) * | 2016-02-22 | 2017-08-31 | 太陽誘電株式会社 | 回路基板及びその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3849573B2 (ja) * | 2001-05-22 | 2006-11-22 | 株式会社日立製作所 | 電子装置 |
JP2004163722A (ja) | 2002-11-14 | 2004-06-10 | Fujitsu Ltd | 部品内蔵基板 |
JP2005286057A (ja) * | 2004-03-29 | 2005-10-13 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
EP2026379B1 (en) * | 2006-06-02 | 2012-08-15 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and method for manufacturing same |
US7842541B1 (en) * | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
KR101752829B1 (ko) * | 2010-11-26 | 2017-06-30 | 삼성전자주식회사 | 반도체 장치 |
US10061967B2 (en) * | 2016-08-22 | 2018-08-28 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
JP6800125B2 (ja) * | 2017-09-29 | 2020-12-16 | 太陽誘電株式会社 | 回路基板及び回路モジュール |
US10504854B2 (en) * | 2017-12-07 | 2019-12-10 | Intel Corporation | Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same |
-
2018
- 2018-07-06 JP JP2018128928A patent/JP2020009879A/ja active Pending
-
2019
- 2019-07-03 CN CN201910593038.7A patent/CN110691457A/zh active Pending
- 2019-07-03 US US16/502,866 patent/US11069589B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002231862A (ja) * | 2001-02-05 | 2002-08-16 | Fujitsu Quantum Devices Ltd | 半導体装置及びチップキャリア |
US20030002260A1 (en) * | 2001-05-22 | 2003-01-02 | Takehiko Hasebe | Electronic apparatus |
CN1701437A (zh) * | 2002-11-21 | 2005-11-23 | 株式会社日立制作所 | 电子装置 |
JP2005276950A (ja) * | 2004-03-23 | 2005-10-06 | Matsushita Electric Ind Co Ltd | 半導体チップの実装基板、半導体装置、半導体チップの実装基板の製造方法 |
JP2007158279A (ja) * | 2005-12-09 | 2007-06-21 | Hitachi Ltd | 半導体装置及びそれを用いた電子制御装置 |
JP2016076510A (ja) * | 2014-10-02 | 2016-05-12 | 太陽誘電株式会社 | 回路モジュール |
US20160338202A1 (en) * | 2015-05-11 | 2016-11-17 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
JP2017152692A (ja) * | 2016-02-22 | 2017-08-31 | 太陽誘電株式会社 | 回路基板及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI795723B (zh) * | 2020-09-18 | 2023-03-11 | 欣興電子股份有限公司 | 電路板及其製作方法 |
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