CN110379857B - 一种包含p型氧化镓薄层的开关器件及其制备方法 - Google Patents

一种包含p型氧化镓薄层的开关器件及其制备方法 Download PDF

Info

Publication number
CN110379857B
CN110379857B CN201910588240.0A CN201910588240A CN110379857B CN 110379857 B CN110379857 B CN 110379857B CN 201910588240 A CN201910588240 A CN 201910588240A CN 110379857 B CN110379857 B CN 110379857B
Authority
CN
China
Prior art keywords
type gallium
gallium oxide
thin layer
oxide thin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910588240.0A
Other languages
English (en)
Other versions
CN110379857A (zh
Inventor
方志来
闫春辉
蒋卓汛
吴征远
田朋飞
张国旗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Naweilang Technology Shenzhen Co ltd
Original Assignee
Shenzhen Third Generation Semiconductor Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Third Generation Semiconductor Research Institute filed Critical Shenzhen Third Generation Semiconductor Research Institute
Priority to CN201910588240.0A priority Critical patent/CN110379857B/zh
Publication of CN110379857A publication Critical patent/CN110379857A/zh
Application granted granted Critical
Publication of CN110379857B publication Critical patent/CN110379857B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/18Metallic material, boron or silicon on other inorganic substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24Vacuum evaporation
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0245Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • C23C16/402Silicon dioxide
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

本发明公开了一种包含p型氧化镓薄层的开关器件及其制备方法,属于功率半导体器件及其制备方法领域,器件包括:衬底、n型氮化镓沟道层、位于所述n型氮化镓沟道层上或部分嵌入所述n型氮化镓沟道层内的p型氧化镓薄层,源电极、漏电极和栅电极,其中所述p型氧化镓薄层氮掺杂含量为1×1011~1×1018/cm3。通过化学气相沉积法在n型氮化镓沟道层上生长p型氧化镓薄膜,在p‑n结内电场和p型氧化镓空穴的作用下,使得n型氮化镓沟道层中的导电沟道有效关闭,实现对场效应晶体管开关特性的提升。本发明制备的包含p型氧化镓薄层的开关器件方法简单,p型氧化镓层的引入优化了器件的开关特性,降低了待机损耗。

Description

一种包含p型氧化镓薄层的开关器件及其制备方法
技术领域
本发明属于集成电路技术领域,特别涉及一种包含p型氧化镓薄层的开关器件及制备方法。
背景技术
基于硅材料的功率半导体器件经过多年发展,器件的性能已经趋近硅材料的理论极限,而随着高效完备的功率转换电路和系统需求的日益增加,具有低功耗和高速特性的功率器件成为了研究热点。目前功率半导体器件正进入以氮化镓为代表的第三代宽禁带半导体时代。由于氮化镓具有的禁带宽度(3.4eV)、高电子饱和速率
Figure 337986DEST_PATH_IMAGE001
、高击穿电场
Figure 527528DEST_PATH_IMAGE002
,较高热导率,耐腐蚀和抗辐射,在高压、高频、大功率条件下具有较强的优势,被认为是研究短波光电子器件和高压高频率大功率器件的理想材料。以氮化镓以及铝镓氮为基础材料的氮化镓场效应晶体管,在降低器件自身的电力损耗、提高开关频率和器件耐热性能等方面具有优异的表现,在大功率高频能量转换和高频微波通讯等方面有着广阔的应用前景。
基于n型氮化镓材料制作的常开型MOSFET,由于导电沟道为电子导电,在外部施加偏压对器件进行关断时,由于n型掺杂的缘故,导电沟道无法有效关闭,这使得关断时器件仍留有较大的电流,待机损耗也较大,这降低了氮化镓基常开器件的开关性能,影响了氮化镓基器件的应用。
发明内容
本发明旨在解决上述问题,提供了一种包含p型氧化镓薄层的开关器件,包括:
衬底;
位于所述衬底上的n型氮化镓沟道层和绝缘层;
位于所述n型氮化镓沟道层上或部分嵌入所述n型氮化镓沟道层内的p型氧化镓薄层;
位于n型氮化镓沟道层和p型氧化镓薄层上的绝缘层;
位于n型氮化镓沟道层上的漏电极和源电极;
位于绝缘介质层上或嵌入绝缘介质层内的栅电极;
所述p型氧化镓薄层氮掺杂含量为
Figure 769022DEST_PATH_IMAGE003
氮掺杂形成p型氧化镓薄层,由于p型氧化镓薄层的引入,一方面p型氧化镓薄层和n型氮化镓薄层间形成新的p-n结内部电场,这使得器件在关闭状态、栅极电压为负时,内部电场和外部电场方向相同,即可以在相同的栅极电压下,获得更窄的导电沟道,降低导电沟道内电流;另一方面,p型氧化镓薄层引入的空穴,可以俘获导电沟道中的电子,进一步减小导电沟道,使导电沟道内电流进一步降低,从而改善n型氮化镓常开器件的开关性能。
优选的,所述绝缘层端部设置有延伸至n型氮化镓沟道层表面或内部的源区和漏区,所述源区和漏区分别设置漏电极和源电极;所述漏电极和源电极与所述n型氮化镓沟道层欧姆接触。
优选的,所述p型氧化镓薄层为p型β-氧化镓薄层。
优选的,所述n型氮化镓沟道层厚度为1~4μm。
优选的,所述漏电极、源电极或栅电极厚度为10~200nm;所述漏电极、源电极或栅电极材料为金、银、铝、钛、铬、镍、铂及其合金任一种。
优选的,所述绝缘层厚度为10~200nm;所述绝缘层材料为二氧化硅、二氧化铪或三氧化二铝中的任一种。
一种包含p型氧化镓薄层的开关器件制备方法,其特征在于,包括:
通过化学气相沉积法,在未经刻蚀或部分刻蚀的n型氮化镓沟道层上,由上表面往下表面方向扩散生长氮掺杂含量为1×1011~1×1018/cm3的p型氧化镓薄层;
刻蚀p型氧化镓薄层,使其两端露出n型氮化镓沟道层上表面;
在露出的n型氮化镓沟道层上表面和p型氧化镓薄层上表面沉积绝缘层;
刻蚀绝缘层和部分n型氮化镓沟道层形成源区和漏区;
分别在源区、漏区和氧化镓绝缘层上表面生长源电极、漏电极和栅电极。
优选的,所述生长p型氧化镓薄层条件包括:
化学气相沉积设备腔体气压为
Figure 635085DEST_PATH_IMAGE004
,含氧量为
Figure 548814DEST_PATH_IMAGE005
,载气流速为0~500sccm,退火温度900~1200℃,退火时间为10~60min。
优选的,所述载气为任一种惰性气体。
优选的,所述刻蚀p型氧化镓薄层方式为等离子体刻蚀,所述等离子刻蚀气源选用SF6/Ar、NF3/Ar或Cl2/Ar。
优选的,所述沉积绝缘层方式为电镀、物理气相沉积、溅射、热蒸发、旋涂或原子层沉积。
优选的,所述刻蚀绝缘层和部分n型氮化镓沟道层方式为等离子体刻蚀、反应性等离子体刻蚀,所述等离子体刻蚀或反应性等离子体刻蚀的气源选用BCl3/Ar或CHF3/Ar。
优选的,所述生长漏电极、源电极和栅电极方式为采用热蒸发、电子束蒸镀或测控溅射。
本发明具有的有益效果:
(1)在p-n结内电场和p型氧化镓空穴的作用下,n型氮化镓沟道层中的导电沟道有效关闭,实现对场效应晶体管开关特性的提升;
(2)降低器件的待机损耗;
(3)在不改变氮化镓基器件原有设计的情况下,可通过生长一层p型氧化镓薄膜来提升器件的电学性能;
(4)p型氧化镓薄膜通过化学气相沉积法制备,工艺简单,重复率高,可推广至其它基于III族氮化物的器件。
附图说明
图1为本发明实例1和2中生长n型氮化镓沟道层的示意图;
图2为本发明实例1中生长p型氧化镓薄层的示意图;
图3为本发明实例1中刻蚀p型氧化镓层的示意图;
图4为本发明实例1中沉积绝缘层的示意图;
图5为本发明实例1中刻蚀绝缘层的示意图;
图6为本发明实例1提供的包含p型氧化镓薄层的开关器件示意图;
图7为本发明实例2中刻蚀n型氮化镓沟道层的示意图;
图8为本发明实例2中生长p型氧化镓薄层的示意图;
图9为本发明实例2中刻蚀p型氧化镓薄层的示意图;
图10为本发明实例2中沉积绝缘层的示意图;
图11为本发明实例2中刻蚀绝缘层的示意图;
图12为本发明实例2提供的包含p型氧化镓薄层的开关器件示意图;
图13为本发明实施例1提供的n型氮化镓沟道层和p型氮掺杂氧化镓薄层二次离子质谱图;
衬底1,n型氮化镓沟道层2,p型氧化镓薄层3,绝缘层4,源电极 5,漏电极6,栅电极7。
具体实施方式
下文结合特定实例说明的实施方式,此处的实施例及各种特征和有关细节将参考附图中图示以及以下描述中详述的非限制性实施例而进行更完整的解释。省略众所周知的部件和处理技术的描述,以免不必要的使此处的实施例难以理解。在制作所述结构时,可以使用半导体工艺中众所周知的传统工艺。此处使用的示例仅仅是为了帮助理解此处的实施例可以被实施的方式,以及进一步使得本领域技术人员能够实施此处的实施例。因而,不应将此处的示例理解为限制此处的实施例的范围。
需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
实施例1
本实施例提供一种包含p型氧化镓薄层的开关器件及其制备方法,开关器件包括:蓝宝石衬底;位于所述衬底上的n型氮化镓沟道层和绝缘层;位于所述n型氮化镓沟道层上的p型氧化镓薄层;位于n型氮化镓沟道层和p型氧化镓薄层上的绝缘层;位于n型氮化镓沟道层上的漏电极和源电极;位于绝缘介质层上或嵌入绝缘介质层内的栅电极;所述p型氧化镓薄层氮掺杂含量为1×109/cm3。所述绝缘层端部设置有延伸至n型氮化镓沟道层表面或内部的源区和漏区,所述源区和漏区分别设置漏电极和源电极;所述漏电极和源电极与所述n型氮化镓沟道层欧姆接触,如图6所示为包含p型氧化镓薄层的开关器件示意图。如图13所示,为n型氮化镓沟道层和p型氮掺杂氧化镓薄层二次离子质谱图,从元素的三维分布中可以看到,制备的氧化镓薄膜中有明显掺杂的氮元素。
在一些优选的实施例中,所述p型氧化镓薄层氮掺杂含量为1×1011/cm3,在一些更优选的实施例中,所述p型氧化镓薄层氮掺杂含量为1×1013/cm3,。
在一些优选的实施例中,所述p型氧化镓薄层为p型β-氧化镓薄层。
在一些优选的实施例中,所述n型氮化镓沟道层厚度为1~4μm。
在一些优选的实施例中,所述漏电极、源电极或栅电极厚度为10~200nm;所述漏电极、源电极或栅电极材料为金、银、铝、钛、铬、镍、铂及其合金任一种。
在一些优选的实施例中,所述绝缘层厚度为10~200nm;所述绝缘层材料为二氧化硅、二氧化铪或三氧化二铝中的任一种。
一种包含p型氧化镓薄层的开关器件制备方法包括:
(1)在蓝宝石衬底上生长一层n型氮化镓沟道层,厚度1~μm,图1为生长的氮化镓沟道层示意图。
(2)在未刻蚀的n型氮化镓沟道层上生长p型氧化镓薄层,具体包括:
将n型氮化镓沟道层放置于化学气相沉积设备中,维持设备腔体中的气压在
Figure 869943DEST_PATH_IMAGE006
,含氧量在
Figure 44572DEST_PATH_IMAGE007
,并以200sccm的流速持续通入氩气。快速退火,退火温度为1000℃,退火时间为30min,自远离衬底的氮化镓表面向靠近衬底的氮化镓表面扩散生长厚度为50~100nm氮掺杂的p型氧化镓薄层,氮掺杂含量为
Figure 910897DEST_PATH_IMAGE008
,图2为生长的p型氧化镓薄层示意图。
(3)刻蚀去除部分p型氧化镓薄层:
使用ICP法,rf=150W,chamberpressure=20mTorr,gasflow=SF6/Ar(15sccm/15sccm),etchingtime=5minutes,将两端部分的p型氧化镓薄层去除,刻蚀深度150nm,露出n型氮化镓沟道层上表面,图3为刻蚀的示意图。
(4)沉积SiO2绝缘层:
使用ALD设备在露出的n型氮化镓沟道层上表面和p型氧化镓薄层上表面沉积绝缘层绝缘材料为SiO2,沉积厚度为50nm,图4为沉积绝缘层的示意图。
(5)刻蚀绝缘层,形成源漏区:
使用RIE法,power=100W,chamberpressure=5mTorr,gasflow=CHF3(15sccm),etchingtime=4minutes,将两端部分的绝缘层去除,刻蚀深度100nm,至n型氮化镓沟道层内50nm,形成源区和漏区,图5为刻蚀的示意图。
(6)生长源电极、漏电极和栅电极:
在p型氧化镓薄层上方的SiO2绝缘层上,漏区和源区内,使用热蒸发法,先生长20nm钛金属,再生长50nm金金属,形成源电极、漏电极和栅电极,图6为生长源电极、漏电极和栅电极后形成的包含p型氧化镓薄层的开关器件示意图。
实例1,通过化学气相沉积法在n型氮化镓表面嵌入式生长p型氧化镓沟道层,使得在氧化镓与氮化镓构成的p-n结内电场和p型氧化镓空穴的作用下,n型氮化镓层中的导电沟道有效关闭,实现n型氮化镓场效应晶体管开关特性的提升。
实施例2:
本实施例提供一种包含p型氧化镓薄层的开关器件,包括:
(1)在蓝宝石衬底上生长n型氮化镓沟道层,厚度1~4μm,如图2所示。
(2)刻蚀去除部分n型氮化镓沟道层:
使用ICP法,rf=150W,chamberpressure=20mTorr,gasflow=BCl3/Ar(30sccm/15sccm),etchingtime=3minutes,刻蚀深度500nm,图7为刻蚀氮化镓沟道层的示意图。
(3)在刻蚀后的n型氮化镓沟道层上生长p型氧化镓薄层,具体包括:
将刻蚀后的n型氮化镓沟道层放置于化学气相沉积设备中,维持设备腔体中的气压在
Figure 187289DEST_PATH_IMAGE009
,含氧量在
Figure 797261DEST_PATH_IMAGE010
,并以100sccm的流速持续通入氩气。快速退火,退火温度为1000℃,退火时间为60min,自远离衬底的氮化镓表面向靠近衬底的氮化镓表面嵌入生长厚度为100~250nm的氮掺杂p型氧化镓薄层,氮掺杂含量为
Figure 826397DEST_PATH_IMAGE011
,图8为生长的氧化镓薄层示意图。
(4)刻蚀去除p型氧化镓薄层:
使用ICP法,rf=150W,chamberpressure=20mTorr,gasflow=SF6/Ar(15sccm/15sccm),etchingtime=10minutes,刻蚀深度300nm,将两端部分的p型氧化镓薄层去除,图9为刻蚀的示意图。
(5)沉积SiO2绝缘层:
使用ALD设备在露出的n型氮化镓沟道层上表面和p型氧化镓薄层上表面沉积绝缘层,绝缘材料为SiO2,沉积厚度为50nm,图10为沉积绝缘层的示意图。
(6)刻蚀绝缘层,形成源漏区:
使用RIE法,power=100W,chamberpressure=5mTorr,gasflow=CHF3(15sccm),etchingtime=4minutes,刻蚀深度100nm,将两端部分的绝缘层去除,形成源区和漏区,图11为刻蚀的示意图。
(7)生长源电极、漏电极和栅电极:
在p型氧化镓薄层上方的SiO2绝缘层上、漏区和源区内,使用热蒸发法,先生长20nm钛金属,再生长50nm金金属,形成源电极、漏电极和栅电极,图12为生长源电极、漏电极和栅电极后形成的包含p型氧化镓薄层的开关器件示意图。
实例2在实例1的基础上,提前对n型氮化镓沟道层进行刻蚀,使得p型氧化镓所在的栅极下沉,对氮化镓导电沟道的影响更加直接,器件关断更加容易。
以上内容是结合优选技术方案对本发明所做的进一步说明,所描述的实例是本发明的一部分实例,而不是全部实例。对于本发明所属技术领域的研究人员来说,在不脱离构思的前提下还可以做出简单推演和替换,在没有做出创造性劳动前提下所获得的其他实例,都属于本发明保护的范围。

Claims (11)

1.一种包含p型氧化镓薄层的开关器件制备方法,其特征在于,包括:
通过化学气相沉积法,在n型氮化镓沟道层上,在远离衬底的n型氮化镓表面向靠近衬底的所述n型氮化镓表面扩散生长氮掺杂含量为1×1011~1×1018/cm3的p型氧化镓薄层;
刻蚀p型氧化镓薄层,使其两端露出n型氮化镓沟道层上表面;
在露出的n型氮化镓沟道层上表面和p型氧化镓薄层上表面沉积绝缘层;
刻蚀绝缘层和部分n型氮化镓沟道层形成源区和漏区;
分别在源区、漏区和绝缘层上表面生长源电极、漏电极和栅电极。
2.一种权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述生长p型氧化镓薄层条件包括:
化学气相沉积设备腔体气压为1.01×104 ~1.01×105 Pa,含氧量为1×10-16 ~ 1×10-5mol/L,载气流速为0~500sccm,退火温度900~1200℃,退火时间为10~60min。
3.一种如权利要求2所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述载气为任一种惰性气体。
4.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述刻蚀p型氧化镓薄层采用等离子体刻蚀,所述等离子刻蚀气源选用SF6和Ar的混合气体、NF3和Ar的混合气体或Cl2和Ar的混合气体。
5.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述沉积绝缘层方式为电镀、物理气相沉积、溅射、热蒸发、旋涂或原子层沉积。
6.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述刻蚀绝缘层和部分n型氮化镓沟道层方式为等离子体刻蚀或反应性等离子体刻蚀,所述等离子体刻蚀或反应性等离子体刻蚀的气源选用BCl3和Ar的混合气体或CHF3和Ar的混合气体。
7.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述生长漏电极、源电极和栅电极方式为采用热蒸发、电子束蒸镀或测控溅射。
8.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述p型氧化镓薄层为p型β-氧化镓薄层。
9.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述n型氮化镓沟道层厚度为1~4μm。
10.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述漏电极、源电极或栅电极厚度为10~200nm;所述漏电极、源电极或栅电极材料为金、银、铝、钛、铬、镍、铂及其合金任一种。
11.一种如权利要求1所述的包含p型氧化镓薄层的开关器件制备方法,其特征在于,所述绝缘层厚度为10~200nm;所述绝缘层材料为二氧化硅、二氧化铪或三氧化二铝中的任一种。
CN201910588240.0A 2019-07-02 2019-07-02 一种包含p型氧化镓薄层的开关器件及其制备方法 Active CN110379857B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910588240.0A CN110379857B (zh) 2019-07-02 2019-07-02 一种包含p型氧化镓薄层的开关器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910588240.0A CN110379857B (zh) 2019-07-02 2019-07-02 一种包含p型氧化镓薄层的开关器件及其制备方法

Publications (2)

Publication Number Publication Date
CN110379857A CN110379857A (zh) 2019-10-25
CN110379857B true CN110379857B (zh) 2022-01-25

Family

ID=68251576

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910588240.0A Active CN110379857B (zh) 2019-07-02 2019-07-02 一种包含p型氧化镓薄层的开关器件及其制备方法

Country Status (1)

Country Link
CN (1) CN110379857B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341839B (zh) * 2020-01-19 2022-01-25 深圳第三代半导体研究院 一种p型氮掺杂氧化镓薄膜及其制备方法
CN111415979A (zh) * 2020-02-28 2020-07-14 深圳第三代半导体研究院 一种垂直异质p-n结结构器件及其制备方法
CN111415977B (zh) * 2020-02-28 2022-02-15 深圳第三代半导体研究院 一种氮化水平异质p-n结结构器件及其制备方法
CN111415978B (zh) * 2020-02-28 2022-02-15 深圳第三代半导体研究院 一种氧化水平异质p-n结结构器件及其制备方法
CN112164724A (zh) * 2020-10-07 2021-01-01 西安电子科技大学 一种pn结栅控氧化镓场效应晶体管及制备方法
CN112652539B (zh) * 2020-12-29 2022-06-10 光华临港工程应用技术研发(上海)有限公司 用于氧化镓材料的微波退火改性方法
CN112951917B (zh) * 2021-01-29 2022-11-15 中国电子科技集团公司第十三研究所 一种氧化镓场效应晶体管及制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550089A (en) * 1994-03-23 1996-08-27 Lucent Technologies Inc. Gallium oxide coatings for optoelectronic devices using electron beam evaporation of a high purity single crystal Gd3 Ga5 O12 source.
CN103469173B (zh) * 2013-09-12 2015-10-28 大连理工大学 空穴导电特性氧化镓膜的制备方法及空穴导电特性氧化镓膜
CN104269433B (zh) * 2014-09-05 2017-03-22 电子科技大学 具有复合沟道层的氮化镓基增强型异质结场效应晶体管
CN107331607B (zh) * 2017-06-27 2020-06-26 中国科学院微电子研究所 一种氧化镓基底场效应晶体管及其制备方法
CN109037326B (zh) * 2018-07-18 2021-09-14 大连理工大学 一种具有p型埋层结构的增强型hemt器件及其制备方法

Also Published As

Publication number Publication date
CN110379857A (zh) 2019-10-25

Similar Documents

Publication Publication Date Title
CN110379857B (zh) 一种包含p型氧化镓薄层的开关器件及其制备方法
CN100557815C (zh) InA1N/GaN异质结增强型高电子迁移率晶体管结构及制作方法
CN102938413B (zh) AlGaN/GaN异质结增强型器件及其制作方法
CN108155099A (zh) 一种包含介质层的p型栅HEMT器件及其制作方法
CN110120425B (zh) 垂直型的高压mosfet器件及制作方法
CN109004029A (zh) 具有金属氧化物/二氧化硅叠栅的GaN基MOS-HEMT器件及其制备方法
CN106549038A (zh) 一种垂直结构的氮化镓异质结hemt
WO2019119959A1 (zh) SiC肖特基二极管的制备方法及其结构
CN107369720A (zh) 一种p型金刚石高低势垒肖特基二极管及其制备方法
CN106876256A (zh) SiC双槽UMOSFET器件及其制备方法
CN110164976B (zh) 应变型氧化镓mosfet器件结构及制备方法
CN109950323A (zh) 极化超结的ⅲ族氮化物二极管器件及其制作方法
CN111785776B (zh) 垂直结构Ga2O3金属氧化物半导体场效应晶体管的制备方法
CN111682064B (zh) 高性能MIS栅增强型GaN基高电子迁移率晶体管及其制备方法
CN208368513U (zh) 基于金属氧化物/二氧化硅叠栅的GaN基MOS-HEMT器件
CN116387361A (zh) SiO2阻挡层Ga2O3垂直UMOS晶体管及其制备方法
CN115376919A (zh) 一种增强型GaN功率器件及其制备方法
CN114899227A (zh) 一种增强型氮化镓基晶体管及其制备方法
CN115312605A (zh) 改善终端边缘峰值电场的氧化镓肖特基二极管及制备方法
CN112736130A (zh) 氮化镓基高电子迁移率晶体管及其制作方法
CN103681831A (zh) 高电子迁移率晶体管及其制造方法
CN112186031A (zh) 一种等离子体的处理方法及其应用
CN114220869B (zh) 一种具有沟槽结构的垂直型氮化镓肖特基二极管及其制备方法
CN116581159B (zh) 垂直型功率器件及其制备方法
CN110556415B (zh) 一种高可靠性外延栅的SiC MOSFET器件及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20230328

Address after: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province

Patentee after: SOUTH University OF SCIENCE AND TECHNOLOGY OF CHINA

Address before: Taizhou building, 1088 Xueyuan Avenue, Xili University Town, Nanshan District, Shenzhen, Guangdong 518051

Patentee before: SHENZHEN THIRD GENERATION SEMICONDUCTOR Research Institute

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20230711

Address after: Building 1, Building 409, No. 1310 Kukeng Sightseeing Road, Kukeng Community, Guanlan Street, Longhua District, Shenzhen City, Guangdong Province, 518109

Patentee after: Naweilang Technology (Shenzhen) Co.,Ltd.

Address before: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province

Patentee before: SOUTH University OF SCIENCE AND TECHNOLOGY OF CHINA