CN110189999B - 半导体封装衬底及其制造方法、半导体封装及其制造方法 - Google Patents
半导体封装衬底及其制造方法、半导体封装及其制造方法 Download PDFInfo
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Abstract
本发明提供一种制造半导体封装衬底的方法、一种使用制造半导体封装衬底的方法来制造的半导体封装衬底、一种制造半导体封装的方法以及一种使用制造半导体封装的方法来制造的半导体封装。制造半导体封装衬底的方法包含:在具有顶部表面和底部表面且由导电材料形成的基底衬底的底部表面中形成多个第一凹槽或第一沟槽;用树脂填充多个第一凹槽或沟槽;固化树脂;去除过度填充于多个第一凹槽或沟槽中的树脂的暴露部分;对基底衬底的顶部表面进行蚀刻以暴露填充于多个第一凹槽或沟槽中的树脂的至少部分;以及在基底衬底的底部表面中形成第二凹槽或第二沟槽。
Description
技术领域
一或多个实施例涉及一种制造以简易方式对其执行焊接的半导体封装衬底的方法和使用所述方法制造的半导体封装衬底,以及一种制造半导体封装的方法和使用所述方法制造的半导体封装。
背景技术
半导体装置通过将其封装在半导体封装衬底上来使用。为了封装半导体装置,半导体封装衬底包含精细电路图案和/或输入/输出(input/output;I/O)端子。随着半导体装置的性能和/或整合度的改进,且使用这类半导体装置来制造的电子装置具有减小的体积和改进的性能,半导体封装衬底的精细电路图案等的关键尺寸(critical dimension)已变得更小且其复杂度已变得更高。
现有半导体封装衬底通过以下操作来制造:通过使用其上堆叠有铜箔的覆铜层压板(copper clad laminate;CCL)来形成通孔,用金属镀敷通孔的内部以电连接堆叠在CCL的顶部表面和底部表面上的铜箔,以及通过使用光刻胶来图案化上部表面铜箔和下部表面铜箔。然而,就高工艺复杂度和低精度来说,制造现有半导体封装衬底的方法是不利的。
因而最近,已引入一种通过用绝缘材料填充导电基底衬底以简化制造工艺来制造半导体封装衬底的方法。
发明内容
一或多个实施例是针对一种制造以简易方式对其执行焊接的半导体封装衬底的方法和使用所述方法制造的半导体封装衬底,以及一种制造半导体封装的方法和使用所述方法制造的半导体封装。然而,这些方面仅仅是实例,且因而本公开的范围不应理解为受其限制。
额外方面将部分地在以下描述中予以阐述,且部分地将从描述中显而易见,或可通过对所提出的实施例的实践而获悉。
根据一或多个实施例,一种制造半导体封装衬底的方法包含:在基底衬底的底部表面中形成多个第一凹槽或多个第一沟槽,所述基底衬底具有顶部表面和底部表面且由导电材料形成;用树脂填充多个第一凹槽或沟槽;固化树脂;去除过度填充于多个第一凹槽或沟槽中的树脂的暴露部分;对基底衬底的顶部表面进行蚀刻以暴露填充于多个第一凹槽或沟槽中的树脂的至少部分;以及在基底衬底的底部表面中形成第二凹槽或第二沟槽。
在一个实施例中,对基底衬底的顶部表面的蚀刻与第二凹槽或沟槽的形成可同时执行。
在一个实施例中,第二凹槽或沟槽的形成可包含沿切割线形成第二凹槽或沟槽。
在一个实施例中,第二凹槽或沟槽的形成可包含在用树脂填充的相邻的多个第一凹槽或沟槽之间形成第二凹槽或沟槽。
在一个实施例中,在用树脂对多个第一凹槽或沟槽的填充之前,方法可进一步包含使多个第一凹槽或沟槽的内部表面粗糙化。
在一个实施例中,经由多个第一凹槽或沟槽暴露于基底衬底的底部表面上的树脂的面积可大于经由第二凹槽或沟槽暴露于基底衬底的顶部表面上的树脂的面积。
在一个实施例中,方法可进一步包含在基底衬底上形成镀层。
在一个实施例中,镀层的形成可包含在第二凹槽或沟槽的内部表面上形成镀层。
根据一或多个实施例,提供一种通过上文所描述的方法来制造的半导体封装衬底。
根据一或多个实施例,一种制造半导体封装的方法包含:在基底衬底的底部表面中形成多个第一凹槽或多个第一沟槽,所述基底衬底具有顶部表面和底部表面且由导电材料形成;用树脂填充多个第一凹槽或沟槽;固化树脂;去除过度填充于多个第一凹槽或沟槽中的树脂的暴露部分;对基底衬底的顶部表面进行蚀刻以暴露填充于多个第一凹槽或沟槽中的树脂的至少部分;在基底衬底的底部表面中形成第二凹槽或第二沟槽;在基底衬底上安装半导体芯片;以及沿第二凹槽或沟槽切割基底衬底。
在一个实施例中,对基底衬底的顶部表面的蚀刻与第二凹槽或沟槽的形成可同时执行。
在一个实施例中,第二凹槽或沟槽的形成可包含在用树脂填充的相邻的多个第一凹槽或沟槽之间形成第二凹槽或沟槽。
在一个实施例中,在基底衬底的切割中,用于切割基底衬底的切割线的宽度可小于第二凹槽或沟槽的宽度。
在一个实施例中,方法可进一步包含在基底衬底上形成镀层。
根据一或多个实施例,提供一种通过上文所描述的方法来制造的半导体封装。
这些和其它方面、特征以及效应将从随附图式、权利要求书以及以下描述中显而易见。
如本文中所阐述的一般方面和特殊方面可使用系统、方法、计算机程序或其组合来实施。
附图说明
根据结合随附图式对实施例进行的以下描述,这些和/或其它方面将变得显而易见且更容易了解,在随附图式中:
图1到图6是说明根据一实施例的制造半导体封装衬底的工艺的示意性横截面视图。
图7和图8是说明根据另一实施例的制造半导体封装的工艺的部分的示意性横截面视图。
图9是说明根据另一实施例的半导体封装的结构的示意性横截面视图。
附图标号说明
10:半导体封装衬底;
20:半导体封装;
100:基底衬底;
100a:底部表面;
100b:顶部表面;
100c:第一凹槽或沟槽;
100d:部分;
100e:第二凹槽或沟槽;
102、104:互连图案;
110:树脂;
120:镀层;
130:半导体芯片;
140:导线;
150:模制层;
CA:切割区域;
We、Wc:宽度;
WF:可润湿侧翼结构;
x、y、z:轴线。
具体实施方式
可在本公开中做出各种修改且可实施各种实施例。因此,实例实施例在图式中加以说明且在本文中进行详细描述。本公开的有利特征以及实现所述特征的方法将从待结合图式在下文详细描述的实施例中显而易见。然而,本公开不限于此且可以许多不同形式实施。如本文中所使用,术语“和/或”包含相关联的所列项目中的一或多个的任何组合以及所有组合。当“…中的至少一个”的表述伴随着一列元件时,其修饰一列元件的所有元件而不是修饰一列元件中的单个元件。
在下文中,将参考随附图式详细地描述实施例。在参考图式描述实施例时,为相同或相应组件分配相同的附图标记,且在本文中不进行过多描述。
在以下实施例中,术语“第一”、“第二”等并不用以限定本公开的范围,且仅用以区分一个组件与另一组件。如本文中所使用,除非上下文另外明确地指示,否则单数形式“一(a/an)”和“所述”还意图包含复数形式。
应理解,当在本文中使用时,术语“包括(comprises)”和/或“包括(comprising)”指明所陈述特征或组件的存在,但不排除一或多个其它特征或组件的存在或添加。应理解,当如层、区域或组件的元件被称作在另一元件“上”或“上方”时,所述元件可直接在另一元件上或另一元件可插入于其间。
在图式中,为解释方便起见,可放大组件的大小。举例来说,为解释方便起见而任意地说明图式中所说明的每一组件的大小和厚度,且因此实施例不应理解为限于此。
如本文中所使用,x轴、y轴以及z轴不限于正交坐标系的三条轴线且可广泛地理解为任何三条轴线。举例来说,x轴、y轴以及z轴可彼此垂直但可指示非正交的不同方向。
当可以不同方式来实施一实施例时,可以不同于此处所描述的次序来执行某一工艺。举例来说,连续描述的两个工艺可基本上同时执行或以与本文中所描述次序相反的次序执行。
图1到图6是说明根据一实施例的制造半导体封装衬底的工艺的示意性横截面视图。
在根据本发明实施例的制造半导体封装衬底10的方法中,首先,如图1中所说明来制备由导电材料形成的基底衬底100。基底衬底100可呈包含导电材料的平板形式。导电材料的实例可包含铁(iron;Fe);Fe合金(如Fe-Ni或Fe-Ni-Co);铜(copper;Cu);Cu合金(如Cu-Sn、Cu-Zr、Cu-Fe或Cu-Zn)等。基底衬底100可为包含顶部表面100b和底部表面100a的板形状,所述顶部表面与底部表面是相对表面。
其后,如图2中所说明,第一凹槽或沟槽100c在基底衬底100的底部表面100a中形成。此处,第一凹槽或沟槽100c可理解为不完全穿透基底衬底100。虽然在作为横截面视图的图2中未绘示,但在从平面视图观察时,除了形成于底部表面100a中的第一凹槽或沟槽100c以外的基底衬底100的剩余部分可理解为在一个方向上延伸的互连图案或卷绕互连图案。
为了形成第一凹槽或沟槽100c,使基底衬底100的底部表面100a与感光性干膜抗蚀剂(dry film resist;DFR)层压,且随后暴光并显影以仅暴露其中待形成第一凹槽或沟槽100c的基底衬底100仅部分。随后,用如氯化铜或氯化铁的蚀刻溶液对未由DFR覆盖的基底衬底100的底部表面100a的部分进行蚀刻,从而在底部表面100a中形成并不穿透基底衬底100的第一凹槽或沟槽100c,如图2中所示出。
基底衬底100的底部表面100a的剩余部分(即其除了第一凹槽或沟槽100c以外的部分)稍后可充当互连图案。因此,当在基底衬底100的底部表面100a中形成第一凹槽或沟槽100c时,相邻第一凹槽或沟槽100c之间的间隙的宽度可等于一般互连图案的宽度,即约20微米到30微米。
当第一凹槽或沟槽100在如图2中所说明的基底衬底100的底部表面100a中形成时,第一凹槽或沟槽100c的深度可为基底衬底100的厚度的约80%到90%。举例来说,形成第一凹槽或沟槽100c的基底衬底100的剩余部分的厚度可在约10微米到约40微米的范围内。
当第一凹槽或沟槽100c的深度大于基底衬底100的厚度的约80%到90%时,基底衬底100或半导体封装衬底10在半导体封装衬底制造工艺或稍后的封装工艺中可能不易于操控。在一些情况下,当第一凹槽或沟槽100c的深度大于基底衬底100的厚度的约80%到90%时,可由于在形成第一凹槽或沟槽100c期间的公差而形成穿透基底衬底100的底部表面100a和顶部表面100b的通孔。当第一凹槽或沟槽100c的深度小于基底衬底100的厚度的约80%到90%时,后续工艺在稍后制造半导体封装衬底时可能不易于执行,或最终所制造的半导体衬底可能过薄。
其后,如图3中所示,用树脂110填充基底衬底100的第一凹槽或沟槽100c。树脂110可以是具有非电学特性的任何类型的绝缘材料。举例来说,树脂110可以是在加热时聚合并固化的热固性树脂。树脂110在半导体封装衬底10的互连图案之间电绝缘。在树脂110的填充中,可使用呈液态的树脂110或含有树脂110的固体型胶带。
在树脂110的填充中,不仅仅是基底衬底100的第一凹槽或沟槽100c,而且基底衬底100的底部表面100a的至少部分也可被树脂110填充,如图3中所示出。当如上文所描述过度填充树脂110时,可利用机械切削(如刷擦、研磨或抛光)或化学切削(如蚀刻)来去除过度填充的树脂110以致树脂110仅填充基底衬底100的第一凹槽或沟槽100c的内部,如图4中所示出。
可替代地,基底衬底100的仅第一凹槽或沟槽100c可如图4中所示来填充树脂110而不是如图3中所示的过度填充树脂110。然而,在这种情况下,基底衬底100的第一凹槽或沟槽100c可能不被树脂110适当地填充。
随后,对基底衬底100的顶部表面100b进行蚀刻以形成暴露填充于第一凹槽或沟槽100c中的树脂110的部分100d,如图5中所示出。可以不同方式对基底衬底100的顶部表面100b进行蚀刻。举例来说,基底衬底100的顶部表面100b可以感光性DFR一起层压,且随后暴露并显影以暴露仅待蚀刻的基底衬底100的顶部表面100b的部分。其后,可使用如氯化铜或氯化铁的蚀刻溶液对未由DFR覆盖的基底衬底100的顶部表面100b的部分进行蚀刻,从而暴露在如图5中所示出的基底衬底100的顶部表面100b上的树脂110的一部分。
通过以上工艺,如图5中所示出,获得在用树脂110填充的基底衬底100的底部表面100a的部分之间的互连图案102和用树脂110填充的基底衬底100的顶部表面100b的部分之间的互连图案104。在半导体封装衬底10中,顶部表面100b的互连图案104与底部表面100a的互连图案102电连接,且因此需要对顶部表面100b和底部表面100a执行如先前所设定的导电层图案化。
同时,第二凹槽或沟槽100e在基底衬底100的底部表面100a中形成。类似于第一凹槽或沟槽100c,第二凹槽或沟槽100e可形成为不完全穿透基底衬底100。第二凹槽或沟槽100e可形成为与切割区域CA相对应。举例来说,第二凹槽或沟槽100e可在一个方向(Y轴方向)上和垂直于所述方向的另一方向(X轴方向)上形成。将参考以下图8详细地描述切割区域CA以及切割基底衬底100。
第二凹槽或沟槽100e可在未形成第一凹槽或沟槽100c的基底衬底100的底部表面100a的部分中形成(即在相邻的第一凹槽或沟槽100c之间)。在制造期间,第二凹槽或沟槽100e在用树脂110填充第一凹槽或沟槽100c之后形成,且因此可理解为在用树脂110填充的第一凹槽或沟槽100c之间形成。第二凹槽或沟槽100e可用作促进稍后焊接半导体封装的可润湿侧翼结构。
第二凹槽或沟槽100e可形成为与切割区域CA相对应。在这种情况下,第二凹槽或沟槽100e的宽度We大于切割区域CA的宽度Wc。当第二凹槽或沟槽100e的宽度We小于切割区域CA的宽度Wc时,第二凹槽或沟槽100e在切割半导体封装衬底10之后不能用作可润湿侧翼结构,且因此将第二凹槽或沟槽100e的宽度We设定成大于切割区域CA的宽度Wc至关重要。
在本实施例中,第二凹槽或沟槽100e在基底衬底100的底部表面100a中形成,同时伴以对基底衬底100的顶部表面100b的蚀刻。即,可同时对基底衬底100的顶部表面100b和底部表面100a进行蚀刻。因此,第二凹槽或沟槽100e可在不执行额外工艺的情况下于基底衬底100的底部表面100a中形成,与对基底衬底100的顶部表面100b的部分的蚀刻同时进行。第二凹槽或沟槽100e在用树脂110填充基底衬底100之后形成。其中形成有第二凹槽或沟槽100e的区域由所填充的树脂110锁住,且因而可形成具有所需宽度和深度的第二凹槽或沟槽100e。
随后,如图6中所说明,镀层120可在基底衬底100的剩余部分中的至少一些上形成。镀层120可在第二凹槽或沟槽100e的内部表面上形成,且可在基底衬底100的顶部表面100b和底部表面100a上以及在一些情况下除了树脂110以外的第一凹槽或沟槽100c的内部表面上形成。具体地说,形成于第二凹槽或沟槽100e的内部表面上的镀层120可改进半导体封装衬底10的焊料可润湿性。镀层120可用例如AU、Pd、NiPdAu合金或类似物来电镀。可在基底衬底100的顶部表面100b上涂布如有机可焊性保护层(organic solderabilitypreservative;OSP)的有机膜或可对所述顶部表面执行抗锈蚀。
在根据上述实施例的半导体封装衬底制造方法中,在用树脂110填充基底衬底100的第一凹槽或沟槽100c之前,可使第一凹槽或沟槽100c的内部粗糙化。因此,可显著增加树脂110与基底衬底100之间的粘合性。可通过等离子体处理、紫外线处理或过氧化氢/硫酸基溶液来使基底衬底100的第一凹槽或沟槽100c的内部粗糙化。在这种情况下,基底衬底100的第一凹槽或沟槽100c的内部可具有150纳米或大于150纳米的粗糙度。
如上文所描述,可形成第二凹槽或沟槽100e以便于在半导体封装衬底10的制造期间焊接半导体封装。在一比较例中,可通过仅焊接其直角拐点或在待于半导体芯片封装之后利用单独工艺来在焊接的部分处形成沟槽来焊接半导体封装衬底。然而,当仅焊接直角拐点时,可能显著降低焊料可润湿性,且可能在沟槽的形成期间出现金属毛刺,进而降低半导体封装的性能。
因此,在制造根据一实施例的半导体封装衬底的方法中,可通过以下操作而有效形成可润湿侧翼结构:在半导体封装衬底的制造期间(即在引线框架的制造期间)的半导体芯片封装之后,在不执行额外工艺的情况下形成与切割区域CA相对应的第二凹槽或沟槽100e。
虽然已在上文描述了制造半导体封装衬底的方法,但本公开不限于此。举例来说,使用制造半导体封装衬底的方法所制造的半导体封装衬底以及使用半导体封装衬底制造半导体封装的方法可理解为属于本公开的范围内。
图7和图8是说明根据另一实施例的制造半导体封装20的工艺的部分的示意性横截面视图。图9是说明根据另一实施例的半导体封装20的结构的示意性横截面视图。
参考图1到图6以及图7,半导体芯片130安装在通过上文参考图1到图6所描述的工艺来制造的半导体封装衬底10上。半导体芯片130可安装在半导体封装衬底的顶部表面100b的平面部分上,且经由导线140以电气方式和物理方式连接到基底衬底100上的引线。导线140可通过导线接合来耦合到半导体芯片130和引线。导线140的一侧附接到引线且其另一侧耦合到半导体芯片130。
可在半导体封装衬底10上的半导体芯片130上形成模制层150。模制层150可配置成从外部密封半导体芯片130,且以例如单层模制结构、双层模制结构或具有三层或大于三层的模制结构来形成。模制层150可由固化树脂110形成,且包含例如萤光物质和光扩散剂中的至少一种。在一些情况下,可以使用不含有萤光物质和光扩散剂的透明材料。
在半导体芯片130安装在半导体封装衬底10上之后,如图8中所示出来切割基底衬底100。对基底衬底100的切割可理解为对用树脂110填充的半导体封装衬底10进行切割。如图8中所说明,可沿着沿第二凹槽或沟槽100e所形成的切割区域CA来切割基底衬底100。如上文参考图5所描述,第二凹槽或沟槽100e的宽度We可大于切割区域CA的宽度Wc。因此,在切割基底衬底100时,半导体封装衬底10具有可润湿侧翼结构WF,即下端的拐角的凹陷,如图9中所示。可由于可润湿侧翼结构WF而改进半导体封装衬底10的焊料可润湿性。
已在上文描述了制造半导体封装的方法,但本公开不限于此。举例来说,通过制造半导体封装的方法所制造的半导体封装属于本公开的范围内。
在现有技术中,可通过仅焊接其直角拐点或在待于半导体芯片封装之后利用单独工艺来焊接的部分处形成沟槽来焊接半导体封装衬底。然而,当焊接直角拐点时,可能大大降低焊料可润湿性,且在通过单独工艺形成沟槽的期间出现金属毛刺,进而降低半导体封装的性能。
一般来说,半导体封装制造商接收已完成的半导体封装衬底(即所谓的引线框架),在其上安装半导体芯片,并执行后续工艺。在这种情况下,半导体封装制造商可在待于半导体封装制造之后的半导体封装的焊接期间焊接的半导体封装的部分处形成凹槽,且因此可能降低半导体封装衬底和半导体封装的品质。
相比之下,在制造根据一实施例的半导体封装的方法中,在半导体封装衬底(即引线框架)的制造期间,在不执行额外工艺的情况下形成与切割区域CA相对应的第二凹槽或沟槽100e,且因此可在于半导体芯片封装之后不执行额外工艺的情况下,有效形成可润湿侧翼结构WF。此外,可提供具有可润湿侧翼结构WF的半导体封装衬底,且因而可显著改进产品竞争力。
根据如上文所描述的一或多个实施例,可实施一种制造以简易方式对其执行焊接的半导体封装衬底的方法和一种使用所述方法制造的半导体封装衬底,以及一种制造半导体封装的方法和一种使用所述方法制造的半导体封装。然而,本公开的范围不限于此。
虽然已参考图式描述了一或多个实施例,但本领域的普通技术人员将理解,可在其中作出对形式和细节的各种改变,且可在不脱离如由以下权利要求书所界定的本公开的精神和范围的情况下,执行与其等效的实施例。因此,本公开的范围应由所附权利要求书的技术理念来界定。
Claims (15)
1.一种制造半导体封装衬底的方法,其特征在于,所述方法包括:
在基底衬底的底部表面中形成多个第一凹槽或多个第一沟槽,所述基底衬底具有顶部表面和所述底部表面且由导电材料形成;
用树脂填充所述多个第一凹槽或沟槽;
固化所述树脂;
去除过度填充于所述多个第一凹槽或沟槽中的所述树脂的暴露部分;
对所述基底衬底的所述顶部表面进行蚀刻以暴露填充于所述多个第一凹槽或沟槽中的所述树脂的至少部分;以及
在所述基底衬底的所述底部表面中形成第二凹槽或第二沟槽,
所述第二凹槽或沟槽在用所述树脂填充所述基底衬底之后形成。
2.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,对所述基底衬底的所述顶部表面的所述蚀刻与所述第二凹槽或沟槽的所述形成同时执行。
3.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,所述第二凹槽或沟槽的所述形成包括沿切割线形成所述第二凹槽或沟槽。
4.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,所述第二凹槽或沟槽的所述形成包括在用所述树脂填充的相邻的所述多个第一凹槽或沟槽之间形成所述第二凹槽或沟槽。
5.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,在用所述树脂对所述多个第一凹槽或沟槽进行所述填充之前,进一步包括使所述多个第一凹槽或沟槽的内部表面粗糙化。
6.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,经由所述多个第一凹槽或沟槽暴露于所述基底衬底的所述底部表面上的所述树脂的面积大于经由所述第二凹槽或沟槽暴露于所述基底衬底的所述顶部表面上的所述树脂的面积。
7.根据权利要求1所述的制造半导体封装衬底的方法,其特征在于,进一步包括在所述基底衬底上形成镀层。
8.根据权利要求7所述的制造半导体封装衬底的方法,其特征在于,所述镀层的所述形成包括在所述第二凹槽或沟槽的内部表面上形成所述镀层。
9.一种半导体封装衬底,其特征在于,通过根据权利要求1所述的方法来制造。
10.一种制造半导体封装的方法,其特征在于,所述方法包括:
在基底衬底的底部表面中形成多个第一凹槽或多个第一沟槽,所述基底衬底具有顶部表面和所述底部表面且由导电材料形成;
用树脂填充所述多个第一凹槽或沟槽;
固化所述树脂;
去除过度填充于所述多个第一凹槽或沟槽中的所述树脂的暴露部分;
对所述基底衬底的所述顶部表面进行蚀刻以暴露填充于所述多个第一凹槽或沟槽中的所述树脂的至少部分;
在所述基底衬底的所述底部表面中形成第二凹槽或第二沟槽;
在所述基底衬底上安装半导体芯片;以及
沿所述第二凹槽或沟槽切割所述基底衬底,
所述第二凹槽或沟槽在用所述树脂填充所述基底衬底之后形成。
11.根据权利要求10所述的制造半导体封装的方法,其特征在于,对所述基底衬底的所述顶部表面的所述蚀刻与所述第二凹槽或沟槽的所述形成同时执行。
12.根据权利要求10所述的制造半导体封装的方法,其特征在于,所述第二凹槽或沟槽的所述形成包括在用所述树脂填充的相邻的多个第一凹槽或沟槽之间形成所述第二凹槽或沟槽。
13.根据权利要求10所述的制造半导体封装的方法,其特征在于,在所述基底衬底的所述切割中,用于切割所述基底衬底的切割线的宽度小于所述第二凹槽或沟槽的宽度。
14.根据权利要求10所述的制造半导体封装的方法,其特征在于,进一步包括在所述基底衬底上形成镀层。
15.一种半导体封装,其特征在于,通过根据权利要求10所述的方法来制造。
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