JP6783840B2 - 半導体パッケージ基板製造方法、及び半導体パッケージ製造方法 - Google Patents
半導体パッケージ基板製造方法、及び半導体パッケージ製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 148
- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 59
- 229920005989 resin Polymers 0.000 claims description 57
- 239000011347 resin Substances 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 37
- 238000005520 cutting process Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 13
- 238000007747 plating Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 5
- 238000007788 roughening Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 description 14
- 238000000465 moulding Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- -1 regions Substances 0.000 description 2
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017827 Cu—Fe Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910017985 Cu—Zr Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4814—Conductive parts
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53261—Refractory-metal alloys
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
20 半導体パッケージ
100 ベース基板
100c 第1溝または第1トレンチ
100e 第2溝または第2トレンチ
102,104 配線パターン
110 樹脂
120 メッキ層
130 半導体チップ
140 ワイヤ
150 モールディング層
Claims (11)
- 上面及び下面を有する伝導性素材のベース基板の下面に、第1溝または第1トレンチを形成する段階と、
第1溝または第1トレンチを樹脂で充填する段階と、
前記樹脂を硬化させる段階と、
第1溝または第1トレンチの外部に露出されて過充填された前記樹脂の部分を除去する段階と、
第1溝または第1トレンチを充填した前記樹脂の少なくとも一部が現れるように、ベース基板の上面をエッチングする段階と、
ベース基板の下面に、第2溝または第2トレンチを形成する段階と、を含み、
前記ベース基板の上面をエッチングする段階と、前記第2溝または第2トレンチを形成する段階は、同時に進められる、半導体パッケージ基板製造方法。 - 前記第2溝または第2トレンチを形成する段階において、第2溝または第2トレンチは、カッティングラインに沿って形成されることを特徴とする請求項1に記載の半導体パッケージ基板製造方法。
- 前記第2溝または第2トレンチを形成する段階において、第2溝または第2トレンチは、前記樹脂間に位置するように形成されることを特徴とする請求項1に記載の半導体パッケージ基板製造方法。
- 前記樹脂で充填する段階以前に、前記第1溝または第1トレンチの内面を粗化する段階をさらに含むことを特徴とする請求項1に記載の半導体パッケージ基板製造方法。
- 第1溝または第1トレンチを介してベース基板の下面に露出された前記樹脂の面積は、第2溝または第2トレンチを介してベース基板の上面に露出された前記樹脂の面積より大きいことを特徴とする請求項1に記載の半導体パッケージ基板製造方法。
- ベース基板上にメッキ層を形成する段階をさらに含むことを特徴とする請求項1に記載の半導体パッケージ基板製造方法。
- 前記メッキ層を形成する段階は、第2溝または第2トレンチの内面にメッキ層を形成する段階であることを特徴とする請求項6に記載の半導体パッケージ基板製造方法。
- 上面及び下面を有する伝導性素材のベース基板の下面に、第1溝または第1トレンチを形成する段階と、
第1溝または第1トレンチを樹脂で充填する段階と、
前記樹脂を硬化させる段階と、
第1溝または第1トレンチの外部に露出されて過充填された前記樹脂の部分を除去する段階と、
第1溝または第1トレンチを充填した前記樹脂の少なくとも一部が現れるように、ベース基板の上面をエッチングする段階と、
ベース基板の下面に、第2溝または第2トレンチを形成する段階と、
ベース基板上に半導体チップを実装する段階と、
第2溝または第2トレンチに沿ってベース基板をカットティングする段階と、
を含み、
前記ベース基板の上面をエッチングする段階と、前記第2溝または第2トレンチを形成する段階は、同時に進められる、半導体パッケージ製造方法。 - 前記第2溝または第2トレンチを形成する段階において、第2溝または第2トレンチは、前記樹脂間に位置するように形成されることを特徴とする請求項8に記載の半導体パッケージ製造方法。
- 前記ベース基板をカットティングする段階において、ベース基板をカットティングするカッティングラインの幅は、第2溝または第2トレンチの幅より狭いことを特徴とする請求項8に記載の半導体パッケージ製造方法。
- ベース基板上にメッキ層を形成する段階をさらに含むことを特徴とする請求項8に記載の半導体パッケージ製造方法。
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