CN109545850A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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Publication number
CN109545850A
CN109545850A CN201711170201.6A CN201711170201A CN109545850A CN 109545850 A CN109545850 A CN 109545850A CN 201711170201 A CN201711170201 A CN 201711170201A CN 109545850 A CN109545850 A CN 109545850A
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layer
area
dielectric layer
semiconductor element
substrate
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CN109545850B (zh
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陈智伟
林恒光
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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Abstract

本发明实施例揭示一种半导体元件，包括：基板、二极管、通道层、阻障层、第一介电层、源极、漏极以及栅极。二极管配置于基板上或基板中。通道层配置于二极管上。阻障层配置于通道层上。第一介电层配置于阻障层上。源极通过穿过第一介电层、阻障层以及通道层的第一导通孔电性连接至二极管的第一区域。漏极通过穿过第一介电层、阻障层以及通道层的第二导通孔电性连接至二极管的第二区域。栅极配置于源极与漏极之间的通道层上。

Description

半导体元件及其制造方法
技术领域
本发明是有关于一种集成电路及其制造方法，且特别是有关于一种半导体元件及其制造方法。
背景技术
近年来，以III-V族化合物半导体为基础的高电子迁移率晶体管(high electronmobility transistor，HEMT)元件具备高击穿电压、较大的能隙以及优异的载子迁移率，同时经由极化现象所产生的二维电子气可展现出色的低阻抗传导特性，使得III-V族化合物半导体材料广泛地应用在高频和功率元件。而金属-绝缘体-半导体的高电子迁移率晶体管(Metal-Insulator-Semiconductor HEMT，MIS-HEMT)元件则为HEMT元件中的一种。MIS-HEMT元件在金属与半导体界面处具有栅介电层，其可强化元件效能，例如高的击穿电压、低的栅极漏电流、低的元件阻抗及宽广的栅极操作范围等。
然而，所述栅介电层的结构也会导致额外的界面陷阱效应(interfacetrapping)，进而影响MIS-HEMT元件的电性，例如夹止电压(pinch off)飘移、电流衰退(current collapse)、可靠度失效…等问题。所述电性问题使得MIS-HEMT元件的应用受到限制。因此，如何避免MIS-HEMT元件产生界面陷阱效应已然成为重要的一门课题。
发明内容
本发明提供一种半导体元件，其可将MIS-HEMT元件并联二极管，以避免界面陷阱效应，进而提升元件效能。
本发明提供一种半导体元件的制造方法，其通过单芯片整合技术将MIS-HEMT元件与二极管整合在同一芯片上，以大幅降低芯片使用面积，进而达到微型化电子元件的需求。
本发明提供一种半导体元件，包括：基板、二极管、通道层、阻障层、第一介电层、源极、漏极以及栅极。二极管配置于基板上或基板中。所述二极管包括具有第一导电型的第一区域以及具有第二导电型的第二区域，所述第一导电型与所述第二导电型不同。通道层配置于二极管上。阻障层配置于通道层上。第一介电层配置于阻障层上。源极以穿过第一介电层、阻障层以及通道层的第一导通孔电性连接至二极管的第一区域。漏极以穿过第一介电层、阻障层以及通道层的第二导通孔电性连接至二极管的第二区域。栅极配置于源极与漏极之间的通道层上。
本发明提供一种半导体元件，包括：基板、通道层、阻障层、介电层、源极、漏极、栅极、阳极以及阴极。通道层配置于基板上。阻障层配置于所述通道层上。介电层配置于所述阻障层上。源极穿过所述介电层与所述阻障层且电性连接至所述通道层。漏极穿过所述介电层与所述阻障层且电性连接至所述通道层。栅极配置于所述源极与所述漏极之间的所述介电层上。阳极穿过所述介电层且电性连接至所述阻障层，并通过第一内连线电性连接至所述源极。阴极穿过所述介电层与所述阻障层且电性连接至所述通道层，并通过第二内连线电性连接至所述漏极。
本发明提供一种半导体元件的制造方法，其步骤如下。于基板的正面上依序形成通道层、阻障层以及介电层；于所述基板中分别形成具有第一导电型的第一区域与具有第二导电型的第二区域，其中所述第一导电型与所述第二导电型不同；于所述介电层、所述阻障层以及所述通道层中形成第一导通孔，使得源极通过所述第一导通孔电性连接至所述第一区域；于所述介电层、所述阻障层以及所述通道层中形成第二导通孔，使得漏极通过所述第二导通孔电性连接至所述第二区域；以及于所述源极与所述漏极之间的所述介电层上形成栅极。
基于上述，本发明通过单芯片整合技术将MIS-HEMT元件与二极管并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A至图1E是本发明的第一实施例的一种半导体元件的制造流程剖面示意图。
图2是本发明的第二实施例的一种半导体元件的剖面示意图。
图3是本发明的第三实施例的一种半导体元件的剖面示意图。
图4是本发明的第四实施例的一种半导体元件的剖面示意图。
图5是本发明的第五实施例的一种半导体元件的剖面示意图。
图6是本发明的第六实施例的一种半导体元件的剖面示意图。
图7是本发明的第七实施例的一种半导体元件的剖面示意图。
附图标号：
1、2、3、4、5、6、7：半导体元件
10a、10b、10c、10d：MIS-HEMT元件
20a、20d、20e：P-N结二极管
20b：PIN结二极管
20c：共振穿隧二极管
20f：萧特基二极管
100、200、300：基板
100a、400a、500a：第一区域
100b、400b、500b：第二区域
100c：第三区域
101：第三区域
101a：第一层
101b：第二层
102：缓冲层
104：通道层
105：二维电子气
106：阻障层
108、118：介电层
110、410、510：第一导通孔
112：第一开口
120、420、520：第二导通孔
122：第二开口
130：第三导通孔
132：第三开口
140：退火处理
D：漏极
G：栅极
S：源极
S1：正面
S2：背面
具体实施方式
参照本实施例的图式以更全面地阐述本发明。然而，本发明亦可以各种不同的形式体现，而不应限于本文中所述的实施例。图式中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再赘述。
请参照图1A，本发明的第一实施例提供一种半导体元件的制造方法，其步骤如下。首先，提供基板100，基板100具有彼此相对的正面S1与背面S2。在一实施例中，基板100可视为一成长基板，其材料可例如是蓝宝石(Sapphire)、碳化硅(SiC)、氮化铝(AlN)、硅(Si)、锗(Ge)、砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)或其组合。在本实施例中，基板100可以是硅基板。
接着，在基板100的正面S1上依序形成缓冲层102、通道层104、阻障层106以及介电层108。在一实施例中，缓冲层102、通道层104、阻障层106以及介电层108的形成方法可以是外延成长法，例如是有机金属化学气相沉积法(Metal-organic Chemical VaporDeposition，MOCVD)或分子束外延法(Molecular Beam Epitaxy，MBE)。
详细地说，缓冲层102可配置于基板100和通道层104之间，以减少基板100和通道层104之间的晶格常数差异与热膨胀系数差异。在一实施例中，缓冲层102的材料包括III族氮化物，例如III-V族化合物半导体材料，并可具有单层或多层结构。在替代实施例中，缓冲层102的材料包括AlN、GaN、AlGaN、InGaN、AlInN、AlGaInN或其组合。
通道层104可配置于缓冲层102和阻障层106之间。由于通道层104与阻障层106之间形成异质结，使得接近阻障层106的通道层104的区域中形成具有高电子迁移率的二维电子气(2DEG)105。在一实施例中，通道层104的材料包括III族氮化物，例如III-V族化合物半导体材料，其可例如是未经掺杂(undoped)或非刻意掺杂(unintentionally doped)的GaN。但本发明不以此为限，在其他实施例中，只要通道层104的材料的能隙与阻障层106的材料的能隙不同，所述通道层104的材料皆为本发明的范畴。
阻障层106可配置于通道层104(或二维电子气105)和介电层108之间。在一实施例中，阻障层106的材料包括III族氮化物，例如III-V族化合物半导体材料，并可具有单层或多层结构。在一实施例中，阻障层106包括AlGaN、AlInN、AlN、AlGaInN或其组合。在一实施例中，阻障层106可以是经掺杂或未经掺杂的层。
介电层108可配置于阻障层106上。在一实施例中，介电层108的材料包括介电材料，并可具有单层或多层结构。在一实施例中，介电层108的材料包括氧化铝(Al2O3)、氮化硅、氧化硅、氮化铝(AlN)或其组合。
请参照图1B，于基板100中分别形成具有第一导电型的第一区域100a与具有第二导电型的第二区域100b。在一实施例中，第一导电型与第二导电型不同。当第一导电型为N型，第二导电型为P型；当第一导电型为P型，第二导电型为N型。P型掺质例如是硼；N型掺质例如是磷或是砷。在本实施例中，是以第一导电型为P型，第二导电型为N型为例来说明，但本发明并不以此为限。
详细地说，于基板100中分别形成第一区域100a与第二区域100b的步骤如下。将基板100的背面S2朝上，于基板100的背面S2上形成第一掩膜图案(未绘示)，以覆盖第二区域100b且暴露出第一区域100a。对第一区域100a进行第一离子注入工艺，使得第一区域100a的基板100的导电型转变为P型。在一实施例中，第一区域100a所植入的掺质可例如是硼，掺杂的浓度可例如是1×1018/cm3至1×1020/cm3。
移除所述第一掩膜图案后，于基板100的背面S2上形成第二掩膜图案(未绘示)，以覆盖第一区域100a且暴露出第二区域100b。对第二区域100b进行第二离子注入工艺，使得第二区域100b的基板100的导电型转变为N型。在一实施例中，第二区域100b所植入的掺质可例如是磷或是砷，掺杂的浓度可例如是1×1018/cm3至1×1020/cm3。
在本实施例中，是先形成第一区域100a，随后形成第二区域100b，但本发明不以此为限。在其他实施例中，可先形成第二区域100b，随后形成第一区域100a。在替代实施例中，亦可利用P型基板，进行一道微影工艺与离子注入工艺，以形成N型掺杂区。
需注意的是，如图1B所示，第一区域100a与第二区域100b彼此相连，且构成一整个基板100。在本实施例中，P型的第一区域100a与N型的第二区域100b可构成P-N结二极管20a。所述P-N结二极管20a内埋在基板100中。换言之，整个基板100变成了一个P-N结二极管20a。
请参照图1C，移除所述第二掩膜图案后，将基板100的正面S1朝上。之后，于介电层108、阻障层106、通道层104以及缓冲层102中形成第一导通孔110与第二导通孔120。源极S可通过第一导通孔110电性连接至基板100的第一区域100a。漏极D可通过第二导通孔120电性连接至基板100的第二区域100b。
具体来说，第一导通孔110与第二导通孔120的形成步骤可包括在介电层108上形成第三掩膜图案(未绘示)，以定义出第一导通孔110与第二导通孔120的位置。接着，以第三掩膜图案为蚀刻掩膜，移除部分介电层108、部分阻障层106、部分通道层104以及部分缓冲层102，以形成第一开口112与第二开口122。第一开口112暴露出基板100的第一区域100a的部分表面；第二开口122暴露出基板100的第二区域100b的部分表面。之后，通过电镀法或蒸发法，将导电材料填入第一开口112与第二开口122中，以于第一开口112中形成第一导通孔110并于第一导通孔110上形成源极S，且于第二开口122中形成第二导通孔120并于第二导通孔120上形成漏极D。在一实施例中，所述导电材料可包括金属(例如Ta、Ti、W、Pd、Ni、Au、Al或其组合)、金属氮化物(例如TaN、TiN、WN或其组合)、金属硅化物(例如WSix)或其组合。
请参照图1D，移除所述第三掩膜图案后，进行退火(Anneal)处理140。在本实施例中，退火处理140不仅可修复离子注入后的第一区域100a与第二区域100b的晶格损伤，还可分别将第一导通孔110与第二导通孔120中的金属(例如铝)扩散至半导体层(例如第一区域100a、第二区域100b、通道层104等)中，以形成欧姆接触(Ohmic contact)。在一实施例中，退火处理140包括快速热退火处理(RTA)或炉管退火处理。以快速热退火处理为例，快速热退火处理的处理温度可例如是800℃至1000℃；其处理时间可例如是10秒至120秒。
请参照图1E，于源极S与漏极D之间的介电层108上形成栅极G。在一实施例中，栅极G的材料包括导电材料。所述导电材料可包括金属(例如Ta、Ti、W、Pd、Ni、Au、Al或其组合)、金属氮化物(例如TaN、TiN、WN或其组合)、金属硅化物(例如WSix)或其组合。在一实施例中，源极S、漏极D以及栅极G的材料可以相同，但本发明不以此为限。在其他实施例中，源极S、漏极D以及栅极G的材料可彼此不同。
请参照图1E，第一实施例提供一种半导体元件1，包括：基板100、缓冲层102、通道层104、阻障层106、介电层108、源极S、漏极D以及栅极G。缓冲层102、通道层104(其在靠近阻障层106处具有二维电子气105)、阻障层106、介电层108依序配置于基板100的正面S1上。基板100包括彼此相连的第一区域100a与第二区域100b，其构成P-N结二极管20a。源极S通过穿过介电层108、阻障层106、通道层104以及缓冲层102的第一导通孔110电性连接至第一区域100a。漏极D通过穿过介电层108、阻障层106、通道层104以及缓冲层102的第二导通孔120电性连接至第二区域100b。栅极G配置于源极S与漏极D之间的介电层108上。
值得注意的是，本实施例可将P型的第一区域100a与N型的第二区域100b所构成的P-N结二极管20a与MIS-HEMT元件10a并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
图2是本发明的第二实施例的一种半导体元件的剖面示意图。
请参照图2，第二实施例的半导体元件2与第一实施例的半导体元件1基本上相似。上述两者不同之处在于：半导体元件2的基板200更包括第三区域100c，其配置于第一区域100a与第二区域100b之间。在一实施例中，第三区域100c可以是本征区域(intrinsicregion)或非掺杂区域。因此，P型的第一区域100a、N型的第二区域100b以及本征或非掺杂的第三区域100c可构成PIN结二极管20b。所述PIN结二极管20b内埋在基板200中。换言之，整个基板200变成了一个PIN结二极管20b。
在本实施例中，PIN结二极管20b与MIS-HEMT元件10a并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。相较于P-N结二极管，所述PIN结二极管20b可承受更大的操作电压(例如10伏特至3000伏特)。
图3是本发明的第三实施例的一种半导体元件的剖面示意图。
请参照图3，第三实施例的半导体元件3与第二实施例的半导体元件2基本上相似。上述两者不同之处在于：半导体元件3的第三区域101包括多层结构，其具有沿着第一区域100a朝着第二区域100b的方向交替排列的多个第一层101a与多个第二层101b。在一实施例中，第一层101a可以是Si层；第二层101b可以是SiGe层。如图3所示，P型的第一区域100a、N型的第二区域100b以及具有多层结构的第三区域101可构成共振穿隧二极管(ResonantTunneling Diode，RTD)20c。所述共振穿隧二极管20c内埋在基板300中。换言之，整个基板300变成了一个共振穿隧二极管20c。
在本实施例中，共振穿隧二极管20c与MIS-HEMT元件10a并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。所述共振穿隧二极管20c可增加能带宽度，进而抑制漏电流。
图4是本发明的第四实施例的一种半导体元件的剖面示意图。
请参照图4，第四实施例的半导体元件4与第一实施例的半导体元件1基本上相似。上述两者不同之处在于：半导体元件4的P-N结二极管20d配置在基板100上。具体来说，P-N结二极管20d配置在缓冲层102与通道层104之间。源极S可通过穿过介电层108、阻障层106以及通道层104的第一导通孔410电性连接至第一区域400a。漏极D通过穿过介电层108、阻障层106以及通道层104的第二导通孔420电性连接至第二区域400b。
在本实施例中，PIN结二极管20d与MIS-HEMT元件10b并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
图5是本发明的第五实施例的一种半导体元件的剖面示意图。
请参照图5，第五实施例的半导体元件5与第四实施例的半导体元件4基本上相似。上述两者不同之处在于：半导体元件5的P-N结二极管20e配置在基板100与缓冲层102之间。源极S可通过穿过介电层108、阻障层106、通道层104以及缓冲层102的第一导通孔510电性连接至第一区域500a。漏极D通过穿过介电层108、阻障层106、通道层104以及缓冲层102的第二导通孔520电性连接至第二区域500b。
在本实施例中，P-N结二极管20e与MIS-HEMT元件10a并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
在一实施例中，半导体元件1、2、3、4、5可以是空乏型(D-mode)高电子迁移率晶体管元件。也就是说，在未施加栅极电压下，通道层104中的二维电子气(或载子通道)105可例如是常开(normally-on)状态；而施加栅极电压下，则可关闭此类空乏型高电子迁移率晶体管之通道层104中的二维电子气(或载子通道)105。
图6是本发明的第六实施例的一种半导体元件的剖面示意图。
请参照图6，第六实施例的半导体元件6与第一实施例的半导体元件1基本上相似。上述两者不同之处在于：半导体元件6更包括介电层118，其共形地配置于介电层108与阻障层106中的第三开口132中。将导电材料填入第三开口132，以形成第三导通孔130。在本实施例中，第三导通孔130可视为栅极G。第三开口132中的介电层118位于栅极G与介电层108之间、位于栅极G与阻障层106之间，且位于栅极G与通道层104之间。在一实施例中，第三开口132至少暴露出通道层104的顶面，使得第三开口132下方的通道层104中不形成二维电子气105。在其他实施例中，如图6所示，第三开口132更延伸至通道层104中，使得二维电子气105分别配置于第三开口132的两侧。
另外，介电层118不仅共形覆盖第三开口132的表面，还延伸覆盖介电层108的顶面。在一实施例中，介电层118可视为栅介电层，其可降低栅极G的漏电流，并可通过改变其厚度以调整阈值电压(Threshold Voltage，Vth)。介电层118的材料包括氧化铝(Al2O3)、氮化硅、氧化硅、氮化铝(AlN)或其组合，其形成方法可以是外延成长法，例如是MOCVD或MBE。
此外，如图6所示，半导体元件6的源极S内埋在介电层118、108以及阻障层106中，其通过穿过通道层104以及缓冲层102的第一导通孔110电性连接至第一区域100a。漏极D也是内埋在介电层118、108以及阻障层106中，其通过穿过通道层104以及缓冲层102的第二导通孔120电性连接至第二区域100b。在一实施例中，第一导通孔110及其上方的源极S亦可视为单一源极结构；而第二导通孔120及其上方的漏极D亦可视为单一漏极结构。
在一实施例中，半导体元件6可以是增强型(E-mode)高电子迁移率晶体管元件。也就是说，在未施加栅极电压下，通道层104中的二维电子气(或载子通道)105可例如是常关(normally-off)状态；而施加栅极电压下，则可开启此类增强型型高电子迁移率晶体管之通道层104中的二维电子气(或载子通道)105。另外，在本实施例中，P-N结二极管20a与MIS-HEMT元件10c并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
图7是本发明的第七实施例的一种半导体元件的剖面示意图。
本实施例提供一种半导体元件7，包括基板100、通道层104、阻障层106、介电层108、层间介电层116、源极S、漏极D、栅极G、阳极A以及阴极C。通道层104(其在靠近阻障层106处具有二维电子气105)、阻障层106、介电层108以及层间介电层116依序配置于基板100上。
在一实施例中，源极S可以是导通孔形式，其穿过层间介电层116、介电层108以及阻障层106且电性连接至通道层104。在替代实施例中，如图7所示，源极S亦可延伸至通道层104中，使得二维电子气105位于源极S的两侧。
在一实施例中，漏极D可以是导通孔形式，其穿过层间介电层116、介电层108以及阻障层106的第二导通孔120且电性连接至通道层104。在替代实施例中，如图7所示，漏极D亦可延伸至通道层104中，使得二维电子气105位于漏极D的两侧。
在一实施例中，栅极G可以是导通孔形式，其穿过层间介电层116且配置于源极S与漏极D之间的介电层108上。在一实施例中，阳极A可以是导通孔形式，其穿过层间介电层116与介电层108且电性连接至阻障层106，并通过第一内连线150电性连接至源极S。在一实施例中，阴极C可以是导通孔形式，其穿过层间介电层116、介电层108以及阻障层106且电性连接至通道层104，并通过第二内连线160电性连接至漏极D。在替代实施例中，如图7所示，阴极C亦可延伸至通道层104中，使得二维电子气105位于阴极C的两侧。
在一实施例中，阳极A与阻障层106可构成萧特基二极管(Schottky diode)20f。阴极C与通道层104可构成欧姆接触。因此，所述MIS-HEMT元件10d便可通过第一内连线150以及第二内连线160与萧特基二极管20f并联且整合在同一芯片上。也就是说，本发明可通过内连线的方式可将各种不同元件(不限于MIS-HEMT元件)与各种不同二极管并联且整合在同一芯片上，以降低芯片使用面积。
在其他实施例中，半导体元件7亦可包括缓冲层(未绘示)，其配置于基板100和通道层104之间，以减少基板100和通道层104之间的晶格常数差异与热膨胀系数差异。
综上所述，本发明通过单芯片整合技术将MIS-HEMT元件与二极管并联且整合在同一芯片上，其不仅可大幅降低芯片使用面积，还可避免界面陷阱效应，进而提升元件效能。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求范围所界定者为准。

Claims (16)

1.一种半导体元件，其特征在于，包括：
二极管，配置于基板上或基板中，其中所述二极管包括具有第一导电型的第一区域以及具有第二导电型的第二区域，所述第一导电型与所述第二导电型不同；
通道层，配置于所述二极管上；
阻障层，配置于所述通道层上；
第一介电层，配置于所述阻障层上；
源极，以穿过所述第一介电层、所述阻障层以及所述通道层的第一导通孔电性连接至所述二极管的所述第一区域；
漏极，以穿过所述第一介电层、所述阻障层以及所述通道层的第二导通孔电性连接至所述二极管的所述第二区域；以及
栅极，配置于所述源极与所述漏极之间的所述通道层上。
2.如权利要求1所述的半导体元件，其特征在于，所述二极管的所述第一区域与所述二极管的所述第二区域彼此相连。
3.如权利要求1所述的半导体元件，其特征在于，所述二极管的所述第一区域与所述二极管的所述第二区域之间具有第三区域，所述第三区域为本征区域或非掺杂区域。
4.如权利要求1所述的半导体元件，其特征在于，所述二极管的所述第一区域与所述二极管的所述第二区域之间具有第三区域，所述第三区域包括多层结构，其具有沿着所述第一区域至所述第二区域的方向交替排列的多个第一层与多个第二层。
5.如权利要求1所述的半导体元件，其特征在于，更包括缓冲层，其位于所述通道层与所述基板之间。
6.如权利要求5所述的半导体元件，其特征在于，所述二极管位于所述通道层与所述缓冲层之间，或者是所述二极管位于所述缓冲层与所述基板之间。
7.如权利要求1所述的半导体元件，其特征在于，所述半导体元件为增强型高电子迁移率晶体管元件，所述增强型高电子迁移率晶体管元件更包括：
第二介电层，共形地配置于所述第一介电层与所述阻障层中的开口中，所述栅极填入所述开口，使得所述开口中的所述第二介电层位于所述栅极与所述第一介电层之间、位于所述栅极与所述阻障层之间，且位于所述栅极与所述通道层之间。
8.一种半导体元件，其特征在于，包括：
通道层，配置于基板上；
阻障层，配置于所述通道层上；
介电层，配置于所述阻障层上；
源极，穿过所述介电层与所述阻障层且电性连接至所述通道层；
漏极，穿过所述介电层与所述阻障层且电性连接至所述通道层；
栅极，配置于所述源极与所述漏极之间的所述介电层上；
阳极，穿过所述介电层且电性连接至所述阻障层，并以第一内连线电性连接至所述源极；以及
阴极，穿过所述介电层与所述阻障层且电性连接至所述通道层，并以第二内连线电性连接至所述漏极。
9.如权利要求8所述的半导体元件，其特征在于，所述阳极与所述阻障层构成萧特基二极管。
10.如权利要求8所述的半导体元件，其特征在于，所述阴极与所述通道层构成欧姆接触。
11.一种半导体元件的制造方法，其特征在于，包括：
于基板的正面上依序形成通道层、阻障层以及介电层；
于所述基板中分别形成具有第一导电型的第一区域与具有第二导电型的第二区域，其中所述第一导电型与所述第二导电型不同；
于所述介电层、所述阻障层以及所述通道层中形成第一导通孔，使得源极通过所述第一导通孔电性连接至所述第一区域；
于所述介电层、所述阻障层以及所述通道层中形成第二导通孔，使得漏极通过所述第二导通孔电性连接至所述第二区域；以及
于所述源极与所述漏极之间的所述介电层上形成栅极。
12.如权利要求11所述的半导体元件的制造方法，其特征在于，于所述基板中分别形成所述第一区域与所述第二区域包括：
于所述基板的所述正面上形成所述介电层之后，于所述基板的背面上形成第一掩膜图案，以覆盖所述第二区域且暴露出所述第一区域；
对所述第一区域进行第一离子注入工艺；
移除所述第一掩膜图案；
于所述基板的所述背面上形成第二掩膜图案，以覆盖所述第一区域且暴露出所述第二区域；以及
对所述第二区域进行第二离子注入工艺。
13.如权利要求11所述的半导体元件的制造方法，其特征在于，所述第一区域与所述第二区域彼此相连。
14.如权利要求11所述的半导体元件的制造方法，其特征在于，所述第一区域与所述第二区域之间具有第三区域，所述第三区域为本征区域、非掺杂区域或多层结构。
15.如权利要求11所述的半导体元件的制造方法，其特征在于，所述第一导通孔与所述第二导通孔的形成方法包括：
于所述介电层上形成第三掩膜图案，以定义出所述第一导通孔与所述第二导通孔的位置；
以所述第三掩膜图案为掩膜，移除部分所述介电层、部分所述阻障层以及部分所述通道层，以形成第一开口与第二开口，所述第一开口暴露出所述基板的所述第一区域的部分表面，而所述第二开口暴露出所述基板的所述第二区域的部分表面；以及
将导电材料填入所述第一开口与所述第二开口中。
16.如权利要求11所述的半导体元件的制造方法，其特征在于，在形成所述第一导通孔与所述第二导通孔之后，更包括进行退火处理。
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