CN109273441A - 半导体器件结构及其制作方法 - Google Patents

半导体器件结构及其制作方法 Download PDF

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Publication number
CN109273441A
CN109273441A CN201811021268.8A CN201811021268A CN109273441A CN 109273441 A CN109273441 A CN 109273441A CN 201811021268 A CN201811021268 A CN 201811021268A CN 109273441 A CN109273441 A CN 109273441A
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type
channel
semiconductor channel
type semiconductor
device structure
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CN109273441B (zh
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肖德元
张汝京
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Xinen (qingdao) Integrated Circuit Co Ltd
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Xinen (qingdao) Integrated Circuit Co Ltd
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Priority to CN201811021268.8A priority Critical patent/CN109273441B/zh
Publication of CN109273441A publication Critical patent/CN109273441A/zh
Priority to TW108114241A priority patent/TW202011610A/zh
Priority to US16/556,181 priority patent/US11049857B2/en
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Abstract

本发明提供一种半导体器件结构及其制作方法，结构包括：衬底；P型半导体沟道及N型半导体沟道，悬空于衬底上；栅介质层，包围P型半导体沟道及N型半导体沟道；栅电极层，包围栅介质层；P型源区及P型漏区，连接于P型半导体沟道的两端；N型源区及N型漏区，连接于N型半导体沟道的两端；其中，P型半导体沟道的P型离子掺杂浓度自P型半导体沟道的表面朝中心逐渐减小，N型半导体沟道的N型离子掺杂浓度自N型半导体沟道的表面朝中心逐渐减小，P型半导体沟道的截面宽度大于N型半导体沟道的截面宽度。本发明可以在单位面积下实现器件的多层堆叠，有效缩短沟道长度，降低短沟道效应，提高器件的负载能力及栅极对沟道的控制能力。

Description

半导体器件结构及其制作方法
技术领域
本发明属于集成电路设计制造，特别是涉及一种三维堆叠的无结型梯度掺杂沟道半导体器件结构及其制作方法。
背景技术
随着半导体技术的不断发展，半导体器件的尺寸不断缩小，驱动电流等性能不断提升，功耗不断降低，同时也面临越来越严重的短沟效应，越来越复杂的半导体制造工艺以及较高的生产成本。
鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)是一种新的互补式金氧半导体晶体管。FinFET的形状与鱼鳍相，这种设计可以改善电路控制并减少漏电流，缩短晶体管的闸长。
FinFET是源自于传统标准的晶体管—场效应晶体管(Field-Effect Transistor；FET)的一项创新设计。在传统晶体管结构中，栅极只能控制电流在沟道区的一个表面的接通与断开，属于平面的架构。在FinFET的架构中，栅极被设计呈鱼鳍状的3D架构，可于鱼鳍状的栅极的两侧控制电路的接通与断开。这种设计可以大幅改善电路控制并减少漏电流(leakage)，也可以大幅缩短晶体管的沟道长度。
在2011年初，英特尔公司推出了商业化的FinFET，使用在其22纳米节点的工艺上，为未来的移动处理器等提供更快，更省电的处理器。从2012年起，FinFET已经开始向20纳米节点和14纳米节点推进。2015年三星率先将FinFET技术用于10nm制程，2016年台积电也将FinFET技术用于10nm制程节点。
作为FinFET技术的一个改进，三面包围栅场效应晶体管可以有效提高场效应晶体管的功率和效率，是最近才开始用于服务器、计算机和设备等领域，三面包围栅场效应晶体管将会是未来几年的主流技术。
随着对器件集成度、功率及性能需求的进一步提高，通过将硅纳米片层叠在一起，可以进一步提高功率和性能。在美国专利US8350298中，肖德元等提出了一种混合晶向积累型全包围栅CMOS场效应晶体管，如图1所示，其包括：底层半导体衬底1010、具有第一沟道401的PMOS区域400、具有第二沟道301的NMOS区域300及一个栅区域500。所述第一沟道401及第二沟道301的横截面均为跑道形。所述栅区域500将所述第一沟道401及第二沟道301的表面完全包围。该器件可避免多晶硅栅耗尽及短沟道效应，增大器件的阈值电压。然而，当器件沟道长度进入深纳米尺度以后，传统反型沟道器件的源漏突变PN结的掺杂浓度需要在几纳米之内变化几个数量级，实现这种大浓度梯度对于掺杂技术设计会带来很大的困难，并且这些复杂工艺的制造成本很高，影响半导体器件的批量化生产。此外，突变PN结空间电荷区的极限尺寸是纳米量级的，所以突变PN结的存在从物理本质上限制了沟道长度的进一步缩小。同时，随着沟道的缩短，要求栅极对沟道的控制越来越强，以避免
基于以上所述，提供一种可以进一步提高器件功率及性能、并可有效缩短器件沟道长度的半导体器件结构实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种半导体器件结构及其制作方法，用于解决现有技术中器件的功率不足以及沟道长度难以进一步降低的问题。
为实现上述目的及其他相关目的，本发明提供一种半导体器件结构，包括：衬底；P型半导体沟道，悬空于所述衬底之上；N型半导体沟道，悬空于所述衬底之上；栅介质层，包围于所述P型半导体沟道及所述N型半导体沟道；栅电极层，包围于所述栅介质层；P型源区及P型漏区，分别连接于所述P型半导体沟道的两端；以及N型源区及N型漏区，分别连接于所述N型半导体沟道的两端；其中，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小，所述P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度。
可选地，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心呈线性减小或梯度减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心呈线性减小或梯度减小。
可选地，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面相对中心减小的数量级不小于102，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面相对中心减小的数量级不小于102。
可选地，所述P半导体沟道的材质包含P型离子掺杂的硅，所述N型半导体沟道的材质包含N型离子掺杂的硅。
可选地，所述P型源区及P型漏区的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区的材质包含N型离子掺杂的碳化硅。
可选地，所述P型源区及P型漏区的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区分别包覆于所述P型半导体沟道的两端，所述N型源区及N型漏区的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区分别包覆于所述N型半导体沟道的两端。
可选地，所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的1.5～10倍。
可选地，所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的2～4倍。
可选地，所述P型半导体沟道及所述N型半导体沟道均经过圆角化处理而具有圆角矩形的截面形状。
可选地，包括至少两个自所述衬底向上堆叠的P型半导体沟道及两个自所述衬底向上堆叠的N型半导体沟道，其中，基于所述P型半导体沟道形成无结型梯度掺杂沟道P型场效应晶体管，基于所述N型半导体沟道形成无结型梯度掺杂沟道N型场效应晶体管，且相邻两无结型梯度掺杂沟道N型场效应晶体管之间及相邻两无结型梯度掺杂沟道P型场效应晶体管之间均具有间距，所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极由一共用电极连接，以形成倒相器。
可选地，所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述共用电极的材质包括Al、W及Cu中的一种。
本发明还提供一种半导体器件结构的制作方法，包括步骤：1)提供一衬底，于所述衬底上形成悬空于所述衬底之上的P型半导体沟道及N型半导体沟道，其中，所述P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小；2)形成包围于所述P型半导体沟道及N型半导体沟道的栅介质层；3)形成包围于所述栅介质层的栅电极层；4)于所述P型半导体沟道的两端分别形成P型源区及P型漏区；以及5)于所述N型半导体沟道的两端分别形成N型源区及N型漏区。
可选地，步骤1)包括：1-1)提供一衬底，于所述衬底上形成堆叠的若干基体结构层，所述基体结构层包括牺牲层以及位于所述牺牲层上的沟道层；1-2)刻蚀所述若干基体结构层，以在所述衬底上形成相邻的第一鳍形结构及第二鳍形结构，所述第一鳍形结构包括交替层叠的若干第一牺牲单元及若干第一半导体沟道，所述第二鳍形结构包括交替层叠的若干第二牺牲单元及若干第二半导体沟道，所述第一半导体沟道的截面宽度大于所述第二半导体沟道的截面宽度；1-3)选择性去除所述第一鳍形结构中的第一牺牲单元及所述第二鳍形结构中的第二牺牲单元，以获得悬空的若干第一半导体沟道及悬空的若干第二半导体沟道；以及1-4)对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道，对所述第二半导体沟道进行N型离子掺杂以形成N型半导体沟道。
可选地，步骤1-4)对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道包括：a)于所述第一半导体沟道表面沉积硼离子重掺杂的介质层；b)热处理以驱动所述介质层中的硼离子向所述第一半导体沟道内扩散，以形成P型半导体沟道，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小；c)湿法腐蚀去除所述介质层。
可选地，步骤1-4)对所述第二半导体沟道进行N型离子掺杂以形成N型半导体沟道包括：a)于所述第二半导体沟道表面沉积磷离子或砷离子重掺杂的介质层；b)热处理以驱动所述介质层中的磷离子或砷离子向所述第二半导体沟道内扩散，以形成N型半导体沟道，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小；c)湿法腐蚀去除所述介质层。
可选地，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面相对中心减小的数量级不小于102，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面相对中心减小的数量级不小于102。
可选地，所述P半导体沟道的材质包含P型离子掺杂的硅，所述N型半导体沟道的材质包含N型离子掺杂的硅。
可选地，所述P型源区及P型漏区的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区的材质包含N型离子掺杂的碳化硅。
可选地，所述P型源区及P型漏区的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区分别包覆于所述P型半导体沟道的两端，所述N型源区及N型漏区的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区分别包覆于所述N型半导体沟道的两端。
可选地，所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的1.5～10倍。
可选地，所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的2～4倍。
可选地，步骤1)还包括对所述P型半导体沟道及N型半导体沟道进行圆角化处理的步骤，使得所述P型半导体沟道及N型半导体沟道具有圆角矩形的截面形状。
可选地，步骤1)于所述衬底上形成至少两个自所述衬底向上堆叠的P型半导体沟道及两个自所述衬底向上堆叠的N型半导体沟道，且相邻两P型半导体沟道之间及相邻两N型半导体沟道之间均具有间距，步骤4)基于所述P型半导体沟道形成无结型梯度掺杂沟道P型场效应晶体管及步骤5)基于所述N型半导体沟道形成无结型梯度掺杂沟道N型场效应晶体管之后，还包括沉积共用电极的步骤，所述共用电极连接所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极，以形成倒相器。
可选地，所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述无结型梯度掺杂沟道P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述共用电极的材质包括Al、W及Cu中的一种。
如上所述，本发明的半导体器件结构及其制作方法，具有以下有益效果：
本发明提出了一种三维堆叠结构的全包围栅无结型梯度掺杂沟道场效应晶体管结构，可以在单位面积下实现器件的多层堆叠，同时有效缩短器件的沟道长度，降低短沟道效应，有效提高器件的集成度，大大提高器件的功率。
本发明的P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度，通过提高P型半导体沟道的截面面积，以提高空穴的迁移量，从而提高P型场效应晶体管的电流负载能力，降低器件的导通电阻；同时，基于N型沟道的电子迁移率高于P型半导体沟道，将N型半导体沟道的截面宽度设计得较小，可以在保证N型场效应晶体管的电流负载能力的同时，缩小N型半导体沟道的面积，降低其关断所需电压，缩小器件的总面积，提高器件的集成度。
本发明通过外延方式形成P型场效应晶体管的P型源区及P型漏区以及N型场效应晶体管的N型源区及N型漏区，并采用锗硅作为P型源区及P型漏区的基体材料以及采用碳化硅作为N型源区及N型漏区的基体材料，可以有效提高P型源区及P型漏区的空穴迁移率，同时提高N型源区及N型漏区的电子迁移率，从而可以有效降低倒相器的导通电阻，提高倒相器的驱动电流。
本发明通过将P型离子掺杂浓度设计为自所述P型半导体沟道的表面朝中心逐渐减小，N型离子掺杂浓度设计为自所述N型半导体沟道的表面朝中心逐渐减小，可以降低沟道中的不受栅极控制的热载流子的浓度，有效提高栅极对沟道内空穴电荷或电子电荷的控制能力，提高器件性能。
附图说明
图1显示为现有技术中的一种混合晶向积累型全包围栅CMOS场效应晶体管的结构示意图。
图2显示为本发明的三维堆叠的无结型梯度掺杂沟道半导体器件结构的结构示意图。
图3显示为本发明的三维堆叠的无结型梯度掺杂沟道半导体器件结构通过共用电极连接N型场效应晶体管及P型场效应晶体管所形成结构的电路原理图。
图4～图13显示为本发明的三维堆叠的无结型梯度掺杂沟道半导体器件结构的制作方法各步骤所呈现的结构示意图。
元件标号说明
101 衬底
102 隔离层
20 基体结构层
201 牺牲层
202 沟道层
30 第一鳍形结构
301 第一牺牲单元
302 第一半导体沟道
40 第二鳍形结构
401 第二牺牲单元
402 第二半导体沟道
303、403 栅介质层
304、404 栅电极层
305 P型半导体沟道
405 N型半导体沟道
306 P型源区及P型漏区
406 N型源区及N型漏区
50 共用电极
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2～图13。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图2所示，本实施例提供一种三维堆叠的无结型梯度掺杂沟道半导体器件结构，包括：衬底101、P型半导体沟道305、N型半导体沟道405、栅介质层303、403、栅电极层304、404、P型源区及P型漏区306、及N型源区及N型漏区406。
所述衬底101可以为硅衬、碳化硅衬底101、锗硅衬底101等。在本实施例中，所述衬底101为硅衬底101，所述衬底101表面还形成有隔离层102，以隔离衬底101与器件的有源区及后续形成的共用电极50，提高器件的性能。
如图2所示，所述P型半导体沟道305及所述N型半导体沟道405悬空于所述衬底101之上。所述P型半导体沟道305及所述N型半导体沟道405经过圆角化处理而具有圆角矩形的截面形状。所述P半导体沟道的材质可以为P型离子掺杂的硅，所述N型半导体沟道405的材质可以为N型离子掺杂的硅。在本实施例中，所述半导体器件结构包括两个自所述衬底101向上堆叠的P型半导体沟道305，以及两个自所述衬底101向上堆叠的N型半导体沟道405，所述P型半导体沟道305用以形成P型场效应晶体管，所述N型半导体沟道405用以形成N型场效应晶体管，所述P型半导体沟道305的截面宽度大于所述N型半导体沟道405的截面宽度。例如，所述P型半导体沟道305的截面宽度可以为所述N型半导体沟道405的截面宽度的1.5～10倍，更优选地，所述P型半导体沟道305的截面宽度为所述N型半导体沟道405的截面宽度的2～4倍。由于P型半导体沟道305中的空穴迁移率通常为N型半导体沟道405中的电子迁移率的三分之一左右，故将所述P型半导体沟道305的截面宽度为所述N型半导体沟道405的截面宽度的2～4倍，可以在保证P型场效应晶体管占用面积较小的情况下，有效提高的P型场效应晶体管的负载能力。本发明的P型半导体沟道305的截面宽度大于所述N型半导体沟道405的截面宽度，通过提高P型半导体沟道305的截面面积，以提高空穴的迁移量，从而提高P型场效应晶体管的电流负载能力，降低器件的导通电阻；同时，基于N型沟道的电子迁移率高于P型半导体沟道305，将N型半导体沟道405的截面宽度设计得较小，可以在保证N型场效应晶体管的电流负载能力的同时，缩小N型半导体沟道405的面积，降低其关断所需电压，缩小器件的总面积，提高器件的集成度。
所述P型半导体沟道305的P型离子掺杂浓度自所述P型半导体沟道305的表面朝中心逐渐减小，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面朝中心逐渐减小，例如，所述P型半导体沟道305的P型离子掺杂浓度自所述P型半导体沟道305的表面朝中心可以呈线性减小或梯度减小，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面朝中心可以呈线性减小或梯度减小。在本实施例中，所述P型半导体沟道305的P型离子掺杂浓度自所述P型半导体沟道305的表面相对中心减小的数量级不小于102，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面相对中心减小的数量级不小于102，以获得更好的效果。本发明通过将P型离子掺杂浓度设计为自所述P型半导体沟道的表面朝中心逐渐减小，N型离子掺杂浓度设计为自所述N型半导体沟道的表面朝中心逐渐减小，可以降低沟道中的不受栅极控制的热载流子的浓度，有效提高栅极对沟道内空穴电荷或电子电荷的控制能力，提高器件性能。
如图2所示，所述栅介质层303、403包围于所述P型半导体沟道305及所述N型半导体沟道405。所述栅介质层303、403可以为可以是二氧化硅、氧化铝、氮氧硅化合物、碳氧硅化合物或铪基的等高介电常数材料中的一种。
所述栅电极层304、404包围于所述栅介质层303、403，所述栅电极层304、404包括N型场效应晶体管的栅电极层404以及P型场效应晶体管的栅电极层304，所述P型场效应晶体管的栅电极层304与所述第一半导体沟道302对应设置，所述N型场效应晶体管的栅电极层404与所述第二半导体沟道402对应设置。
所述N型场效应晶体管的栅电极层404的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。所述P型场效应晶体管的栅电极层304的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。例如，所述N型场效应晶体管的栅电极层404与所述P型场效应晶体管的栅电极层304可以为相同的材质。
如图2所示，所述P型源区及P型漏区306分别连接于所述P型半导体沟道305的两端。所述N型源区及N型漏区406分别连接于所述N型半导体沟道405的两端。所述P型源区及P型漏区306的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区406的材质包含N型离子掺杂的碳化硅。所述P型源区及P型漏区306的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区306分别包覆于所述P型半导体沟道305的两端，所述N型源区及N型漏区406的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区406分别包覆于所述N型半导体沟道405的两端。本发明通过外延方式形成P型场效应晶体管的P型源区及P型漏区306以及N型场效应晶体管的N型源区及N型漏区406，并采用锗硅作为P型源区及P型漏区306的基体材料以及采用碳化硅作为N型源区及N型漏区406的基体材料，可以有效提高P型源区及P型漏区306的空穴迁移率，同时提高N型源区及N型漏区406的电子迁移率，从而可以有效降低倒相器的导通电阻，提高倒相器的驱动电流。
如图2所示，所述半导体器件结构包括至少两个自所述衬底向上堆叠的P型半导体沟道305及两个自所述衬底向上堆叠的N型半导体沟道405，其中，基于所述P型半导体沟道305形成无结型梯度掺杂沟道P型场效应晶体管，基于所述N型半导体沟道405形成无结型梯度掺杂沟道N型场效应晶体管，且相邻两无结型梯度掺杂沟道N型场效应晶体管之间及相邻两无结型梯度掺杂沟道P型场效应晶体管之间均具有间距，所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极由一共用电极连接，以形成倒相器。所述共用电极50的材质包括Al、W及Cu中的一种。
本发明提出了一种三维堆叠结构的全包围栅无结型梯度掺杂沟道场效应晶体管结构，可以在单位面积下实现器件的多层堆叠，同时有效缩短器件的沟道长度，降低短沟道效应，有效提高器件的集成度，大大提高器件的功率。
图3显示为通过共用电极50连接的所述N型场效应晶体管及所述P型场效应晶体管所形成结构的电路原理图。该电路中，所述N型场效应晶体管的栅电极层404与所述P型场效应晶体管的栅电极相连后作为输入端Vin，所述P型场效应晶体管的源极与电源VDD相连，所述N型场效应晶体管的漏极与所述P型场效应晶体管的漏极相连，并作为输出端Vout，所述N型场效应晶体管的源极接地。
如图4～图13所示，本实施例还提供一种三维堆叠的无结型梯度掺杂沟道半导体器件结构的制作方法，所述制作方法包括：
如图4所示，首先进行步骤1)，提供一衬底101，于所述衬底101上形成堆叠的若干基体结构层20，所述基体结构层20包括牺牲层201以及位于所述牺牲层201上的沟道层202。
所述衬底101可以为硅衬、碳化硅衬底101、锗硅衬底101等。在本实施例中，所述衬底101为硅衬底101。然后采用如化学气相沉积法等工艺于所述衬底101上重复形成牺牲层201及沟道层202，所述牺牲层201的材料可以为二氧化硅层，所述沟道层202的材料可以为硅。
在本实施例中，所述牺牲层201的厚度范围可以为10～200纳米，如50纳米、100纳米、150纳米等，所述沟道层202的厚度范围可以为10～100纳米，如25纳米、50纳米、75纳米等。
如图5所示，然后进行步骤2)，采用光刻工艺及刻蚀工艺刻蚀所述若干基体结构层20，以在所述衬底101上形成相邻的第一鳍形结构30及第二鳍形结构40，所述第一鳍形结构30的宽度D1大于所述第二鳍形结构40的宽度D2，所述第一鳍形结构30包括交替层叠的若干第一牺牲单元301及若干第一半导体沟道302，所述第二鳍形结构40包括交替层叠的若干第二牺牲单元401及若干第二半导体沟道402。所述第一牺牲单元301及第二牺牲单元401为由所述牺牲层201刻蚀而成，所述第一半导体沟道302及所述第二半导体沟道402为由所述沟道层202刻蚀而成。
如图6所示，接着进行步骤3)，选择性去除所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401，以获得悬空的若干第一半导体沟道302及悬空的若干第二半导体沟道402。
具体地，采用稀释氢氟酸溶液DHF对所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401进行湿法腐蚀，以选择性去除所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401，以获得悬空的若干第一半导体沟道302及悬空的若干第二半导体沟道402。
如图7～图9所示，接着，对所述半导体沟道经过圆角化处理，使得所述半导体沟道具有圆角矩形的截面形状。具体地，包括：a)采用热氧化工艺对所述第一半导体沟道302及第二半导体沟道402进行氧化，形成包围所述第一半导体沟道302及第二半导体沟道402的热氧化层，所述热氧化工艺的氧化温度可以为800℃～1200℃之间，氧化时间可以为5分钟～8小时之间；b)采用稀释氢氟酸溶液DHF对所述热氧化层进行湿法腐蚀，以将其去除，获得具有圆角矩形(或跑道形)的截面形状的第一半导体沟道302及第二半导体沟道402。
如图8所示，对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道305，例如，对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道305包括步骤：
a)采用化学气相沉积工艺CVD或原子层沉积工艺ALD于所述第一半导体沟道302表面沉积硼离子重掺杂的介质层，所述硼离子重掺杂的介质层可以为具有高浓度的硼离子的硼硅玻璃；
b)热处理以驱动所述介质层中的硼离子向所述第一半导体沟道302内扩散，以形成P型半导体沟道305，所述P型半导体沟道305的P型离子掺杂浓度自所述P型半导体沟道305的表面朝中心逐渐减小，其中，所述热处理的温度范围可以介于800℃～1200℃之间，热处理的时间范围可以介于5分钟～8小时之间；优选地，所述P型半导体沟道305的P型离子掺杂浓度自所述P型半导体沟道305的表面相对中心减小的数量级不小于102。
c)湿法腐蚀去除所述介质层，例如，可以采用稀释氟化氢溶液DHF对所述介质层进行湿法腐蚀，以将其去除。
如图9所示，对所述第二半导体沟道进行N型离子掺杂以形成N型半导体沟道405，例如，对所述第二半导体沟道402进行N型离子掺杂以形成N型半导体沟道405，包括步骤：
a)于所述第二半导体沟道402表面沉积磷离子或砷离子重掺杂的介质层，所述磷离子或砷离子重掺杂的介质层可以为具有高浓度磷离子或砷离子的磷硅玻璃；
b)热处理以驱动所述介质层中的磷离子或砷离子向所述第二半导体沟道402内扩散，以形成N型半导体沟道405，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面朝中心逐渐减小，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面朝中心逐渐减小，其中，所述热处理的温度范围可以介于800℃～1200℃之间，热处理的时间范围可以介于5分钟～8小时之间；优选地，所述N型半导体沟道405的N型离子掺杂浓度自所述N型半导体沟道405的表面相对中心减小的数量级不小于102。
c)湿法腐蚀去除所述介质层,例如，可以采用稀释氟化氢溶液DHF对所述介质层进行湿法腐蚀，以将其去除。
本发明通过将P型离子掺杂浓度设计为自所述P型半导体沟道的表面朝中心逐渐减小，N型离子掺杂浓度设计为自所述N型半导体沟道的表面朝中心逐渐减小，可以降低沟道中的不受栅极控制的热载流子的浓度，有效提高栅极对沟道内空穴电荷或电子电荷的控制能力，提高器件性能。
在本实施例中，所述半导体器件结构包括两个自所述衬底101向上堆叠的P型半导体沟道305，以及两个自所述衬底101向上堆叠的N型半导体沟道405，所述P型半导体沟道305用以形成P型场效应晶体管，所述N型半导体沟道405用以形成N型场效应晶体管。
所述P型半导体沟道305的截面宽度可以为所述N型半导体沟道405的截面宽度的1.5～10倍，更优选地，所述P型半导体沟道305的截面宽度为所述N型半导体沟道405的截面宽度的2～4倍。由于P型半导体沟道305中的空穴迁移率通常为N型半导体沟道405中的电子迁移率的三分之一左右，故将所述P型半导体沟道305的截面宽度为所述N型半导体沟道405的截面宽度的2～4倍，可以在保证P型场效应晶体管占用面积较小的情况下，有效提高的P型场效应晶体管的负载能力。
如图10所示，然后进行步骤4)，形成包围所述P型半导体沟道305及N型半导体沟道405的栅介质层303、403。
例如，可以采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)形成包围所述P型半导体沟道305及N型半导体沟道405的栅介质层303、403。所述栅介质层303、403可以为可以是二氧化硅、氧化铝、氮氧硅化合物、碳氧硅化合物或铪基的等高介电常数材料中的一种。
形成所述栅介质层303、403的同时，于所述衬底101表面形成隔离层102，以隔离衬底101与器件的有源区及后续形成的共用电极50，提高器件的性能。
如图11所示，接着进行步骤5)，形成包围所述栅介质层303、403的栅电极层304、404。
例如，可以采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)沉积形成包围所述栅介质层303、403的栅电极层304、404。所述N型场效应晶体管的栅电极层404的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。所述P型场效应晶体管的栅电极层304的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。如图12所示，然后沉积一共用电极，连接所述栅电极层304、404，所述共用电极50的材质包括Al、W及Cu中的一种。
如图13所示，然后进行步骤6)，于所述P型半导体沟道305的两端分别形成P型源区及P型漏区306，以形成无结型梯度掺杂沟道P型场效应晶体管，于所述N型半导体沟道405的两端分别形成N型源区及N型漏区406，以形成无结型梯度掺杂沟道N型场效应晶体管，所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层404与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极层304由所述共用电极50连接，以形成倒相器。
所述P型源区及P型漏区306的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区406的材质包含N型离子掺杂的碳化硅。所述P型源区及P型漏区306的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区306分别包覆于所述P型半导体沟道305的两端，所述N型源区及N型漏区406的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区406分别包覆于所述N型半导体沟道405的两端。本发明通过外延方式形成P型场效应晶体管的P型源区及P型漏区306以及N型场效应晶体管的N型源区及N型漏区406，并采用锗硅作为P型源区及P型漏区306的基体材料以及采用碳化硅作为N型源区及N型漏区406的基体材料，可以有效提高P型源区及P型漏区306的空穴迁移率，同时提高N型源区及N型漏区406的电子迁移率，从而可以有效降低倒相器的导通电阻，提高倒相器的驱动电流。
如上所述，本发明的半导体器件结构及其制作方法，具有以下有益效果：
本发明提出了一种三维堆叠结构的全包围栅无结型梯度掺杂沟道场效应晶体管结构，可以在单位面积下实现器件的多层堆叠，同时有效缩短器件的沟道长度，降低短沟道效应，有效提高器件的集成度，大大提高器件的功率。
本发明通过P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度，通过提高P型半导体沟道的截面面积，以提高空穴的迁移量，从而提高P型场效应晶体管的电流负载能力，降低器件的导通电阻；同时，基于N型沟道的电子迁移率高于P型半导体沟道，将N型半导体沟道的截面宽度设计得较小，可以在保证N型场效应晶体管的电流负载能力的同时，缩小N型半导体沟道的面积，降低其关断所需电压，缩小器件的总面积，提高器件的集成度。
本发明通过外延方式形成P型场效应晶体管的P型源区及P型漏区以及N型场效应晶体管的N型源区及N型漏区，并采用锗硅作为P型源区及P型漏区的基体材料以及采用碳化硅作为N型源区及N型漏区的基体材料，可以有效提高P型源区及P型漏区的空穴迁移率，同时提高N型源区及N型漏区的电子迁移率，从而可以有效降低倒相器的导通电阻，提高倒相器的驱动电流。
本发明通过将P型离子掺杂浓度设计为自所述P型半导体沟道的表面朝中心逐渐减小，N型离子掺杂浓度设计为自所述N型半导体沟道的表面朝中心逐渐减小，可以降低沟道中的不受栅极控制的热载流子的浓度，有效提高栅极对沟道内空穴电荷或电子电荷的控制能力，提高器件性能。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (24)

1.一种半导体器件结构，其特征在于，包括：
衬底；
P型半导体沟道，悬空于所述衬底之上；
N型半导体沟道，悬空于所述衬底之上；
栅介质层，包围于所述P型半导体沟道及所述N型半导体沟道；
栅电极层，包围于所述栅介质层；
P型源区及P型漏区，分别连接于所述P型半导体沟道的两端；以及
N型源区及N型漏区，分别连接于所述N型半导体沟道的两端；
其中，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小，所述P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度。
2.根据权利要求1所述的半导体器件结构，其特征在于：所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心呈线性减小或梯度减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心呈线性减小或梯度减小。
3.根据权利要求1所述的半导体器件结构，其特征在于：所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面相对中心减小的数量级不小于102，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面相对中心减小的数量级不小于102。
4.根据权利要求1所述的半导体器件结构，其特征在于：所述P半导体沟道的材质包含P型离子掺杂的硅，所述N型半导体沟道的材质包含N型离子掺杂的硅。
5.根据权利要求1所述的半导体器件结构，其特征在于：所述P型源区及P型漏区的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区的材质包含N型离子掺杂的碳化硅。
6.根据权利要求1所述的半导体器件结构，其特征在于：所述P型源区及P型漏区的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区分别包覆于所述P型半导体沟道的两端，所述N型源区及N型漏区的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区分别包覆于所述N型半导体沟道的两端。
7.根据权利要求1所述的半导体器件结构，其特征在于：所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的1.5～10倍。
8.根据权利要求7所述的半导体器件结构，其特征在于：所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的2～4倍。
9.根据权利要求1所述的半导体器件结构，其特征在于：所述P型半导体沟道及所述N型半导体沟道均经过圆角化处理而具有圆角矩形的截面形状。
10.根据权利要求1～9任意一项所述的半导体器件结构，其特征在于：包括至少两个自所述衬底向上堆叠的P型半导体沟道及两个自所述衬底向上堆叠的N型半导体沟道，其中，基于所述P型半导体沟道形成无结型梯度掺杂沟道P型场效应晶体管，基于所述N型半导体沟道形成无结型梯度掺杂沟道N型场效应晶体管，且相邻两无结型梯度掺杂沟道N型场效应晶体管之间及相邻两无结型梯度掺杂沟道P型场效应晶体管之间均具有间距，所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极由一共用电极连接，以形成倒相器。
11.根据权利要求10所述的半导体器件结构，其特征在于：所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述共用电极的材质包括Al、W及Cu中的一种。
12.一种半导体器件结构的制作方法，其特征在于，包括步骤：
1)提供一衬底，于所述衬底上形成悬空于所述衬底之上的P型半导体沟道及N型半导体沟道，其中，所述P型半导体沟道的截面宽度大于所述N型半导体沟道的截面宽度，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小；
2)形成包围于所述P型半导体沟道及N型半导体沟道的栅介质层；
3)形成包围于所述栅介质层的栅电极层；
4)于所述P型半导体沟道的两端分别形成P型源区及P型漏区；以及
5)于所述N型半导体沟道的两端分别形成N型源区及N型漏区。
13.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：步骤1)包括：
1-1)提供一衬底，于所述衬底上形成堆叠的若干基体结构层，所述基体结构层包括牺牲层以及位于所述牺牲层上的沟道层；
1-2)刻蚀所述若干基体结构层，以在所述衬底上形成相邻的第一鳍形结构及第二鳍形结构，所述第一鳍形结构包括交替层叠的若干第一牺牲单元及若干第一半导体沟道，所述第二鳍形结构包括交替层叠的若干第二牺牲单元及若干第二半导体沟道，所述第一半导体沟道的截面宽度大于所述第二半导体沟道的截面宽度；
1-3)选择性去除所述第一鳍形结构中的第一牺牲单元及所述第二鳍形结构中的第二牺牲单元，以获得悬空的若干第一半导体沟道及悬空的若干第二半导体沟道；以及
1-4)对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道，对所述第二半导体沟道进行N型离子掺杂以形成N型半导体沟道。
14.根据权利要求13所述的半导体器件结构的制作方法，其特征在于：步骤1-4)对所述第一半导体沟道进行P型离子掺杂以形成P型半导体沟道包括：
a)于所述第一半导体沟道表面沉积硼离子重掺杂的介质层；
b)热处理以驱动所述介质层中的硼离子向所述第一半导体沟道内扩散，以形成P型半导体沟道，所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面朝中心逐渐减小；
c)湿法腐蚀去除所述介质层。
15.根据权利要求13所述的半导体器件结构的制作方法，其特征在于：步骤1-4)对所述第二半导体沟道进行N型离子掺杂以形成N型半导体沟道包括：
a)于所述第二半导体沟道表面沉积磷离子或砷离子重掺杂的介质层；
b)热处理以驱动所述介质层中的磷离子或砷离子向所述第二半导体沟道内扩散，以形成N型半导体沟道，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面朝中心逐渐减小；
c)湿法腐蚀去除所述介质层。
16.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：所述P型半导体沟道的P型离子掺杂浓度自所述P型半导体沟道的表面相对中心减小的数量级不小于102，所述N型半导体沟道的N型离子掺杂浓度自所述N型半导体沟道的表面相对中心减小的数量级不小于102。
17.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：所述P半导体沟道的材质包含P型离子掺杂的硅，所述N型半导体沟道的材质包含N型离子掺杂的硅。
18.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：所述P型源区及P型漏区的材质包含P型离子掺杂的锗硅，所述N型源区及N型漏区的材质包含N型离子掺杂的碳化硅。
19.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：所述P型源区及P型漏区的截面面积大于所述P型沟道的截面面积，且所述P型源区及P型漏区分别包覆于所述P型半导体沟道的两端，所述N型源区及N型漏区的截面面积大于所述N型沟道的截面面积，且所述N型源区及N型漏区分别包覆于所述N型半导体沟道的两端。
20.根据权利要求19所述的半导体器件结构的制作方法，其特征在于：所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的1.5～10倍。
21.根据权利要求20所述的半导体器件结构的制作方法，其特征在于：所述P型半导体沟道的截面宽度为所述N型半导体沟道的截面宽度的2～4倍。
22.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：步骤1)还包括对所述P型半导体沟道及N型半导体沟道进行圆角化处理的步骤，使得所述P型半导体沟道及N型半导体沟道具有圆角矩形的截面形状。
23.根据权利要求12所述的半导体器件结构的制作方法，其特征在于：步骤1)于所述衬底上形成至少两个自所述衬底向上堆叠的P型半导体沟道及两个自所述衬底向上堆叠的N型半导体沟道，且相邻两P型半导体沟道之间及相邻两N型半导体沟道之间均具有间距，步骤4)基于所述P型半导体沟道形成无结型梯度掺杂沟道P型场效应晶体管及步骤5)基于所述N型半导体沟道形成无结型梯度掺杂沟道N型场效应晶体管之后，还包括沉积共用电极的步骤，所述共用电极连接所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层与所述无结型梯度掺杂沟道P型场效应晶体管的栅电极，以形成倒相器。
24.根据权利要求23所述的半导体器件结构的制作方法，其特征在于：所述无结型梯度掺杂沟道N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述无结型梯度掺杂沟道P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种，所述共用电极的材质包括Al、W及Cu中的一种。
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