TWI692102B - 全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法 - Google Patents

全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法 Download PDF

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TWI692102B
TWI692102B TW108127971A TW108127971A TWI692102B TW I692102 B TWI692102 B TW I692102B TW 108127971 A TW108127971 A TW 108127971A TW 108127971 A TW108127971 A TW 108127971A TW I692102 B TWI692102 B TW I692102B
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肖德元
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大陸商芯恩（青島）積體電路有限公司
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Abstract

本發明提供一種全包圍閘梯度摻雜奈米片互補反相器結構，其P型場效電晶體包括P型半導體奈米片通道和完全包圍P型半導體奈米片通道的第一閘介質層、第一閘極層以及設置於通道兩端的源汲區，其N型場效電晶體包括N型半導體奈米片通道、完全包圍N型半導體奈米片通道的第二閘介質層、第二閘極層以及設置於通道兩端的源汲區；並設有共用閘電極將第一閘極層和第二閘極層完全包圍；其中，P型半導體奈米片通道和N型半導體奈米片通道的摻雜濃度由表及裡梯度遞減，且橫向並排設置，P型半導體奈米片通道的寬度大於N型半導體奈米片通道的寬度。本發明的元件結構緊湊，有利於提高元件密度，提升晶片性能，並且結構簡單，製作工藝易於實現。

Description

全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法
本發明涉及半導體元件領域，特別是涉及一種全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法。
FinFET是一種具有垂直“鰭”結構的鰭式場效電晶體。鰭式的三維結構可以形成三個閘極以提高功率和效率。當今的14奈米和10奈米晶片採用帶有這種FinFET的晶片供電，甚至不久前宣佈的7奈米測試晶片也是如此。這些FinFET晶片最近已開始進入伺服器、電腦和設備，並將成為未來幾年的標準。
公開號為US08350298B2的美國專利HYBRID MATERIAL INVERSION MODE GAA CMOSFET公開了一種採用混合材料的全包圍閘CMOS場效電晶體。該電晶體的PMOS通道和NMOS通道的橫截面為跑道形，閘極將PMOS通道和NMOS通道的表面完全包圍。這種全包圍閘（GAA，Gate-All-Around）電晶體結構具備較高的載子遷移率、可避免多晶矽閘耗盡及短通道效應等優點。
通過將矽奈米片層水平堆疊在一起，可以實現5奈米節點的GAA電晶體結構，提供未來應用所需的功率和性能提升。從垂直結構到水平矽層的變化開啟了電晶體上的第四個“閘”，這使得電信號能夠穿過晶片上的其他電晶體並在它們之間傳遞。在這些維度上，它意味著這些信號正穿過一個寬度不大於兩到三條並排DNA鏈寬度的開關。因此，人們非常渴望利用類似這樣的新的性能提升技術，來應對超過5 nm節點的元件所面臨的挑戰。
在京都召開的2017年VLSI技術和電路研討會上宣佈了一種用於5奈米節點晶片的新型電晶體。這種電晶體採用業界一流的工藝來堆疊矽奈米片作為元件結構，將閘極圍繞在電晶體周圍，能夠在指甲大小的晶片上實現300億個開關的規模，這與如今最前沿的10奈米晶片相比將顯著提高功率和性能。
然而，在實際的生產應用中，如何進一步提高元件的密度、功率和性能仍是本領域技術人員亟待解決的技術問題。
鑒於以上所述現有技術，本發明的目的在於提供一種全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法，用於進一步提升元件性能。
為實現上述目的及其他相關目的，本發明提供一種全包圍閘梯度摻雜奈米片互補反相器結構，包括：基板；位於所述基板上的P型場效電晶體和N型場效電晶體，所述P型場效電晶體包括位於所述基板上的P型半導體奈米片通道、完全包圍所述P型半導體奈米片通道的第一閘介質層、完全包圍所述第一閘介質層的第一閘極層以及相對的設置於所述P型半導體奈米片通道兩端的第一源區和第一汲區，所述N型場效電晶體包括位於所述基板上的N型半導體奈米片通道、完全包圍所述N型半導體奈米片通道的第二閘介質層、完全包圍所述第二閘介質層的第二閘極層以及相對的設置於所述N型半導體奈米片通道兩端的第二源區和第二汲區；以及將所述第一閘極層和所述第二閘極層連接在一起的共用閘電極，所述共用閘電極將所述第一閘極層和所述第二閘極層完全包圍；其中，所述P型半導體奈米片通道和所述N型半導體奈米片通道橫向並排設置，且分別具有水平方向的寬度和長度，以及垂直於水平方向的高度，所述P型半導體奈米片通道的長度定義了所述第一源區和所述第一汲區之間的距離，所述N型半導體奈米片通道的長度定義了所述第二源區和所述第二汲區之間的距離，所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度，所述P型半導體奈米片通道和所述N型半導體奈米片通道的摻雜濃度由表面向中心梯度遞減。
可選地，所述第一源極連接電源端V DD，所述第一汲極與所述第二汲極連接在一起作為輸出端V out，所述第二源極接地，所述共用閘電極作為輸入端V in。
可選地，所述P型半導體奈米片通道和所述N型半導體奈米片通道在寬度方向的截面輪廓大致為跑道形，所述跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。
可選地，所述P型半導體奈米片通道採用P型矽奈米片，所述N型半導體奈米片通道採用N型矽奈米片。
可選地，所述P型效應電晶體包括縱向排列的多條所述P型半導體奈米片通道，所述N型場效電晶體包括縱向排列的多條所述N型半導體奈米片通道。
可選地，所述第一源區和所述第一汲區的材料採用P型的SiGe，所述第二源區和所述第二汲區的材料採用N型的SiC。
可選地，在所述第一源區和所述第一汲區與第一閘極層和共用閘電極之間設有介電質層隔離，在所述第二源區和所述第二汲區與第二閘極層和共用閘電極之間也設有介電質層隔離。
可選地，所述P型場效電晶體和所述N型場效電晶體之下設有絕緣埋層與所述基板隔離。
為實現上述目的及其他相關目的，本發明還提供一種全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，包括以下步驟：提供基板；在所述基板上形成犧牲層與半導體奈米片層交錯的堆疊結構；定義至少兩個並排的不同寬度的通道區域，並蝕刻所述堆疊結構得到分別對應所述兩個通道區域的兩組並排的不同寬度的半導體奈米片，去除所述半導體奈米片下方的犧牲層，使所述半導體奈米片周圍裸露並懸於所述基板上；分別對兩組半導體奈米片進行離子摻雜，形成梯度摻雜的P型半導體奈米片通道和梯度摻雜的N型半導體奈米片通道，其中，所述P型半導體奈米片通道和所述N型半導體奈米片通道的摻雜濃度由表面向中心梯度遞減，且所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度；在所述P型半導體奈米片通道上形成完全環繞包圍所述P型半導體奈米片通道的第一閘介質層以及完全包圍所述第一閘介質層的第一閘極層，在所述N型半導體奈米片通道上形成完全環繞包圍所述N型半導體奈米片通道的第二閘介質層以及完全包圍所述第二閘介質層的第二閘極層；形成共用閘電極，所述共用閘電極同時將所述第一閘極層和所述第二閘極層完全包圍；在所述P型半導體奈米片通道的兩端分別形成第一源區和第一汲區，在所述N型半導體奈米片通道的兩端分別形成第二源區和第二汲區。
可選地，所述堆疊結構是在所述基板上磊晶生長形成，所述犧牲層為磊晶生長的SiGe層，所述半導體奈米片層為磊晶生長在所述犧牲層上的Si層。
可選地，所述犧牲層的厚度為10-200nm，所述半導體奈米片層的厚度為10-100nm。
可選地，去除所述半導體奈米片下方的犧牲層之後，利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角。進一步可選地，利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角之後，對所述半導體奈米片進行氫退火。
可選地，形成梯度摻雜的P型半導體奈米片通道包括：在所述半導體奈米片表面沉積重摻雜硼的硼矽玻璃（BSG）層，然後進行退火擴散，再去除所述硼矽玻璃（BSG）層。
可選地，形成梯度摻雜的N型半導體奈米片通道包括：在所述半導體奈米片表面沉積重摻雜磷或砷的磷矽玻璃（PSG）層，然後進行退火擴散，再去除所述磷矽玻璃（PSG）層。
可選地，所述第一源區和所述第一汲區是在所述P型半導體奈米片通道的兩端磊晶生長形成，所述第二源區和所述第二汲區是在所述N型半導體奈米片通道的兩端磊晶生長形成。
可選地，所述第一源區和所述第一汲區的材料為P型的SiGe，所述第二源區和所述第二汲區的材料為N型的SiC。
可選地，在所述基板上形成淺溝槽隔離結構，並在所述基板上形成絕緣埋層。
如上所述，本發明的全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法，具有以下有益效果：本發明利用堆疊矽奈米片層製作了三維元件結構，閘極將通道表面完全包圍，實現了全包圍閘，並且共用閘電極將多個通道同時包圍，使元件結構更為緊密，通過pEFT和nEFT形成互補反相器電路，pEFT與nEFT的通道並排，pEFT的通道寬度大於nEFT的通道寬度，使反相器緊湊且平衡，通道採用梯度摻雜，摻雜濃度由表面向中心梯度遞減，能提高元件關態性能，降低漏電流及功耗，使元件具備更好的性能及進一步按比例縮小的能力。此外，通道截面為跑道形，可增大通道橫截面積，提高元件的驅動電流，而同時又保持元件的電完整性。
相較於現有技術，本發明的元件結構緊湊，有利於提高元件密度，提升晶片性能，並且結構簡單，製作工藝易於實現。
以下通過特定的具體實例說明本發明的實施方式，本領域技術人員可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用，本說明書中的各項細節也可以基於不同觀點與應用，在沒有背離本發明的精神下進行各種修飾或改變。需說明的是，在不衝突的情況下，以下實施例及實施例中的特徵可以相互組合。
需要說明的是，以下實施例中所提供的圖示僅以示意方式說明本發明的基本構想，遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的元件數目、形狀及尺寸繪製，其實際實施時各元件的型態、數量及比例可為一種隨意的改變，且其元件佈局型態也可能更為複雜。
請參閱圖1a和圖1b，本實施例提供一種全包圍閘梯度摻雜奈米片互補反相器結構，其包括：基板100、位於所述基板100上的P型場效電晶體a、N型場效電晶體b和共用閘電極600，其中，圖1a為俯視示意圖，圖1b為圖1a中AA’方向的截面示意圖。
所述基板100可以是常規的體矽基板或其他適合的半導體基板。在所述基板100上設有絕緣埋層200，使之與所述P型場效電晶體a和所述N型場效電晶體b隔離。
所述P型場效電晶體a和所述N型場效電晶體b均為全包圍閘的非平面電晶體。它們的結構基本相同。所述P型場效電晶體a包括位於所述基板100上的P型半導體奈米片通道301、完全包圍所述P型半導體奈米片通道301的第一閘介質層401、完全包圍所述第一閘介質層401的第一閘極層501以及相對的設置於所述P型半導體奈米片通道301兩端的第一源區S1和第一汲區D1。所述N型場效電晶體b包括位於所述基板100上的N型半導體奈米片通道302、完全包圍所述N型半導體奈米片通道302的第二閘介質層402、完全包圍所述第二閘介質層402的第二閘極層502以及相對的設置於所述N型半導體奈米片通道302兩端的第二源區S2和第二汲區D2。
所述共用閘電極600完全包圍第一閘極層501和第二閘極層502，使它們連接在一起。
其中，所述P型半導體奈米片通道301和所述N型半導體奈米片通道302橫向並排設置。所述P型半導體奈米片通道301具有水平方向的寬度w1和長度l1，以及垂直於水平方向的高度h1，長度l1定義了所述第一源區S1和所述第一汲區D1之間的距離。所述N型半導體奈米片通道302具有水平方向的寬度w2和長度l2，以及垂直於水平方向的高度h2，長度l2定義了所述第二源區S2和所述第二汲區D2之間的距離。所述P型半導體奈米片通道301的寬度w2大於所述N型半導體奈米片通道302的寬度w2。它們的高度h1和h2基本相同，可以為10-100nm。它們在寬度方向上的截面輪廓都大致為跑道形，如圖1b中所示，所述跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。這種截面形狀可增大通道橫截面積，提高元件的驅動電流，而同時又保持元件的電完整性。由於pFET的通道載子電洞，其遷移率比nFET的通道載子電子遷移率小很多，因此，本發明設計的pEFT通道寬度比nEFT更寬，使組成的CMOS更為平衡。
另外，在本發明中，所述P型半導體奈米片通道和所述N型半導體奈米片通道的摻雜濃度由表面向中心梯度遞減。當元件需要關斷時，由於通道中心位置遠離表面，電場較弱，載子不容易被耗盡。通道的摻雜濃度由表面至中心梯度遞減，能提高元件關態性能，降低漏電流及功耗。
具體地，所述P型半導體奈米片通道301可以採用梯度摻雜的P型矽奈米片。所述N型半導體奈米片通道302可以採用梯度摻雜的N型矽奈米片。pEFT的源汲區，即第一源區S1和第一汲區D1，可以採用磊晶生長的P型SiGe材料，nEFT的源汲區，即第二源區S2和第二汲區D2的材料可以採用磊晶生長的N型SiC材料。其中，pEFT的源汲區採用SiGe可對pFET的通道產生圧應力，以提高載子電洞遷移率；nEFT的源汲區採用SiC可對nFET的通道產生張應力，以提高載子電子遷移率。在所述第一源區S1和所述第一汲區D1與第一閘極層501和共用閘電極600之間設有介電質層700作為側牆隔離（spacer），在所述第二源區S2和所述第二汲區D2與第二閘極層502和共用閘電極600之間也設有介電質層700作為側牆隔離（spacer）。
本實施例的全包圍閘梯度摻雜奈米片互補反相器結構可採用如圖2所示的互補反相器電路，其中，所述P型場效電晶體a即為pEFT ，所述N型場效電晶體b即為nEFT，第一源極S1連接電源端V DD，所述第一汲極D1與所述第二汲極D2連接在一起作為輸出端V out，所述第二源極S2接地，所述共用閘電極作為輸入端V in。
此外，作為本發明的優選方案，所述P型效應電晶體a可以包括縱向排列的多條所述P型半導體奈米片通道301；所述N型場效電晶體b可以包括縱向排列的多條所述N型半導體奈米片通道302，以提高元件性能。本實施例中，每個電晶體可以對應上下兩條通道，而在本發明的其他實施例中，每個場效電晶體還可以對應更多數量的通道。
下面結合附圖進一步詳細說明本實施例提供的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法。
請參閱圖3a-3n，本實施例提供一種全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，包括S1-S7等步驟。
S1提供基板100。所述基板100可以是常規的體矽基板或其他適合的半導體基板。
S2在所述基板100上形成犧牲層310與半導體奈米片層320交錯的堆疊結構，如圖3a所示。
具體地，所述堆疊結構可以在所述基板100上磊晶生長形成。例如，可以在所述基板100上磊晶生長SiGe層作為所述犧牲層310，再在所述犧牲層310上磊晶生長Si層作為所述半導體奈米片層320。其中，所述犧牲層310的厚度可以為10-200nm，所述半導體奈米片層320的厚度可以為10-100nm。本實施例中，堆疊結構中的犧牲層310和半導體奈米片層320為兩層，在其他實施例中，它們的層數可以更多，以提供更多數量的通道。
S3定義至少兩個並排的不同寬度的通道區域，並蝕刻所述堆疊結構得到對應所述兩個通道區域的兩組並排的不同寬度的半導體奈米片300，去除所述半導體奈米片300下方的犧牲層310，使所述半導體奈米片300周圍裸露並懸於所述基板100上。
如圖3b所示，可以先利用光刻和蝕刻工藝形成淺溝槽隔離結構（STI）所需的溝槽，同時可定義出至少兩個並排的通道區域，分別對應P型場效電晶體a和N型場效電晶體b的第一通道區域330a和第二通道區域330b。所述溝槽從所述堆疊結構表面深入至基板100中。蝕刻所述溝槽的同時，即可得到分別對應第一通道區域330a和第二通道區域330b的兩組並排的半導體奈米片300。
然後，如圖3c所示，在溝槽中填入隔離介質210，再如圖3d所示採用化學機械研磨（CMP）使所得結構表面平坦化，避免在半導體奈米片300上有介質材料殘留。隨後，如圖3e所示，利用光刻和蝕刻工藝去除第一通道區域330a和第二通道區域330b周圍的隔離介質材料，保留填入基板100中的隔離介質210。
接著，可以採用選擇性橫向蝕刻去除半導體奈米片300下方的犧牲層310，如圖3f所示，使所述半導體奈米片300周圍裸露並懸於所述基板100上。本實施例中，去除SiGe材質的犧牲層310，可以採用包含HF、HNO 3、H 2O的蝕刻液。
為了獲得跑道形的截面輪廓，去除犧牲層310後，還可以利用先氧化再濕式蝕刻的方法處理所述半導體奈米片300的拐角以形成圓角。如圖3g所示，先氧化半導體奈米片300，再採用稀氟氫酸(DHF)蝕刻去除氧化層，從而得到截面大致為跑道形的半導體奈米片300。然後在高於800℃-1200℃的溫度下進行氫退火，退火時間可為5分鐘到8小時。進行氫退火可使蝕刻處理後的半導體奈米片300表面更加光滑、緻密。
S4分別對兩組半導體奈米片300進行離子摻雜，形成梯度摻雜的P型半導體奈米片通道301和梯度摻雜的N型半導體奈米片通道302，使所述P型半導體奈米片通道301和所述N型半導體奈米片通道302的摻雜濃度由表面向中心梯度遞減。其中，寬度較大的一組半導體奈米片300用於形成P型半導體奈米片通道301，寬度較小的一組半導體奈米片300用於形成N型半導體奈米片通道302。
具體地，如圖3h所示，可以利用化學氣相沉積（CVD）或原子層沉積（ALD）工藝先在所述半導體奈米片300上沉積重摻雜硼的硼矽玻璃（BSG）層，然後去除用於形成N型半導體奈米片通道302的半導體奈米片300上的硼矽玻璃（BSG）層，再進行高溫退火使硼離子擴散入半導體奈米片300內，退火溫度可以為800℃-1200℃，退火時間可為5分鐘到8小時，隨後去除硼矽玻璃（BSG）層，得到梯度摻雜的P型半導體奈米片通道301。在P型半導體奈米片通道301的表面硼離子的摻雜濃度最高，並從表面梯度遞減至中心區域。去除硼矽玻璃（BSG）層可利用稀氟氫酸(DHF)濕式蝕刻工藝。接著，如圖3i所示，可以利用化學氣相沉積（CVD）或原子層沉積（ALD）工藝在另一組半導體奈米片300上沉積重摻雜磷或砷的磷矽玻璃（PSG）層，然後去除P型半導體奈米片通道301上的磷矽玻璃（PSG）層，再進行高溫退火使磷或砷離子擴散入半導體奈米片300內，退火溫度可以為800℃-1200℃，退火時間可為5分鐘到8小時，隨後去除磷矽玻璃（PSG）層，得到梯度摻雜的N型半導體奈米片通道302。在N型半導體奈米片通道302的表面磷或砷離子的摻雜濃度最高，並從表面梯度遞減至中心區域。去除磷矽玻璃（PSG）層可利用稀氟氫酸(DHF)濕式蝕刻工藝。本實施例中，先形成梯度摻雜的P型半導體奈米片通道301，再形成梯度摻雜的N型半導體奈米片通道302，而在本發明的其他實施例中，也可以先形成梯度摻雜的N型半導體奈米片通道302，再形成梯度摻雜的P型半導體奈米片通道301。
S5在所述P型半導體奈米片通道301上形成完全環繞包圍所述P型半導體奈米片通道301的第一閘介質層401以及完全包圍所述第一閘介質層401的第一閘極層501，在所述N型半導體奈米片通道302上形成完全環繞包圍所述N型半導體奈米片通道302的第二閘介質層402以及完全包圍所述第二閘介質層402的第二閘極層502。
如圖3j所示，可以採用化學氣相沉積（CVD）或原子層沉積（ALD）工藝沉積高介電常數（High-k）電介質作為第一閘介質層401和第二閘介質層402。形成閘介質層的同時，也在暴露的基板100表面形成了絕緣埋層200。然後，如圖3k所示，可以利用化學氣相沉積（CVD）或原子層沉積（ALD）工藝沉積閘極材料，在第一閘介質層401和第二閘介質層402上分別形成第一閘極層501和第二閘極層502。具體地，可以先在第一閘介質層401上形成第一閘極層501，並去除沉積在第二閘介質層402上的閘極材料，然後再在第二閘介質層402上形成第二閘極層502，並去除第一閘極層501上多餘的閘極材料。即，可以先形成第一閘極層501，再形成第二閘極層502。形成第一閘極層501的材料可以包括TiN、TaN、TiAl、Ti或其他適合的閘極材料，形成第二閘極層502的材料可以包括TiN、TaN、TiAl、Ti或其他適合的閘極材料。
S6形成共用閘電極600，所述共用閘電極600同時將第一閘極層501和第二閘極層502完全包圍，使它們連接在一起，如圖3l所示。形成共用閘電極600的材料可以包括Al、W、Cu等導電材料。
S7在所述P型半導體奈米片通道301的兩端分別形成第一源區S1和第一汲區D1，在所述N型半導體奈米片通道302的兩端分別形成第二源區S2和第二汲區D2，完成P型效應電晶體和N型效應電晶體的製作。
具體地，可以在所述P型半導體奈米片通道301的兩端磊晶生長P型的SiGe，作為所述第一源區S1和所述第一汲區D1。在所述N型半導體奈米片通道302的兩端磊晶生長N型的SiC作為所述第二源區S2和所述第二汲區D2。圖3m為形成源汲區後元件側面的示意圖。
最後還可以根據圖2所示的互補反相器電路形成完整的反相器，包括引出源極、汲極等步驟。由於pEFT和nEFT的通道橫向並排設置，使兩端的源極汲極更加便於連接和引出，也使得元件更為緊湊，易於積體化。
綜上所述，本發明利用堆疊矽奈米片層製作了三維元件結構，閘極將通道表面完全包圍，實現了全包圍閘，並且共用閘電極將多個通道同時包圍，使元件結構更為緊密，通過pEFT和nEFT形成互補反相器電路，pEFT與nEFT的通道並排，pEFT的通道寬度大於nEFT的通道寬度，使反相器緊湊且平衡，通道採用梯度摻雜，摻雜濃度由表面向中心梯度遞減，能提高元件關態性能，降低漏電流及功耗，通道截面為跑道形，可增大通道橫截面積，提高元件的驅動電流，而同時又保持元件的電完整性，使元件具備更好的性能及進一步按比例縮小的能力。
相較於現有技術，本發明的元件結構緊湊，有利於提高元件密度，提升晶片性能，並且結構簡單，製作工藝易於實現。所以，本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。
上述實施例僅例示性說明本發明的原理及其功效，而非用於限制本發明。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下，對上述實施例進行修飾或改變。因此，舉凡所屬技術領域中具有通常知識者在未脫離本發明所揭示的精神與技術思想下所完成的一切等效修飾或改變，仍應由本發明的權利要求所涵蓋。
Figure 108127971-A0305-0001
圖1a-1b顯示為本發明實施例提供的全包圍閘梯度摻雜奈米片互補反相器結構的示意圖，其中，圖1a為俯視示意圖，圖1b為圖1a中AA’方向的截面示意圖。
圖2顯示為本發明實施例提供的全包圍閘梯度摻雜奈米片互補反相器的電路示意圖。
圖3a-3m顯示為本發明實施例提供的全包圍閘梯度摻雜奈米片互補反相器結構製造方法的流程示意圖。
100:基板
200:絕緣埋層
a:P型場效電晶體
b:N型場效電晶體
301:P型半導體奈米片通道
302:N型半導體奈米片通道
401:第一閘介質層
402:第二閘介質層
501:第一閘極層
502:第二閘極層
600:共用閘電極
w1、w2:寬度
h1、h2:高度

Claims (17)

  1. 一種全包圍閘梯度摻雜奈米片互補反相器結構，包括：基板；位於該基板上的P型場效電晶體和N型場效電晶體，該P型場效電晶體包括位於該基板上的P型半導體奈米片通道、完全包圍該P型半導體奈米片通道的第一閘介質層、完全包圍該第一閘介質層的第一閘極層以及相對的設置於該P型半導體奈米片通道兩端的第一源區和第一汲區，該N型場效電晶體包括位於該基板上的N型半導體奈米片通道、完全包圍該N型半導體奈米片通道的第二閘介質層、完全包圍該第二閘介質層的第二閘極層以及相對的設置於該N型半導體奈米片通道兩端的第二源區和第二汲區；以及將該第一閘極層和該第二閘極層連接在一起的共用閘電極，該共用閘電極將該第一閘極層和該第二閘極層完全包圍；其中，該P型半導體奈米片通道和該N型半導體奈米片通道橫向並排設置，且分別具有水平方向的寬度和長度，以及垂直於水平方向的高度，該P型半導體奈米片通道的長度定義了該第一源區和該第一汲區之間的距離，該N型半導體奈米片通道的長度定義了該第二源區和該第二汲區之間的距離，該P型半導體奈米片通道的寬度大於該N型半導體奈米片通道的寬度，該P型半導體奈米片通道和該N型半導體奈米片通道的摻雜濃度由表面向中心梯度遞減，且其中：該P型效應電晶體包括縱向排列的多條該P型半導體奈米片通道，該N型場效電晶體包括縱向排列的多條該N型半導體奈米片通道。
  2. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相器結構，其中：該第一源極連接電源端，該第一汲極與該第二汲極連接在一起作為輸出端，該第二源極接地，該共用閘電極作為輸入端。
  3. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相 器結構，其中：該P型半導體奈米片通道和該N型半導體奈米片通道在寬度方向的截面輪廓大致為跑道形，該跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。
  4. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相器結構，其中：該P型半導體奈米片通道採用P型矽奈米片，該N型半導體奈米片通道採用N型矽奈米片。
  5. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相器結構，其中：該第一源區和該第一汲區的材料採用P型的SiGe，該第二源區和該第二汲區的材料採用N型的SiC。
  6. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相器結構，其中：在該第一源區和該第一汲區與第一閘極層和共用閘電極之間設有介電質層隔離，在該第二源區和該第二汲區與第二閘極層和共用閘電極之間也設有介電質層隔離。
  7. 如申請專利範圍第1項所述的全包圍閘梯度摻雜奈米片互補反相器結構，其中：該P型場效電晶體和該N型場效電晶體之下設有絕緣埋層與該基板隔離。
  8. 一種全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，包括以下步驟：提供基板； 在該基板上形成犧牲層與半導體奈米片層交錯的堆疊結構；定義至少兩個並排的不同寬度的通道區域，並蝕刻該堆疊結構得到分別對應該兩個通道區域的兩組並排的不同寬度的半導體奈米片，去除該半導體奈米片下方的犧牲層，使該半導體奈米片周圍裸露並懸於該基板上；分別對兩組半導體奈米片進行離子摻雜，形成梯度摻雜的P型半導體奈米片通道和梯度摻雜的N型半導體奈米片通道，其中，該P型半導體奈米片通道和該N型半導體奈米片通道的摻雜濃度由表面向中心梯度遞減，且該P型半導體奈米片通道的寬度大於該N型半導體奈米片通道的寬度；在該P型半導體奈米片通道上形成完全環繞包圍該P型半導體奈米片通道的第一閘介質層以及完全包圍該第一閘介質層的第一閘極層，在該N型半導體奈米片通道上形成完全環繞包圍該N型半導體奈米片通道的第二閘介質層以及完全包圍該第二閘介質層的第二閘極層；形成共用閘電極，該共用閘電極同時將該第一閘極層和該第二閘極層完全包圍；在該P型半導體奈米片通道的兩端分別形成第一源區和第一汲區，在該N型半導體奈米片通道的兩端分別形成第二源區和第二汲區。
  9. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：該堆疊結構是在該基板上磊晶生長形成，該犧牲層為磊晶生長的SiGe層，該半導體奈米片層為磊晶生長在該犧牲層上的Si層。
  10. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：該犧牲層的厚度為10-200nm，該半導體奈米片層的厚度為10-100nm。
  11. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反 相器結構的製造方法，其中：去除該半導體奈米片下方的犧牲層之後，利用先氧化再濕式蝕刻的方法使該半導體奈米片的拐角變為圓角。
  12. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：利用先氧化再濕式蝕刻的方法使該半導體奈米片的拐角變為圓角之後，對該半導體奈米片進行氫退火。
  13. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中，形成梯度摻雜的P型半導體奈米片通道包括：在該半導體奈米片表面沉積重摻雜硼的硼矽玻璃層，然後進行退火擴散，再去除該硼矽玻璃層。
  14. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中，形成梯度摻雜的N型半導體奈米片通道包括：在該半導體奈米片表面沉積重摻雜磷或砷的磷矽玻璃層，然後進行退火擴散，再去除該磷矽玻璃層。
  15. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：該第一源區和該第一汲區是在該P型半導體奈米片通道的兩端磊晶生長形成，該第二源區和該第二汲區是在該N型半導體奈米片通道的兩端磊晶生長形成。
  16. 如申請專利範圍第9項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：該第一源區和該第一汲區的材料為P型的SiGe，該第二源區和該第二汲區的材料為N型的SiC。
  17. 如申請專利範圍第8項所述的全包圍閘梯度摻雜奈米片互補反相器結構的製造方法，其中：在該基板上形成淺溝槽隔離結構，並在該基板上形成絕緣埋層。
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