CN110970421A - 全包围栅梯度掺杂纳米片互补反相器结构及其制造方法 - Google Patents

全包围栅梯度掺杂纳米片互补反相器结构及其制造方法 Download PDF

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CN110970421A
CN110970421A CN201811134875.5A CN201811134875A CN110970421A CN 110970421 A CN110970421 A CN 110970421A CN 201811134875 A CN201811134875 A CN 201811134875A CN 110970421 A CN110970421 A CN 110970421A
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肖德元
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SiEn Qingdao Integrated Circuits Co Ltd
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Abstract

本发明提供一种全包围栅梯度掺杂纳米片互补反相器结构，其P型场效应晶体管包括P型半导体纳米片沟道和完全包围P型半导体纳米片沟道的第一栅介质层、第一栅极层以及设置于沟道两端的源漏区，其N型场效应晶体管包括N型半导体纳米片沟道、完全包围N型半导体纳米片沟道的第二栅介质层、第二栅极层以及设置于沟道两端的源漏区；并设有共用栅电极将第一栅极层和第二栅极层完全包围；其中，P型半导体纳米片沟道和N型半导体纳米片沟道的掺杂浓度由表及里梯度递减，且横向并排设置，P型半导体纳米片沟道的宽度大于N型半导体纳米片沟道的宽度。本发明的器件结构紧凑，有利于提高器件密度，提升芯片性能，并且结构简单，制作工艺易于实现。

Description

全包围栅梯度掺杂纳米片互补反相器结构及其制造方法
技术领域
本发明涉及半导体器件领域，特别是涉及一种全包围栅梯度掺杂纳米片互补反相器结构及其制造方法。
背景技术
FinFET是一种具有垂直“鳍”结构的鳍式场效应晶体管。鳍式的三维结构可以形成三个栅极以提高功率和效率。当今的14纳米和10纳米芯片采用带有这种FinFET的芯片供电，甚至不久前宣布的7纳米测试芯片也是如此。这些FinFET芯片最近已开始进入服务器、计算机和设备，并将成为未来几年的标准。
公开号为US08350298B2的美国专利HYBRID MATERIAL INVERSION MODE GAACMOSFET公开了一种采用混合材料的全包围栅CMOS场效应晶体管。该晶体管的PMOS沟道和NMOS沟道的横截面为跑道形，栅极将PMOS沟道和NMOS沟道的表面完全包围。这种全包围栅(GAA，Gate-All-Around)晶体管结构具备较高的载流子迁移率、可避免多晶硅栅耗尽及短沟道效应等优点。
通过将硅纳米片层水平堆叠在一起，可以实现5纳米节点的GAA晶体管结构，提供未来应用所需的功率和性能提升。从垂直结构到水平硅层的变化开启了晶体管上的第四个“栅”，这使得电信号能够穿过芯片上的其他晶体管并在它们之间传递。在这些维度上，它意味着这些信号正穿过一个宽度不大于两到三条并排DNA链宽度的开关。因此，人们非常渴望利用类似这样的新的性能提升技术，来应对超过5nm节点的器件所面临的挑战。
在京都召开的2017年VLSI技术和电路研讨会上宣布了一种用于5纳米节点芯片的新型晶体管。这种晶体管采用业界一流的工艺来堆叠硅纳米片作为器件结构，将栅极围绕在晶体管周围，能够在指甲大小的芯片上实现300亿个开关的规模，这与如今最前沿的10纳米芯片相比将显著提高功率和性能。
然而，在实际的生产应用中，如何进一步提高器件的密度、功率和性能仍是本领域技术人员亟待解决的技术问题。
发明内容
鉴于以上所述现有技术，本发明的目的在于提供一种全包围栅梯度掺杂纳米片互补反相器结构及其制造方法，用于进一步提升器件性能。
为实现上述目的及其他相关目的，本发明提供一种全包围栅梯度掺杂纳米片互补反相器结构，包括：
衬底；
位于所述衬底上的P型场效应晶体管和N型场效应晶体管，所述P型场效应晶体管包括位于所述衬底上的P型半导体纳米片沟道、完全包围所述P型半导体纳米片沟道的第一栅介质层、完全包围所述第一栅介质层的第一栅极层以及相对的设置于所述P型半导体纳米片沟道两端的第一源区和第一漏区，所述N型场效应晶体管包括位于所述衬底上的N型半导体纳米片沟道、完全包围所述N型半导体纳米片沟道的第二栅介质层、完全包围所述第二栅介质层的第二栅极层以及相对的设置于所述N型半导体纳米片沟道两端的第二源区和第二漏区；以及
将所述第一栅极层和所述第二栅极层连接在一起的共用栅电极，所述共用栅电极将所述第一栅极层和所述第二栅极层完全包围；
其中，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道横向并排设置，且分别具有水平方向的宽度和长度，以及垂直于水平方向的高度，所述P型半导体纳米片沟道的长度定义了所述第一源区和所述第一漏区之间的距离，所述N型半导体纳米片沟道的长度定义了所述第二源区和所述第二漏区之间的距离，所述P型半导体纳米片沟道的宽度大于所述N型半导体纳米片沟道的宽度，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道的掺杂浓度由表面向中心梯度递减。
可选地，所述第一源极连接电源端VDD，所述第一漏极与所述第二漏极连接在一起作为输出端Vout，所述第二源极接地，所述共用栅电极作为输入端Vin。
可选地，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道在宽度方向的截面轮廓大致为跑道形，所述跑道形由左右两端的半圆及中部的与左右两端半圆过渡连接的矩形共同构成。
可选地，所述P型半导体纳米片沟道采用P型硅纳米片，所述N型半导体纳米片沟道采用N型硅纳米片。
可选地，所述P型效应晶体管包括纵向排列的多条所述P型半导体纳米片沟道，所述N型场效应晶体管包括纵向排列的多条所述N型半导体纳米片沟道。
可选地，所述第一源区和所述第一漏区的材料采用P型的SiGe，所述第二源区和所述第二漏区的材料采用N型的SiC。
可选地，在所述第一源区和所述第一漏区与第一栅极层和共用栅电极之间设有电介质层隔离，在所述第二源区和所述第二漏区与第二栅极层和共用栅电极之间也设有电介质层隔离。
可选地，所述P型场效应晶体管和所述N型场效应晶体管之下设有绝缘埋层与所述衬底隔离。
为实现上述目的及其他相关目的，本发明还提供一种全包围栅梯度掺杂纳米片互补反相器结构的制造方法，包括以下步骤：
提供衬底；
在所述衬底上形成牺牲层与半导体纳米片层交错的堆叠结构；
定义至少两个并排的不同宽度的沟道区域，并刻蚀所述堆叠结构得到分别对应所述两个沟道区域的两组并排的不同宽度的半导体纳米片，去除所述半导体纳米片下方的牺牲层，使所述半导体纳米片周围裸露并悬于所述衬底上；
分别对两组半导体纳米片进行离子掺杂，形成梯度掺杂的P型半导体纳米片沟道和梯度掺杂的N型半导体纳米片沟道，其中，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道的掺杂浓度由表面向中心梯度递减，且所述P型半导体纳米片沟道的宽度大于所述N型半导体纳米片沟道的宽度；
在所述P型半导体纳米片沟道上形成完全环绕包围所述P型半导体纳米片沟道的第一栅介质层以及完全包围所述第一栅介质层的第一栅极层，在所述N型半导体纳米片沟道上形成完全环绕包围所述N型半导体纳米片沟道的第二栅介质层以及完全包围所述第二栅介质层的第二栅极层；
形成共用栅电极，所述共用栅电极同时将所述第一栅极层和所述第二栅极层完全包围；
在所述P型半导体纳米片沟道的两端分别形成第一源区和第一漏区，在所述N型半导体纳米片沟道的两端分别形成第二源区和第二漏区。
可选地，所述堆叠结构是在所述衬底上外延生长形成，所述牺牲层为外延生长的SiGe层，所述半导体纳米片层为外延生长在所述牺牲层上的Si层。
可选地，所述牺牲层的厚度为10-200nm，所述半导体纳米片层的厚度为10-100nm。
可选地，去除所述半导体纳米片下方的牺牲层之后，利用先氧化再湿法腐蚀的方法使所述半导体纳米片的拐角变为圆角。进一步可选地，利用先氧化再湿法腐蚀的方法使所述半导体纳米片的拐角变为圆角之后，对所述半导体纳米片进行氢退火。
可选地，形成梯度掺杂的P型半导体纳米片沟道包括：在所述半导体纳米片表面沉积重掺杂硼的硼硅玻璃(BSG)层，然后进行退火扩散，再去除所述硼硅玻璃(BSG)层。
可选地，形成梯度掺杂的N型半导体纳米片沟道包括：在所述半导体纳米片表面沉积重掺杂磷或砷的磷硅玻璃(PSG)层，然后进行退火扩散，再去除所述磷硅玻璃(PSG)层。
可选地，所述第一源区和所述第一漏区是在所述P型半导体纳米片沟道的两端外延生长形成，所述第二源区和所述第二漏区是在所述N型半导体纳米片沟道的两端外延生长形成。
可选地，所述第一源区和所述第一漏区的材料为P型的SiGe，所述第二源区和所述第二漏区的材料为N型的SiC。
可选地，在所述衬底上形成浅沟槽隔离结构，并在所述衬底上形成绝缘埋层。
如上所述，本发明的全包围栅梯度掺杂纳米片互补反相器结构及其制造方法，具有以下有益效果：
本发明利用堆叠硅纳米片层制作了三维器件结构，栅极将沟道表面完全包围，实现了全包围栅，并且共用栅电极将多个沟道同时包围，使器件结构更为紧密，通过pEFT和nEFT形成互补反相器电路，pEFT与nEFT的沟道并排，pEFT的沟道宽度大于nEFT的沟道宽度，使反相器紧凑且平衡，沟道采用梯度掺杂，掺杂浓度由表面向中心梯度递减，能提高器件关态性能，降低漏电流及功耗，使器件具备更好的性能及进一步按比例缩小的能力。此外，沟道截面为跑道形，可增大沟道横截面积，提高器件的驱动电流，而同时又保持器件的电完整性。
相较于现有技术，本发明的器件结构紧凑，有利于提高器件密度，提升芯片性能，并且结构简单，制作工艺易于实现。
附图说明
图1a-1b显示为本发明实施例提供的全包围栅梯度掺杂纳米片互补反相器结构的示意图，其中，图1a为俯视示意图，图1b为图1a中AA’方向的截面示意图。
图2显示为本发明实施例提供的全包围栅梯度掺杂纳米片互补反相器的电路示意图。
图3a-3m显示为本发明实施例提供的全包围栅梯度掺杂纳米片互补反相器结构制造方法的流程示意图。
元件标号说明
100 衬底
200 绝缘埋层
a P型场效应晶体管
b N型场效应晶体管
301 P型半导体纳米片沟道
302 N型半导体纳米片沟道
401 第一栅介质层
402 第二栅介质层
501 第一栅极层
502 第二栅极层
600 共用栅电极
S1 第一源区
D1 第一漏区
S2 第二源区
D2 第二漏区
700 电介质层
310 牺牲层
320 半导体纳米片层
330a 第一沟道区域
330b 第二沟道区域
210 隔离介质
S1-S7 步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1a和图1b，本实施例提供一种全包围栅梯度掺杂纳米片互补反相器结构，其包括：衬底100、位于所述衬底100上的P型场效应晶体管a、N型场效应晶体管b和共用栅电极600，其中，图1a为俯视示意图，图1b为图1a中AA’方向的截面示意图。
所述衬底100可以是常规的体硅衬底或其他适合的半导体衬底。在所述衬底100上设有绝缘埋层200，使之与所述P型场效应晶体管a和所述N型场效应晶体管b隔离。
所述P型场效应晶体管a和所述N型场效应晶体管b均为全包围栅的非平面晶体管。它们的结构基本相同。所述P型场效应晶体管a包括位于所述衬底100上的P型半导体纳米片沟道301、完全包围所述P型半导体纳米片沟道301的第一栅介质层401、完全包围所述第一栅介质层401的第一栅极层501以及相对的设置于所述P型半导体纳米片沟道301两端的第一源区S1和第一漏区D1。所述N型场效应晶体管b包括位于所述衬底100上的N型半导体纳米片沟道302、完全包围所述N型半导体纳米片沟道302的第二栅介质层402、完全包围所述第二栅介质层402的第二栅极层502以及相对的设置于所述N型半导体纳米片沟道302两端的第二源区S2和第二漏区D2。
所述共用栅电极600完全包围第一栅极层501和第二栅极层502，使它们连接在一起。
其中，所述P型半导体纳米片沟道301和所述N型半导体纳米片沟道302横向并排设置。所述P型半导体纳米片沟道301具有水平方向的宽度w1和长度l1，以及垂直于水平方向的高度h1，长度l1定义了所述第一源区S1和所述第一漏区D1之间的距离。所述N型半导体纳米片沟道302具有水平方向的宽度w2和长度l2，以及垂直于水平方向的高度h2，长度l2定义了所述第二源区S2和所述第二漏区D2之间的距离。所述P型半导体纳米片沟道301的宽度w2大于所述N型半导体纳米片沟道302的宽度w2。它们的高度h1和h2基本相同，可以为10-100nm。它们在宽度方向上的截面轮廓都大致为跑道形，如图1b中所示，所述跑道形由左右两端的半圆及中部的与左右两端半圆过渡连接的矩形共同构成。这种截面形状可增大沟道横截面积，提高器件的驱动电流，而同时又保持器件的电完整性。由于pFET的沟道载流子空穴，其迁移率比nFET的沟道载流子电子迁移率小很多，因此，本发明设计的pEFT沟道宽度比nEFT更宽，使组成的CMOS更为平衡。
另外，在本发明中，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道的掺杂浓度由表面向中心梯度递减。当器件需要关断时，由于沟道中心位置远离表面，电场较弱，载流子不容易被耗尽。沟道的掺杂浓度由表面至中心梯度递减，能提高器件关态性能，降低漏电流及功耗。
具体地，所述P型半导体纳米片沟道301可以采用梯度掺杂的P型硅纳米片。所述N型半导体纳米片沟道302可以采用梯度掺杂的N型硅纳米片。pEFT的源漏区，即第一源区S1和第一漏区D1，可以采用外延生长的P型SiGe材料，nEFT的源漏区，即第二源区S2和第二漏区D2的材料可以采用外延生长的N型SiC材料。其中，pEFT的源漏区采用SiGe可对pFET的沟道产生圧应力，以提高载流子空穴迁移率；nEFT的源漏区采用SiC可对nFET的沟道产生张应力，以提高载流子电子迁移率。在所述第一源区S1和所述第一漏区D1与第一栅极层501和共用栅电极600之间设有电介质层700作为侧墙隔离(spacer)，在所述第二源区S2和所述第二漏区D2与第二栅极层502和共用栅电极600之间也设有电介质层700作为侧墙隔离(spacer)。
本实施例的全包围栅梯度掺杂纳米片互补反相器结构可采用如图2所示的互补反相器电路，其中，所述P型场效应晶体管a即为pEFT，所述N型场效应晶体管b即为nEFT，第一源极S1连接电源端VDD，所述第一漏极D1与所述第二漏极D2连接在一起作为输出端Vout，所述第二源极S2接地，所述共用栅电极作为输入端Vin。
此外，作为本发明的优选方案，所述P型效应晶体管a可以包括纵向排列的多条所述P型半导体纳米片沟道301；所述N型场效应晶体管b可以包括纵向排列的多条所述N型半导体纳米片沟道302，以提高器件性能。本实施例中，每个晶体管可以对应上下两条沟道，而在本发明的其他实施例中，每个场效应晶体管还可以对应更多数量的沟道。
下面结合附图进一步详细说明本实施例提供的全包围栅梯度掺杂纳米片互补反相器结构的制造方法。
请参阅图3a-3m，本实施例提供一种全包围栅梯度掺杂纳米片互补反相器结构的制造方法，包括S1-S7等步骤。
S1提供衬底100。所述衬底100可以是常规的体硅衬底或其他适合的半导体衬底。
S2在所述衬底100上形成牺牲层310与半导体纳米片层320交错的堆叠结构，如图3a所示。
具体地，所述堆叠结构可以在所述衬底100上外延生长形成。例如，可以在所述衬底100上外延生长SiGe层作为所述牺牲层310，再在所述牺牲层310上外延生长Si层作为所述半导体纳米片层320。其中，所述牺牲层310的厚度可以为10-200nm，所述半导体纳米片层320的厚度可以为10-100nm。本实施例中，堆叠结构中的牺牲层310和半导体纳米片层320为两层，在其他实施例中，它们的层数可以更多，以提供更多数量的沟道。
S3定义至少两个并排的不同宽度的沟道区域，并刻蚀所述堆叠结构得到对应所述两个沟道区域的两组并排的不同宽度的半导体纳米片300，去除所述半导体纳米片300下方的牺牲层310，使所述半导体纳米片300周围裸露并悬于所述衬底100上。
如图3b所示，可以先利用光刻和刻蚀工艺形成浅沟槽隔离结构(STI)所需的沟槽，同时可定义出至少两个并排的沟道区域，分别对应P型场效应晶体管a和N型场效应晶体管b的第一沟道区域330a和第二沟道区域330b。所述沟槽从所述堆叠结构表面深入至衬底100中。刻蚀所述沟槽的同时，即可得到分别对应第一沟道区域330a和第二沟道区域330b的两组并排的半导体纳米片300。
然后，如图3c所示，在沟槽中填入隔离介质210，再如图3d所示采用化学机械研磨(CMP)使所得结构表面平坦化，避免在半导体纳米片300上有介质材料残留。随后，如图3e所示，利用光刻和刻蚀工艺去除第一沟道区域330a和第二沟道区域330b周围的隔离介质材料，保留填入衬底100中的隔离介质210。
接着，可以采用选择性横向刻蚀去除半导体纳米片300下方的牺牲层310，如图3f所示，使所述半导体纳米片300周围裸露并悬于所述衬底100上。本实施例中，去除SiGe材质的牺牲层310，可以采用包含HF、HNO3、H2O的腐蚀液。
为了获得跑道形的截面轮廓，去除牺牲层310后，还可以利用先氧化再湿法腐蚀的方法处理所述半导体纳米片300的拐角以形成圆角。如图3g所示，先氧化半导体纳米片300，再采用稀氟氢酸(DHF)腐蚀去除氧化层，从而得到截面大致为跑道形的半导体纳米片300。然后在高于800℃-1200℃的温度下进行氢退火，退火时间可为5分钟到8小时。进行氢退火可使腐蚀处理后的半导体纳米片300表面更加光滑、致密。
S4分别对两组半导体纳米片300进行离子掺杂，形成梯度掺杂的P型半导体纳米片沟道301和梯度掺杂的N型半导体纳米片沟道302，使所述P型半导体纳米片沟道301和所述N型半导体纳米片沟道302的掺杂浓度由表面向中心梯度递减。其中，宽度较大的一组半导体纳米片300用于形成P型半导体纳米片沟道301，宽度较小的一组半导体纳米片300用于形成N型半导体纳米片沟道302。
具体地，如图3h所示，可以利用化学气相沉积(CVD)或原子层沉积(ALD)工艺先在所述半导体纳米片300上沉积重掺杂硼的硼硅玻璃(BSG)层，然后去除用于形成N型半导体纳米片沟道302的半导体纳米片300上的硼硅玻璃(BSG)层，再进行高温退火使硼离子扩散入半导体纳米片300内，退火温度可以为800℃-1200℃，退火时间可为5分钟到8小时，随后去除硼硅玻璃(BSG)层，得到梯度掺杂的P型半导体纳米片沟道301。在P型半导体纳米片沟道301的表面硼离子的掺杂浓度最高，并从表面梯度递减至中心区域。去除硼硅玻璃(BSG)层可利用稀氟氢酸(DHF)湿法腐蚀工艺。接着，如图3i所示，可以利用化学气相沉积(CVD)或原子层沉积(ALD)工艺在另一组半导体纳米片300上沉积重掺杂磷或砷的磷硅玻璃(PSG)层，然后去除P型半导体纳米片沟道301上的磷硅玻璃(PSG)层，再进行高温退火使磷或砷离子扩散入半导体纳米片300内，退火温度可以为800℃-1200℃，退火时间可为5分钟到8小时，随后去除磷硅玻璃(PSG)层，得到梯度掺杂的N型半导体纳米片沟道302。在N型半导体纳米片沟道302的表面磷或砷离子的掺杂浓度最高，并从表面梯度递减至中心区域。去除磷硅玻璃(PSG)层可利用稀氟氢酸(DHF)湿法腐蚀工艺。本实施例中，先形成梯度掺杂的P型半导体纳米片沟道301，再形成梯度掺杂的N型半导体纳米片沟道302，而在本发明的其他实施例中，也可以先形成梯度掺杂的N型半导体纳米片沟道302，再形成梯度掺杂的P型半导体纳米片沟道301。
S5在所述P型半导体纳米片沟道301上形成完全环绕包围所述P型半导体纳米片沟道301的第一栅介质层401以及完全包围所述第一栅介质层401的第一栅极层501，在所述N型半导体纳米片沟道302上形成完全环绕包围所述N型半导体纳米片沟道302的第二栅介质层402以及完全包围所述第二栅介质层402的第二栅极层502。
如图3j所示，可以采用化学气相沉积(CVD)或原子层沉积(ALD)工艺沉积高介电常数(High-k)电介质作为第一栅介质层401和第二栅介质层402。形成栅介质层的同时，也在暴露的衬底100表面形成了绝缘埋层200。然后，如图3k所示，可以利用化学气相沉积(CVD)或原子层沉积(ALD)工艺沉积栅极材料，在第一栅介质层401和第二栅介质层402上分别形成第一栅极层501和第二栅极层502。具体地，可以先在第一栅介质层401上形成第一栅极层501，并去除沉积在第二栅介质层402上的栅极材料，然后再在第二栅介质层402上形成第二栅极层502，并去除第一栅极层501上多余的栅极材料。即，可以先形成第一栅极层501，再形成第二栅极层502。形成第一栅极层501的材料可以包括TiN、TaN、TiAl、Ti或其他适合的栅极材料，形成第二栅极层502的材料可以包括TiN、TaN、TiAl、Ti或其他适合的栅极材料。
S6形成共用栅电极600，所述共用栅电极600同时将第一栅极层501和第二栅极层502完全包围，使它们连接在一起，如图3l所示。形成共用栅电极600的材料可以包括Al、W、Cu等导电材料。
S7在所述P型半导体纳米片沟道301的两端分别形成第一源区S1和第一漏区D1，在所述N型半导体纳米片沟道302的两端分别形成第二源区S2和第二漏区D2，完成P型效应晶体管和N型效应晶体管的制作。
具体地，可以在所述P型半导体纳米片沟道301的两端外延生长P型的SiGe，作为所述第一源区S1和所述第一漏区D1。在所述N型半导体纳米片沟道302的两端外延生长N型的SiC作为所述第二源区S2和所述第二漏区D2。图3m为形成源漏区后器件侧面的示意图。
最后还可以根据图2所示的互补反相器电路形成完整的反相器，包括引出源极、漏极等步骤。由于pEFT和nEFT的沟道横向并排设置，使两端的源极漏极更加便于连接和引出，也使得器件更为紧凑，易于集成。
综上所述，本发明利用堆叠硅纳米片层制作了三维器件结构，栅极将沟道表面完全包围，实现了全包围栅，并且共用栅电极将多个沟道同时包围，使器件结构更为紧密，通过pEFT和nEFT形成互补反相器电路，pEFT与nEFT的沟道并排，pEFT的沟道宽度大于nEFT的沟道宽度，使反相器紧凑且平衡，沟道采用梯度掺杂，掺杂浓度由表面向中心梯度递减，能提高器件关态性能，降低漏电流及功耗，沟道截面为跑道形，可增大沟道横截面积，提高器件的驱动电流，而同时又保持器件的电完整性，使器件具备更好的性能及进一步按比例缩小的能力。
相较于现有技术，本发明的器件结构紧凑，有利于提高器件密度，提升芯片性能，并且结构简单，制作工艺易于实现。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (18)

1.一种全包围栅梯度掺杂纳米片互补反相器结构，其特征在于，包括：
衬底；
位于所述衬底上的P型场效应晶体管和N型场效应晶体管，所述P型场效应晶体管包括位于所述衬底上的P型半导体纳米片沟道、完全包围所述P型半导体纳米片沟道的第一栅介质层、完全包围所述第一栅介质层的第一栅极层以及相对的设置于所述P型半导体纳米片沟道两端的第一源区和第一漏区，所述N型场效应晶体管包括位于所述衬底上的N型半导体纳米片沟道、完全包围所述N型半导体纳米片沟道的第二栅介质层、完全包围所述第二栅介质层的第二栅极层以及相对的设置于所述N型半导体纳米片沟道两端的第二源区和第二漏区；以及
将所述第一栅极层和所述第二栅极层连接在一起的共用栅电极，所述共用栅电极将所述第一栅极层和所述第二栅极层完全包围；
其中，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道横向并排设置，且分别具有水平方向的宽度和长度，以及垂直于水平方向的高度，所述P型半导体纳米片沟道的长度定义了所述第一源区和所述第一漏区之间的距离，所述N型半导体纳米片沟道的长度定义了所述第二源区和所述第二漏区之间的距离，所述P型半导体纳米片沟道的宽度大于所述N型半导体纳米片沟道的宽度，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道的掺杂浓度由表面向中心梯度递减。
2.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述第一源极连接电源端，所述第一漏极与所述第二漏极连接在一起作为输出端，所述第二源极接地，所述共用栅电极作为输入端。
3.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述P型半导体纳米片沟道和所述N型半导体纳米片沟道在宽度方向的截面轮廓大致为跑道形，所述跑道形由左右两端的半圆及中部的与左右两端半圆过渡连接的矩形共同构成。
4.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述P型半导体纳米片沟道采用P型硅纳米片，所述N型半导体纳米片沟道采用N型硅纳米片。
5.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述P型效应晶体管包括纵向排列的多条所述P型半导体纳米片沟道，所述N型场效应晶体管包括纵向排列的多条所述N型半导体纳米片沟道。
6.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述第一源区和所述第一漏区的材料采用P型的SiGe，所述第二源区和所述第二漏区的材料采用N型的SiC。
7.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：在所述第一源区和所述第一漏区与第一栅极层和共用栅电极之间设有电介质层隔离，在所述第二源区和所述第二漏区与第二栅极层和共用栅电极之间也设有电介质层隔离。
8.根据权利要求1所述的全包围栅梯度掺杂纳米片互补反相器结构，其特征在于：所述P型场效应晶体管和所述N型场效应晶体管之下设有绝缘埋层与所述衬底隔离。
9.一种全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于，包括以下步骤：
提供衬底；
在所述衬底上形成牺牲层与半导体纳米片层交错的堆叠结构；
定义至少两个并排的不同宽度的沟道区域，并刻蚀所述堆叠结构得到分别对应所述两个沟道区域的两组并排的不同宽度的半导体纳米片，去除所述半导体纳米片下方的牺牲层，使所述半导体纳米片周围裸露并悬于所述衬底上；
分别对两组半导体纳米片进行离子掺杂，形成梯度掺杂的P型半导体纳米片沟道和梯度掺杂的N型半导体纳米片沟道，其中，所述P型半导体纳米片沟道和所述N型半导体纳米片沟道的掺杂浓度由表面向中心梯度递减，且所述P型半导体纳米片沟道的宽度大于所述N型半导体纳米片沟道的宽度；
在所述P型半导体纳米片沟道上形成完全环绕包围所述P型半导体纳米片沟道的第一栅介质层以及完全包围所述第一栅介质层的第一栅极层，在所述N型半导体纳米片沟道上形成完全环绕包围所述N型半导体纳米片沟道的第二栅介质层以及完全包围所述第二栅介质层的第二栅极层；
形成共用栅电极，所述共用栅电极同时将所述第一栅极层和所述第二栅极层完全包围；
在所述P型半导体纳米片沟道的两端分别形成第一源区和第一漏区，在所述N型半导体纳米片沟道的两端分别形成第二源区和第二漏区。
10.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：所述堆叠结构是在所述衬底上外延生长形成，所述牺牲层为外延生长的SiGe层，所述半导体纳米片层为外延生长在所述牺牲层上的Si层。
11.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：所述牺牲层的厚度为10-200nm，所述半导体纳米片层的厚度为10-100nm。
12.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：去除所述半导体纳米片下方的牺牲层之后，利用先氧化再湿法腐蚀的方法使所述半导体纳米片的拐角变为圆角。
13.根据权利要求12所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：利用先氧化再湿法腐蚀的方法使所述半导体纳米片的拐角变为圆角之后，对所述半导体纳米片进行氢退火。
14.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于，形成梯度掺杂的P型半导体纳米片沟道包括：在所述半导体纳米片表面沉积重掺杂硼的硼硅玻璃层，然后进行退火扩散，再去除所述硼硅玻璃层。
15.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于，形成梯度掺杂的N型半导体纳米片沟道包括：在所述半导体纳米片表面沉积重掺杂磷或砷的磷硅玻璃层，然后进行退火扩散，再去除所述磷硅玻璃层。
16.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：所述第一源区和所述第一漏区是在所述P型半导体纳米片沟道的两端外延生长形成，所述第二源区和所述第二漏区是在所述N型半导体纳米片沟道的两端外延生长形成。
17.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：所述第一源区和所述第一漏区的材料为P型的SiGe，所述第二源区和所述第二漏区的材料为N型的SiC。
18.根据权利要求9所述的全包围栅梯度掺杂纳米片互补反相器结构的制造方法，其特征在于：在所述衬底上形成浅沟槽隔离结构，并在所述衬底上形成绝缘埋层。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007742A1 (zh) * 2022-07-05 2024-01-11 北京理工大学 横向型全栅晶体管、三维集成电路、及其制造方法

Families Citing this family (5)

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US11799035B2 (en) * 2019-04-12 2023-10-24 The Research Foundation For The State University Of New York Gate all-around field effect transistors including quantum-based features
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US11417653B2 (en) * 2019-09-30 2022-08-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for forming the same
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101719500B (zh) 2009-12-01 2011-09-21 中国科学院上海微系统与信息技术研究所 混合材料反型模式全包围栅cmos场效应晶体管
KR101813181B1 (ko) * 2011-08-26 2017-12-29 삼성전자주식회사 튜너블 배리어를 포함하는 그래핀 전계효과 트랜지스터를 구비한 인버터 논리소자
US9847233B2 (en) * 2014-07-29 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9583490B2 (en) * 2015-01-20 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Inverters and manufacturing methods thereof
US9812449B2 (en) * 2015-11-20 2017-11-07 Samsung Electronics Co., Ltd. Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
CN107154428B (zh) * 2016-03-03 2019-12-24 上海新昇半导体科技有限公司 互补纳米线半导体器件及其制备方法
US11869973B2 (en) * 2018-06-20 2024-01-09 Intel Corporation Nanowire transistor structure and method of shaping
US10566248B1 (en) * 2018-07-27 2020-02-18 Globalfoundries Inc. Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007742A1 (zh) * 2022-07-05 2024-01-11 北京理工大学 横向型全栅晶体管、三维集成电路、及其制造方法

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