TWI685947B - 全包圍閘奈米片互補反相器結構及其製造方法 - Google Patents
全包圍閘奈米片互補反相器結構及其製造方法 Download PDFInfo
- Publication number
- TWI685947B TWI685947B TW108114247A TW108114247A TWI685947B TW I685947 B TWI685947 B TW I685947B TW 108114247 A TW108114247 A TW 108114247A TW 108114247 A TW108114247 A TW 108114247A TW I685947 B TWI685947 B TW I685947B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- type semiconductor
- layer
- type
- nano
- Prior art date
Links
- 239000002135 nanosheet Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000000295 complement effect Effects 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 148
- 239000002090 nanochannel Substances 0.000 claims description 68
- 239000000758 substrate Substances 0.000 claims description 44
- 230000005669 field effect Effects 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000002055 nanoplate Substances 0.000 claims 4
- 239000013078 crystal Substances 0.000 claims 1
- 238000012856 packing Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 19
- 230000000694 effects Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 241000209094 Oryza Species 0.000 description 3
- 235000007164 Oryza sativa Nutrition 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 235000009566 rice Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本發明提供一種全包圍閘奈米片互補反相器結構,包括P型場效應電晶體和N型場效應電晶體, P型場效應電晶體包括P型半導體奈米片通道和完全包圍P型半導體奈米片通道的第一閘介電層、第一閘極層以及設置於通道兩端的源區和汲區, N型場效應電晶體包括N型半導體奈米片通道、完全包圍N型半導體奈米片通道的第二閘介電層、第二閘極層以及設置於通道兩端的源區和汲區;其中, P型半導體奈米片通道和N型半導體奈米片通道橫向並排設置, P型半導體奈米片通道的寬度大於N型半導體奈米片通道的寬度;並設有共用閘電極將第一閘極層和第二閘極層完全包圍。本發明的元件結構緊湊,有利於提高元件密度,提升晶片性能,並且結構簡單,製作工藝易於實現。
Description
本發明涉及半導體元件領域,特別是涉及一種全包圍閘奈米片互補反相器結構及其製造方法。
FinFET是一種具有垂直“鰭”結構的鰭式場效應電晶體。鰭式的三維結構可以形成三個閘極以提高功率和效率。當今的14奈米和10奈米晶片採用帶有這種FinFET的晶片供電,甚至不久前宣佈的7奈米測試晶片也是如此。這些FinFET晶片最近已開始進入伺服器、電腦和設備,並將成為未來幾年的標準。
公開號為US08350298B2的美國專利HYBRID MATERIAL INVERSION MODE GAA CMOSFET公開了一種採用混合材料的全包圍閘CMOS場效應電晶體。該電晶體的PMOS通道和NMOS通道的橫截面為跑道形,閘極將PMOS通道和NMOS通道的表面完全包圍。這種全包圍閘(GAA,Gate-All-Around)電晶體結構具備較高的載子遷移率、可避免多晶矽閘耗盡及短通道效應等優點。
通過將矽奈米片層水平堆疊在一起,可以實現5奈米節點的GAA電晶體結構,提供未來應用所需的功率和性能提升。從垂直結構到水平矽層的變化開啟了電晶體上的第四個“閘”,這使得電信號能夠穿過晶片上的其他電晶體並在它們之間傳遞。在這些維度上,它意味著這些信號正穿過一個寬度不大於兩到三條並排DNA鏈寬度的開關。因此,人們非常渴望利用類似這樣的新的性能提升技術,來應對超過5nm節點的元件所面臨的挑戰。
在京都召開的2017年VLSI技術和電路研討會上宣佈了一種用於5奈米節點晶片的新型電晶體。這種電晶體採用業界一流的製程來堆疊矽奈米片作為元件結構,將閘極圍繞在電晶體周圍,能夠在指甲大小的晶片上實現300億個開關的規模,這與如今最先進的10奈米晶片相比將顯著提高功率和性能。
然而,在實際的生產應用中,如何進一步提高元件的密度、功率和性能仍是本領域技術人員亟待解決的技術問題。
鑒於以上所述現有技術,本發明的目的在於提供一種全包圍閘奈米片互補反相器結構及其製造方法,用於進一步提升元件性能。
為實現上述目的及其他相關目的,本發明提供一種全包圍閘奈米片互補反相器結構,包括:基板;位於所述基板上的P型場效應電晶體和N型場效應電晶體,所述P型場效應電晶體包括位於所述基板上的P型半導體奈米片通道、完全包圍所述P型半導體奈米片通道的第一閘介電層、完全包圍所述第一閘介電層的第一閘極層以及相
對的設置於所述P型半導體奈米片通道兩端的第一源區和第一汲區,所述N型場效應電晶體包括位於所述基板上的N型半導體奈米片通道、完全包圍所述N型半導體奈米片通道的第二閘介電層、完全包圍所述第二閘介電層的第二閘極層以及相對的設置於所述N型半導體奈米片通道兩端的第二源區和第二汲區;以及將所述第一閘極層和所述第二閘極層連接在一起的共用閘電極,所述共用閘電極將所述第一閘極層和所述第二閘極層完全包圍;其中,所述P型半導體奈米片通道和所述N型半導體奈米片通道橫向並排設置,且分別具有水平方向的寬度和長度,以及垂直于水平方向的高度,所述P型半導體奈米片通道的長度定義了所述第一源區和所述第一汲區之間的距離,所述N型半導體奈米片通道的長度定義了所述第二源區和所述第二汲區之間的距離,所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度。
可選地,所述第一源極連接電源端VDD,所述第一汲極與所述第二汲極連接在一起作為輸出端Vout,所述第二源極接地,所述共用閘電極作為輸入端Vin。
可選地,所述P型半導體奈米片通道和所述N型半導體奈米片通道在寬度方向的截面輪廓大致為跑道形,所述跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。
可選地,所述P型半導體奈米片通道採用P型矽奈米片,所述N型半導體奈米片通道採用N型矽奈米片。
可選地,所述P型效應電晶體包括縱向排列的多條所述P型半導體奈米片通道,所述N型場效應電晶體包括縱向排列的多條所述N型半導體奈米片通道。
可選地,所述第一源區和所述第一汲區的材料採用P型的SiGe,所述第二源區和所述第二汲區的材料採用N型的SiC。
可選地,在所述第一源區和所述第一汲區與第一閘極層和共用閘電極之間設有介電層隔離,在所述第二源區和所述第二汲區與第二閘極層和共用閘電極之間也設有介電層隔離。
可選地,所述P型場效應電晶體和所述N型場效應電晶體之下設有絕緣埋層與所述基板隔離。
為實現上述目的及其他相關目的,本發明還提供一種全包圍閘奈米片互補反相器結構的製造方法,包括以下步驟:提供基板;在所述基板上形成犧牲層與半導體奈米片層交錯的堆疊結構;定義至少兩個並排的不同寬度的通道區域,並蝕刻所述堆疊結構得到分別對應所述兩個通道區域的兩組並排的不同寬度的半導體奈米片,去除所述半導體奈米片下方的犧牲層,使所述半導體奈米片周圍裸露並懸於所述基板上;分別對兩組半導體奈米片進行離子摻雜,形成P型半導體奈米片通道和N型半導體奈米片通道,且所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度;在所述P型半導體奈米片通道上形成完全環繞包圍所述P型半導體奈米片通道的第一閘介電層以及完全包圍所述第一閘介電層的第一閘極層,在所述N型半導體奈米片通道上形成完全環繞包圍所述N型半導體奈米片通道的第二閘介電層以及完全包圍所述第二閘介電層的第二閘極層;
形成共用閘電極,所述共用閘電極同時將所述第一閘極層和所述第二閘極層完全包圍;在所述P型半導體奈米片通道的兩端分別形成第一源區和第一汲區,在所述N型半導體奈米片通道的兩端分別形成第二源區和第二汲區。
可選地,所述堆疊結構是在所述基板上磊晶生長形成,所述犧牲層為磊晶生長的SiGe層,所述半導體奈米片層為磊晶生長在所述犧牲層上的Si層。
可選地,所述犧牲層的厚度為10-200nm,所述半導體奈米片層的厚度為10-100nm。
可選地,去除所述半導體奈米片下方的犧牲層之後,利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角。進一步可選地,利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角之後,對所述半導體奈米片進行氫退火。
可選地,所述第一源區和所述第一汲區是在所述P型半導體奈米片通道的兩端磊晶生長形成,所述第二源區和所述第二汲區是在所述N型半導體奈米片通道的兩端磊晶生長形成。
可選地,所述第一源區和所述第一汲區的材料為P型的SiGe,所述第二源區和所述第二汲區的材料為N型的SiC。
可選地,在所述基板上形成淺溝槽隔離結構,並在所述基板上形成絕緣埋層。
如上所述,本發明的全包圍閘奈米片互補反相器結構及其製造方法,具有以下有益效果:
本發明利用堆疊矽奈米片層製作了三維元件結構,閘極將通道表面完全包圍,實現了全包圍閘,並且共用閘電極將多個通道同時包圍,使結構更為緊密,通過pFET和nFET形成互補反相器電路,pFET與nFET的通道並排,pFET的通道寬度大於nFET的通道寬度,使反相器緊湊平衡,具備更好的性能及進一步按比例縮小的能力。此外,通道截面為跑道形,可增大通道橫截面積,提高元件的驅動電流,而同時又保持元件的電完整性。
相較於現有技術,本發明的元件結構緊湊,有利於提高元件密度,提升晶片性能,並且結構簡單,製作工藝易於實現。
100‧‧‧基板
200‧‧‧絕緣埋層
210‧‧‧隔離介電層
300‧‧‧半導體奈米片
301‧‧‧P型半導體奈米片通道
302‧‧‧N型半導體奈米片通道
310‧‧‧犧牲層
320‧‧‧半導體奈米片層
330a‧‧‧第一通道區域
330b‧‧‧第二通道區域
401‧‧‧第一閘介電層
402‧‧‧第二閘介電層
501‧‧‧第一閘極層
502‧‧‧第二閘極層
600‧‧‧共用閘電極
700‧‧‧介電層
圖1a-1b顯示為本發明實施例提供的全包圍閘奈米片互補反相器結構的示意圖,其中,圖1a為俯視示意圖,圖1b為圖1a中AA’方向的截面示意圖。
圖2顯示為本發明實施例提供的全包圍閘奈米片互補反相器的電路示意圖。
圖3a-3n顯示為本發明實施例提供的全包圍閘奈米片互補反相器結構製造方法的流程示意圖。
在下文的描述中,給出了大量具體的細節以便提供對本發明更為徹底的理解。然而,對於本領域技術人員而言顯而易見的是,本發明可以無需一個
或多個這些細節而得以實施。在其他的例子中,為了避免與本發明發生混淆,對於本領域公知的一些技術特徵未進行描述。
以下通過特定的具體實例說明本發明的實施方式,本領域技術人員可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用,本說明書中的各項細節也可以基於不同觀點與應用,在沒有背離本發明的精神下進行各種修飾或改變。需說明的是,在不衝突的情況下,以下實施例及實施例中的特徵可以相互組合。
需要說明的是,以下實施例中所提供的圖示僅以示意方式說明本發明的基本構想,遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的元件數目、形狀及尺寸繪製,其實際實施時各元件的型態、數量及比例可為一種隨意的改變,且其元件佈局型態也可能更為複雜。
請參閱圖1a和圖1b,本實施例提供一種全包圍閘奈米片互補反相器結構,其包括:基板100、位於所述基板100上的P型場效應電晶體a、N型場效應電晶體b和共用閘電極600,其中,圖1a為俯視示意圖,圖1b為圖1a中AA’方向的截面示意圖。
所述基板100可以是常規的體矽基板或其他適合的半導體基板。在所述基板100上設有絕緣埋層200,使之與所述P型場效應電晶體a和所述N型場效應電晶體b隔離。
所述P型場效應電晶體a和所述N型場效應電晶體b均為全包圍閘的非平面電晶體。它們的結構基本相同。所述P型場效應電晶體a包括位於所述基板100上的P型半導體奈米片通道301、完全包圍所述P型半導體奈米片通道301的第一閘介電層401、完全包圍所述第一閘介電層401的第一閘極層501以及相對的
設置於所述P型半導體奈米片通道301兩端的第一源區S1和第一汲區D1。所述N型場效應電晶體b包括位於所述基板100上的N型半導體奈米片通道302、完全包圍所述N型半導體奈米片通道302的第二閘介電層402、完全包圍所述第二閘介電層402的第二閘極層502以及相對的設置於所述N型半導體奈米片通道302兩端的第二源區S2和第二汲區D2。
所述共用閘電極600完全包圍第一閘極層501和第二閘極層502,使它們連接在一起。
其中,所述P型半導體奈米片通道301和所述N型半導體奈米片通道302橫向並排設置。所述P型半導體奈米片通道301具有水平方向的寬度w1和長度11,以及垂直於水平方向的高度h1,長度11定義了所述第一源區S1和所述第一汲區D1之間的距離。所述N型半導體奈米片通道302具有水平方向的寬度w2和長度12,以及垂直於水平方向的高度h2,長度12定義了所述第二源區S2和所述第二汲區D2之間的距離。所述P型半導體奈米片通道301的寬度w2大於所述N型半導體奈米片通道302的寬度w2。它們的高度h1和h2基本相同,可以為10-100nm。它們在寬度方向上的截面輪廓都大致為跑道形,如圖1b中所示,所述跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。這種截面形狀可增大通道橫截面積,提高元件的驅動電流,而同時又保持元件的電完整性。由於pFET的通道載子電洞,其遷移率比nFET的通道載子電子遷移率小很多,因此,本發明設計的pFET通道寬度比nFET更寬,使組成的CMOS更為平衡。
具體地,所述P型半導體奈米片通道301可以採用P型矽奈米片。所述N型半導體奈米片通道302可以採用N型矽奈米片。pFET的源汲區,即第一源區S1和第一汲區D1,可以採用磊晶生長的P型SiGe材料,nFET的源汲區,即第二
源區S2和第二汲區D2的材料可以採用磊晶生長的N型SiC材料。其中,pFET的源汲區採用SiGe可對pFET的通道產生壓應力,以提高載子電洞遷移率;nFET的源汲區採用SiC可對nFET的通道產生張應力,以提高載子電子遷移率。在所述第一源區S1和所述第一汲區D1與第一閘極層501和共用閘電極600之間設有電介電層700作為側牆隔離(spacer),在所述第二源區S2和所述第二汲區D2與第二閘極層502和共用閘電極600之間也設有電介電層700作為側牆隔離(spacer)。
本實施例的全包圍閘奈米片互補反相器結構可採用如圖2所示的互補反相器電路,其中,所述P型場效應電晶體a即為pFET,所述N型場效應電晶體b即為nFET,第一源極S1連接電源端VDD,所述第一汲極D1與所述第二汲極D2連接在一起作為輸出端Vout,所述第二源極S2接地,所述共用閘電極作為輸入端Vin。
此外,作為本發明的優選方案,所述P型效應電晶體a可以包括縱向排列的多條所述P型半導體奈米片通道301;所述N型場效應電晶體b可以包括縱向排列的多條所述N型半導體奈米片通道302,以提高元件性能。本實施例中,每個電晶體可以對應上下兩條通道,而在本發明的其他實施例中,每個場效應電晶體還可以對應更多數量的通道。
下面結合附圖進一步詳細說明本實施例提供的全包圍閘奈米片互補反相器結構的製造方法。
請參閱圖3a-3n,本實施例提供一種全包圍閘奈米片互補反相器結構的製造方法,包括S1-S7等步驟。
S1提供基板100。所述基板100可以是常規的體矽基板或其他適合的半導體基板。
S2在所述基板100上形成犧牲層310與半導體奈米片層320交錯的堆疊結構,如圖3a所示。
具體地,所述堆疊結構可以在所述基板100上磊晶生長形成。例如,可以在所述基板100上磊晶生長SiGe層作為所述犧牲層310,再在所述犧牲層310上磊晶生長Si層作為所述半導體奈米片層320。其中,所述犧牲層310的厚度可以為10-200nm,所述半導體奈米片層320的厚度可以為10-100nm。本實施例中,堆疊結構中的犧牲層310和半導體奈米片層320為兩層,在其他實施例中,它們的層數可以更多,以提供更多數量的通道。
S3定義至少兩個並排的不同寬度的通道區域,並蝕刻所述堆疊結構得到對應所述兩個通道區域的兩組並排的不同寬度的半導體奈米片300,去除所述半導體奈米片300下方的犧牲層310,使所述半導體奈米片300周圍裸露並懸於所述基板100上。
如圖3b所示,可以先利用微影和蝕刻製程形成淺溝槽隔離結構(STI)所需的溝槽,同時可定義出至少兩個並排的通道區域,分別對應P型場效應電晶體a和N型場效應電晶體b的第一通道區域330a和第二通道區域330b。所述溝槽從所述堆疊結構表面深入至基板100中。蝕刻所述溝槽的同時,即可得到分別對應第一通道區域330a和第二通道區域330b的兩組並排的半導體奈米片300。
然後,如圖3c所示,在溝槽中填入隔離介電210,再如圖3d所示採用化學機械研磨(CMP)使所得結構表面平坦化,避免在半導體奈米片300上有介電材料殘留。隨後,如圖3e所示,利用微影和蝕刻製程去除第一通道區域330a和第二通道區域330b周圍的隔離介電材料,保留填入基板100中的隔離介電210。
接著,可以採用選擇性橫向蝕刻去除半導體奈米片300下方的犧牲層310,如圖3f所示,使所述半導體奈米片300周圍裸露並懸於所述基板100上。本實施例中,去除SiGe材質的犧牲層310,可以採用包含HF、HNO3、H2O的蝕刻液。
為了獲得跑道形的截面輪廓,去除犧牲層310後,還可以利用先氧化再濕式蝕刻的方法處理所述半導體奈米片300的拐角以形成圓角。如圖3g所示,先氧化半導體奈米片300,再採用稀氟氫酸(DHF)蝕刻去除氧化層,從而得到截面大致為跑道形的半導體奈米片300。然後在高於800℃-1200℃的溫度下進行氫退火,退火時間可為5分鐘到8小時。進行氫退火可使蝕刻處理後的半導體奈米片300表面更加光滑、緻密。
S4採用離子注入的方法分別對兩組半導體奈米片300進行離子摻雜,形成P型半導體奈米片通道301和N型半導體奈米片通道302。如圖3h所示,寬度較大的一組半導體奈米片300用於形成P型半導體奈米片通道301,寬度較小的一組半導體奈米片300用於形成N型半導體奈米片通道302。
S5在所述P型半導體奈米片通道301上形成完全環繞包圍所述P型半導體奈米片通道301的第一閘介電層401以及完全包圍所述第一閘介電層401的第一閘極層501,在所述N型半導體奈米片通道302上形成完全環繞包圍所述N型半導體奈米片通道302的第二閘介電層402以及完全包圍所述第二閘介電層402的第二閘極層502。
如圖3i所示,可以採用化學氣相沉積(CVD)或原子層沉積(ALD)製程沉積高介電常數(High-k)介電作為第一閘介電層401和第二閘介電層402。形成閘介電層的同時,也在暴露的基板100表面形成了絕緣埋層200。然後,如圖
3j所示,可以利用化學氣相沉積(CVD)或原子層沉積(ALD)製程沉積閘極材料,在第一閘介電層401和第二閘介電層402上分別形成第一閘極層501和第二閘極層502。具體地,可以先在第一閘介電層401上形成第一閘極層501,並去除沉積在第二閘介電層402上的閘極材料,然後再在第二閘介電層402上形成第二閘極層502,並去除第一閘極層501上多餘的閘極材料。即,可以先形成第一閘極層501,再形成第二閘極層502。形成第一閘極層501的材料可以包括TiN、TaN、TiAl、Ti或其他適合的閘極材料,形成第二閘極層502的材料可以包括TiN、TaN、TiAl、Ti或其他適合的閘極材料。
S6形成共用閘電極600,所述共用閘電極600同時將第一閘極層501和第二閘極層502完全包圍,使它們連接在一起,如圖3k所示。形成共用閘電極600的材料可以包括Al、W、Cu等導電材料。
S7在所述P型半導體奈米片通道301的兩端分別形成第一源區S1和第一汲區D1,在所述N型半導體奈米片通道302的兩端分別形成第二源區S2和第二汲區D2,完成P型效應電晶體和N型效應電晶體的製作。
具體地,可以在所述P型半導體奈米片通道301的兩端磊晶生長P型的SiGe,作為所述第一源區S1和所述第一汲區D1。在所述N型半導體奈米片通道302的兩端磊晶生長N型的SiC作為所述第二源區S2和所述第二汲區D2。圖31為形成源汲區後元件側面的示意圖,圖3m和3n分別為沿P型半導體奈米片通道301和N型半導體奈米片通道302的長度方向的截面示意圖。在所述第一源區S1和所述第一汲區D1與第一閘極層501和共用閘電極600之間設有介電層700隔離,在所述第二源區S2和所述第二汲區D2與第二閘極層502和共用閘電極600之間也設有介電層700隔離。
最後還可以根據圖2所示的互補反相器電路形成完整的反相器,包括引出源極、汲極等步驟。由於pFET和nFET的通道橫向並排設置,使兩端的源極汲極更加便於連接和引出,也使得元件更為緊湊,易於集成。
綜上所述,本發明利用堆疊矽奈米片層製作了三維元件結構,閘極將通道表面完全包圍,實現了全包圍閘,並且共用閘電極將多個通道同時包圍,使元件結構更為緊密,通過pFET和nFET形成互補反相器電路,pFET與nFET的通道並排,pFET的通道寬度大於nFET的通道寬度,使反相器緊湊平衡,具備更好的性能及進一步按比例縮小的能力。此外,通道截面為跑道形,可增大通道橫截面積,提高元件的驅動電流,而同時又保持元件的電完整性。
相較于現有技術,本發明的元件結構緊湊,有利於提高元件密度,提升晶片性能,並且結構簡單,製作工藝易於實現。所以,本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。上述實施例僅例示性說明本發明的原理及其功效,而非用於限制本發明。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下,對上述實施例進行修飾或改變。因此,舉凡所屬技術領域中具有通常知識者在未脫離本發明所揭示的精神與技術思想下所完成的一切等效修飾或改變,仍應由本發明的請求項所涵蓋。
100‧‧‧基板
200‧‧‧絕緣埋層
301‧‧‧P型半導體奈米片通道
302‧‧‧N型半導體奈米片通道
401‧‧‧第一閘介電層
402‧‧‧第二閘介電層
501‧‧‧第一閘極層
502‧‧‧第二閘極層
600‧‧‧共用閘電極
Claims (16)
- 一種全包圍閘奈米片互補反相器結構,包括:基板;位於所述基板上的P型場效應電晶體和N型場效應電晶體,所述P型場效應電晶體包括位於所述基板上的P型半導體奈米片通道、完全包圍所述P型半導體奈米片通道的第一閘介電層、完全包圍所述第一閘介電層的第一閘極層以及相對的設置於所述P型半導體奈米片通道兩端的第一源區和第一汲區,所述N型場效應電晶體包括位於所述基板上的N型半導體奈米片通道、完全包圍所述N型半導體奈米片通道的第二閘介電層、完全包圍所述第二閘介電層的第二閘極層以及相對的設置於所述N型半導體奈米片通道兩端的第二源區和第二汲區;以及將所述第一閘極層和所述第二閘極層連接在一起的共用閘電極,所述共用閘電極將所述第一閘極層和所述第二閘極層完全包圍;其中,所述P型半導體奈米片通道和所述N型半導體奈米片通道橫向並排設置,且分別具有水平方向的寬度和長度,以及垂直於水平方向的高度,所述P型半導體奈米片通道的長度定義了所述第一源區和所述第一汲區之間的距離,所述N型半導體奈米片通道的長度定義了所述第二源區和所述第二汲區之間的距離,所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述第一源極連接電源端,所述第一汲極與所述第二汲極連接在一起作為輸出端,所述第二源極接地,所述共用閘電極作為輸入端。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述P型半導體奈米片通道和所述N型半導體奈米片通道在寬度方向的截面輪廓實質為 跑道形,所述跑道形由左右兩端的半圓及中部的與左右兩端半圓過渡連接的矩形共同構成。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述P型半導體奈米片通道採用P型矽奈米片,所述N型半導體奈米片通道採用N型矽奈米片。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述P型效應電晶體包括縱向排列的多條所述P型半導體奈米片通道,所述N型場效應電晶體包括縱向排列的多條所述N型半導體奈米片通道。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述第一源區和所述第一汲區的材料採用P型的SiGe,所述第二源區和所述第二汲區的材料採用N型的SiC。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中在所述第一源區和所述第一汲區與第一閘極層和共用閘電極之間設有電介電層隔離,在所述第二源區和所述第二汲區與第二閘極層和共用閘電極之間也設有電介電層隔離。
- 如請求項1所述的全包圍閘奈米片互補反相器結構,其中所述P型場效應電晶體和所述N型場效應電晶體之下設有絕緣埋層與所述基板隔離。
- 一種全包圍閘奈米片互補反相器結構的製造方法,包括以下步驟:提供基板;在所述基板上形成犧牲層與半導體奈米片層交錯的堆疊結構;定義至少兩個並排的不同寬度的通道區域,並蝕刻所述堆疊結構得到分別對應所述兩個通道區域的兩組並排的不同寬度的半導體奈米片,去除所述 半導體奈米片下方的犧牲層,使所述半導體奈米片周圍裸露並懸於所述基板上;分別對兩組半導體奈米片進行離子摻雜,形成P型半導體奈米片通道和N型半導體奈米片通道,且所述P型半導體奈米片通道的寬度大於所述N型半導體奈米片通道的寬度;在所述P型半導體奈米片通道上形成完全環繞包圍所述P型半導體奈米片通道的第一閘介電層以及完全包圍所述第一閘介電層的第一閘極層,在所述N型半導體奈米片通道上形成完全環繞包圍所述N型半導體奈米片通道的第二閘介電層以及完全包圍所述第二閘介電層的第二閘極層;形成共用閘電極,所述共用閘電極同時將所述第一閘極層和所述第二閘極層完全包圍;及在所述P型半導體奈米片通道的兩端分別形成第一源區和第一汲區,在所述N型半導體奈米片通道的兩端分別形成第二源區和第二汲區。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中所述堆疊結構是在所述基板上磊晶生長形成,所述犧牲層為磊晶生長的SiGe層,所述半導體奈米片層為磊晶生長在所述犧牲層上的Si層。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中所述犧牲層的厚度為10-200nm,所述半導體奈米片層的厚度為10-100nm。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中在去除所述半導體奈米片下方的犧牲層之後,利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角。
- 如請求項12所述的全包圍閘奈米片互補反相器結構的製造方法,其中利用先氧化再濕式蝕刻的方法使所述半導體奈米片的拐角變為圓角之後,對所述半導體奈米片進行氫退火。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中所述第一源區和所述第一汲區是在所述P型半導體奈米片通道的兩端磊晶生長形成,所述第二源區和所述第二汲區是在所述N型半導體奈米片通道的兩端磊晶生長形成。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中所述第一源區和所述第一汲區的材料為P型的SiGe,所述第二源區和所述第二汲區的材料為N型的SiC。
- 如請求項9所述的全包圍閘奈米片互補反相器結構的製造方法,其中在所述基板上形成淺溝槽隔離結構,並在所述基板上形成絕緣埋層。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811134878.9 | 2018-09-28 | ||
CN201811134878.9A CN110970432A (zh) | 2018-09-28 | 2018-09-28 | 全包围栅纳米片互补反相器结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI685947B true TWI685947B (zh) | 2020-02-21 |
TW202013676A TW202013676A (zh) | 2020-04-01 |
Family
ID=69945183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108114247A TWI685947B (zh) | 2018-09-28 | 2019-04-24 | 全包圍閘奈米片互補反相器結構及其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10916544B2 (zh) |
CN (1) | CN110970432A (zh) |
TW (1) | TWI685947B (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11799035B2 (en) * | 2019-04-12 | 2023-10-24 | The Research Foundation For The State University Of New York | Gate all-around field effect transistors including quantum-based features |
US11152377B2 (en) * | 2019-04-25 | 2021-10-19 | International Business Machines Corporation | Nanosheet SRAM by SIT process |
US11417653B2 (en) * | 2019-09-30 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for forming the same |
CN113571515B (zh) * | 2020-04-29 | 2024-04-09 | 广东致能科技有限公司 | 一种驱动电路、驱动ic以及驱动系统 |
US11295988B2 (en) * | 2020-06-11 | 2022-04-05 | International Business Machines Corporation | Semiconductor FET device with bottom isolation and high-κ first |
CN116195047A (zh) * | 2020-10-22 | 2023-05-30 | 华为技术有限公司 | 环栅纳米片场效应晶体管和制备方法 |
US11527535B2 (en) | 2021-01-21 | 2022-12-13 | International Business Machines Corporation | Variable sheet forkFET device |
US11776856B2 (en) | 2021-03-25 | 2023-10-03 | Nxp B.V. | Nanosheet transistors with different gate materials in same stack and method of making |
WO2022198568A1 (zh) * | 2021-03-25 | 2022-09-29 | 华为技术有限公司 | 反相器及其制备方法、半导体器件、芯片、终端设备 |
CN114267736A (zh) * | 2021-06-02 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 一种堆叠式全栅纳米片器件及其制造方法 |
CN117690955A (zh) * | 2022-09-01 | 2024-03-12 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350298B2 (en) * | 2009-12-01 | 2013-01-08 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Hybrid material inversion mode GAA CMOSFET |
CN103426764A (zh) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
JP2017011272A (ja) * | 2015-06-22 | 2017-01-12 | グローバルファウンドリーズ・インコーポレイテッド | finFET構造を形成する方法、半導体基板とfinFETトランジスタを提供する方法、およびfinFETトランジスタ |
TW201830704A (zh) * | 2017-02-08 | 2018-08-16 | 美商格芯(美國)集成電路科技有限公司 | 垂直場效電晶體與鞍形鰭式場效電晶體的整合 |
CN108470766A (zh) * | 2018-03-14 | 2018-08-31 | 上海华力集成电路制造有限公司 | 全包覆栅极晶体管及其制造方法 |
CN108511344A (zh) * | 2018-02-09 | 2018-09-07 | 中国科学院微电子研究所 | 垂直纳米线晶体管与其制作方法 |
TW201834249A (zh) * | 2016-12-09 | 2018-09-16 | 日商半導體能源硏究所股份有限公司 | 半導體裝置以及半導體裝置的製造方法 |
US20180269320A1 (en) * | 2017-03-17 | 2018-09-20 | International Business Machines Corporation | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate |
US20180277652A1 (en) * | 2017-03-24 | 2018-09-27 | Globalfoundries Inc. | Field effect transistor (fet) with a gate having a recessed work function metal layer and method of forming the fet |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7928426B2 (en) * | 2007-03-27 | 2011-04-19 | Intel Corporation | Forming a non-planar transistor having a quantum well channel |
JP4966153B2 (ja) * | 2007-10-05 | 2012-07-04 | 株式会社東芝 | 電界効果トランジスタおよびその製造方法 |
WO2009107031A1 (en) * | 2008-02-26 | 2009-09-03 | Nxp B.V. | Method for manufacturing semiconductor device and semiconductor device |
CN101719501B (zh) * | 2009-12-01 | 2011-07-20 | 中国科学院上海微系统与信息技术研究所 | 混合晶向反型模式全包围栅cmos场效应晶体管 |
CN104011849B (zh) * | 2011-12-23 | 2016-12-28 | 英特尔公司 | Cmos纳米线结构 |
US9171843B2 (en) * | 2013-08-02 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
KR102083632B1 (ko) * | 2014-04-25 | 2020-03-03 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9853101B2 (en) * | 2015-10-07 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained nanowire CMOS device and method of forming |
US9754840B2 (en) * | 2015-11-16 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Horizontal gate-all-around device having wrapped-around source and drain |
KR102434993B1 (ko) * | 2015-12-09 | 2022-08-24 | 삼성전자주식회사 | 반도체 소자 |
US9704962B1 (en) * | 2015-12-16 | 2017-07-11 | Globalfoundries Inc. | Horizontal gate all around nanowire transistor bottom isolation |
KR102367408B1 (ko) * | 2016-01-04 | 2022-02-25 | 삼성전자주식회사 | 복수의 시트들로 구성된 채널 영역을 포함하는 sram 소자 |
KR102618607B1 (ko) * | 2016-09-06 | 2023-12-26 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10170378B2 (en) * | 2016-11-29 | 2019-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate all-around semiconductor device and manufacturing method thereof |
KR102316293B1 (ko) * | 2017-09-18 | 2021-10-22 | 삼성전자주식회사 | 반도체 장치 |
US10304833B1 (en) * | 2018-02-19 | 2019-05-28 | Globalfoundries Inc. | Method of forming complementary nano-sheet/wire transistor devices with same depth contacts |
US10263100B1 (en) * | 2018-03-19 | 2019-04-16 | International Business Machines Corporation | Buffer regions for blocking unwanted diffusion in nanosheet transistors |
US11329136B2 (en) * | 2018-06-01 | 2022-05-10 | International Business Machines Corporation | Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression |
US10741641B2 (en) * | 2018-06-20 | 2020-08-11 | International Business Machines Corporation | Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices |
US11031395B2 (en) * | 2018-07-13 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming high performance MOSFETs having varying channel structures |
US10804162B2 (en) * | 2018-09-27 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual channel gate all around transistor device and fabrication methods thereof |
-
2018
- 2018-09-28 CN CN201811134878.9A patent/CN110970432A/zh not_active Withdrawn
-
2019
- 2019-04-24 TW TW108114247A patent/TWI685947B/zh active
- 2019-08-29 US US16/556,060 patent/US10916544B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350298B2 (en) * | 2009-12-01 | 2013-01-08 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Hybrid material inversion mode GAA CMOSFET |
CN103426764A (zh) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
JP2017011272A (ja) * | 2015-06-22 | 2017-01-12 | グローバルファウンドリーズ・インコーポレイテッド | finFET構造を形成する方法、半導体基板とfinFETトランジスタを提供する方法、およびfinFETトランジスタ |
TW201834249A (zh) * | 2016-12-09 | 2018-09-16 | 日商半導體能源硏究所股份有限公司 | 半導體裝置以及半導體裝置的製造方法 |
TW201830704A (zh) * | 2017-02-08 | 2018-08-16 | 美商格芯(美國)集成電路科技有限公司 | 垂直場效電晶體與鞍形鰭式場效電晶體的整合 |
US20180269320A1 (en) * | 2017-03-17 | 2018-09-20 | International Business Machines Corporation | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate |
US20180277652A1 (en) * | 2017-03-24 | 2018-09-27 | Globalfoundries Inc. | Field effect transistor (fet) with a gate having a recessed work function metal layer and method of forming the fet |
CN108511344A (zh) * | 2018-02-09 | 2018-09-07 | 中国科学院微电子研究所 | 垂直纳米线晶体管与其制作方法 |
CN108470766A (zh) * | 2018-03-14 | 2018-08-31 | 上海华力集成电路制造有限公司 | 全包覆栅极晶体管及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW202013676A (zh) | 2020-04-01 |
US10916544B2 (en) | 2021-02-09 |
CN110970432A (zh) | 2020-04-07 |
US20200105762A1 (en) | 2020-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI685947B (zh) | 全包圍閘奈米片互補反相器結構及其製造方法 | |
TWI700830B (zh) | 反型模式全包圍閘奈米片互補反相器結構及其製造方法 | |
TWI695505B (zh) | 全包圍閘量子井互補反相器結構及其製造方法 | |
TWI692102B (zh) | 全包圍閘梯度摻雜奈米片互補反相器結構及其製造方法 | |
TWI701723B (zh) | 閘極環繞奈米片場效應電晶體及其製造方法 | |
CN104241134B (zh) | 具有替代鳍的非平面晶体管及其制造方法 | |
WO2011066730A1 (zh) | 混合晶向反型模式全包围栅cmos场效应晶体管 | |
JPWO2009151001A1 (ja) | ナノワイヤ電界効果トランジスタ及びその作製方法、並びにこれを含む集積回路 | |
CN109860184A (zh) | 半导体元件 | |
CN109244073B (zh) | 半导体器件结构及其制作方法 | |
WO2011066727A1 (zh) | 混合材料反型模式全包围栅cmos场效应晶体管 | |
US11049857B2 (en) | Nanosheet CMOS semiconductor device and the method of manufacturing the same | |
US20210313326A1 (en) | Transistors in a layered arrangement | |
Valasa et al. | A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications | |
US20210066292A1 (en) | Semiconductor device and manufacturing method thereof | |
TWI686949B (zh) | 半導體元件結構及其製作方法 | |
CN112366204B (zh) | 一种高集成度sram | |
TWI719510B (zh) | 半導體元件結構及其製作方法 | |
CN113658914A (zh) | 场效应晶体管的制造方法 | |
EP4396869A1 (en) | A nanostructure comprising nanosheet or nanowire transistors | |
CN115719706A (zh) | 一种堆叠纳米片gaa-fet器件及其制作方法 | |
CN116825720A (zh) | 一种半导体器件及制造方法 | |
CN114267736A (zh) | 一种堆叠式全栅纳米片器件及其制造方法 | |
CN116825721A (zh) | 一种半导体器件及制造方法 | |
CN115995490A (zh) | 一种半导体器件及其制造方法 |