CN101719501B - 混合晶向反型模式全包围栅cmos场效应晶体管 - Google Patents

混合晶向反型模式全包围栅cmos场效应晶体管 Download PDF

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CN101719501B
CN101719501B CN2009101997242A CN200910199724A CN101719501B CN 101719501 B CN101719501 B CN 101719501B CN 2009101997242 A CN2009101997242 A CN 2009101997242A CN 200910199724 A CN200910199724 A CN 200910199724A CN 101719501 B CN101719501 B CN 101719501B
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raceway groove
around
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CN101719501A (zh
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肖德元
王曦
张苗
陈静
薛忠营
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

本发明公开了一种混合晶向反型模式全包围栅CMOS场效应晶体管，其包括：具有第一沟道的PMOS区域、具有第二沟道的NMOS区域及栅区域，其特征在于：所述的第一沟道及第二沟道的横截面均为腰形(跑道形)，且所述第一沟道采用n型(110)Si材料，所述第二沟道采用p型(100)Si材料；栅区域将所述第一沟道及第二沟道的表面完全包围；在PMOS与NMOS区域之间、PMOS区域或NMOS区域与Si衬底之间均有埋层氧化层将它们隔离。本器件结构简单、紧凑，集成度高，在反型工作模式下，采用不同晶向材料的沟道、跑道形全包围栅结构、高介电常数栅介质和金属栅，具备高载流子迁移率，可避免多晶硅栅耗尽及短沟道效应等。

Description

混合晶向反型模式全包围栅CMOS场效应晶体管
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种混合晶向的反型模式全包围栅CMOS场效应晶体管。
背景技术
互补金属氧化物半导体(CMOS，Complementary Metal Oxide Semiconductor)器件是在将N型金属氧化物半导体晶体管(NMOS)与P型金属氧化物半导体晶体管(PMOS)集成在同一块硅片上的半导体器件。专利申请号为200610028768.5的中国专利公开了一种互补金属氧化物半导体器件。图1为该专利公开的互补金属氧化物半导体器件结构示意图。如图1所示，半导体衬底上形成有第一区域310a、第二区域310b和隔离区305。所述第一区域310a和第二区域310b并排分布，栅极340贯穿所述第一区域310a、隔离区305和第二区域310b。在所述栅极340两侧的第一区域310a、第二区域310b中分别形成源极320、350和漏极330、360。所述栅极340的材料为金属或全金属硅化物，其宽度为2-200nm，所述栅极340下面的导电沟道宽度为5-500nm。该专利的有益效果在于：在第一区域310a形成PMOS，第二区域310b形成NMOS，所述NMOS和PMOS并排分布，共用一个栅极，形成的CMOS呈方形分布，这种共栅极的分布能够有效提高晶片面积利用率。
随着器件尺寸的不断缩小，CMOS技术将常规平面CMOS器件沟道长度按比例继续缩小所面临的日益严重的挑战是如何在控制器件漏电流(Ioff)的同时保持较高的电流驱动能力(Ion)并且阈值电压有很好的稳定性。短沟道效应(SCE)成为所有常规平面CMOS器件按比例进一步缩小所难以逾越的一道障碍，它导致器件特性的退化，为进一步缩小常规平面CMOS器件设置限制。
绝缘体上硅(SOI，Silicon On Insulator)是指以“工程化的”基板代替传 统的体型衬底硅的基板技术，这种基板通常由以下三层构成：薄的单晶硅顶层，在其上形成蚀刻电路；相当薄的埋层氧化层(BOX，buried oxide)，即绝缘二氧化硅中间层；非常厚的体型衬底硅衬底层，其主要作用是为上面的两层提供机械支撑。由于SOI结构中氧化层把其上的硅膜层与体型衬底硅衬底层分隔开来，因此大面积的p-n结将被介电隔离(dielectric isolation)取代。源极(sourceregion)和漏极(drain region)向下延伸至埋层氧化层，有效减少了漏电流和结电容。对于沟道长度以纳米为长度单位的器件来讲，主要由栅极电场来控制沟道电导而不受漏极散射电场影响变得非常重要。对于SOI器件来讲，不管是采用部分耗尽还是全耗尽设计，均可以通过减小硅的厚度改善上述问题。与常规平面CMOS器件相比，基于沟道反型工作模式的双栅或三栅鳍形场效应管具备很好的栅控制及按比例缩小能力，可以作为22nm及以下节点可供选择的器件。其中，反型模式场效应晶体管，其源区和漏区的杂质掺杂类型与沟道杂质掺杂类型不同，导电载流子为少数载流子(少子)，源区和漏区分别于沟道之间存在PN结。此结构器件目前应用最为广泛。
另一方面，在Si材料中，空穴迁移率在(110)Si衬底电流沿<110>晶向流动与传统的(100)Si衬底相比增加一倍以上。而电子迁移率在(100)Si衬底是最高的。为充分利用载流子迁移率依赖于Si表面晶向的优势，IBM公司的Yang等人开发出一种采用混合晶体取向Si衬底制造CMOS电路的新技术。Yang M，leong M，Shi L等人于2003年在《Digest of Technical Paper of InternationalElectron Devices Meeting》杂志上发表的文章《High performance CMOSfabricated on hybrid substrate with different crystal orientations》中介绍了他们的技术。其通过键合和选择性外延技术，NMOS器件制作在具有埋层氧化层的(100)晶面Si表面上，而PMOS器件制作在(110)晶面Si上，PMOS器件性能取得极大提高。当Ioff＝100nA/μm，(110)衬底上的PMOS器件驱动电流提高了45％。其缺点是制作在外延层上的PMOS器件没有埋层氧化层将其与衬底隔离，因而器件性能还是受到影响。在2009年，第54卷，第14期的《科学通报》杂志上，肖德元、王曦、俞跃辉等人发表的名为《一种新型混合晶向积累型圆柱体共包围栅互补金属氧化物场效应晶体管》的文章中提出了一种新型的CMOS器件，该器件工作于积累模式，采用圆柱体全包围栅的结构，其NMOS和PMOS的沟道采用了不同晶向的Si材料，且均具有埋层氧化层将其与衬底隔离。该器件具备较高的载流子迁移率、可避免多晶硅栅耗尽及短沟道效应等优点。
由于沟道的截面形状即全包围栅的形状结构对器件沟道的电完整性有较大影响。鉴于此，本发明为了进一步提升器件性能，提高器件进一步按比例缩小的能力，提出一种新型的工作于反型模式的全包围栅CMOS场效应晶体管，其NMOS和PMOS的沟道的截面形状为跑道形，并采用了不同晶向的Si材料，且均有埋层氧化层将其与衬底隔离。
发明内容
本发明要解决的技术问题在于提供一种混合晶向反型模式全包围栅CMOS场效应晶体管，在反型工作模式下，具有高载流子迁移率，低低频器件噪声，并可避免多晶硅栅耗尽及短沟道效应，增大器件的阈值电压。
为了解决上述技术问题，本发明采用如下技术方案：
一种混合晶向反型模式全包围栅CMOS场效应晶体管，其包括：底层半导体衬底、具有第一沟道的PMOS区域、具有第二沟道的NMOS区域及一个栅区域，其特征在于：
所述第一沟道及第二沟道的横截面均为跑道形，由左右两端的半圆，及中部的与左右两端半圆过渡连接的矩形共同构成，且所述第一沟道采用n型(110)Si材料，所述第二沟道采用p型(100)Si材料；
所述栅区域将所述第一沟道及第二沟道的表面完全包围；
在所述PMOS区域与NMOS区域之间，除栅区域以外，设有第一埋层氧化层；
在所述PMOS区域与所述底层半导体衬底之间或NMOS区域与所述底层半导体衬底之间，除栅区域以外，设有第二埋层氧化层。
进一步地，所述PMOS区域和NMOS区域还包括分别位于其沟道两端的源区及 漏区。其中所述PMOS区域的源区及漏区为重掺杂的p型(110)Si材料或GeSi材料；所述NMOS区域的源区及漏区为重掺杂的n型(100)Si材料或SiC材料。
进一步地，所述第一沟道及第二沟道的长度L均为10-50nm，其横截面左右两端半圆的直径d均为10-80nm，中部矩形的宽度w为10-200nm。
进一步地，所述栅区域包括：将所述第一沟道及第二沟道的表面完全包围的栅介质层以及将所述栅介质层完全包围的栅材料层。
其中，所述的栅材料层为金属或全金属硅化物；所述的栅材料层可以选自钛、镍、钽、钨、氮化钽、氮化钨、氮化钛、硅化钛、硅化钨、硅化镍中的一种或其组合；所述的栅介质层的材料为二氧化硅、氮氧硅化合物、碳氧硅化合物或铪基的高介电常数材料中的一种。
进一步地，所述底层半导体衬底的材料为Si。
进一步地，所述第一埋层氧化层或第二埋层氧化层的厚度均为10-200nm，其材料均为二氧化硅。
本发明的混合晶向反型模式全包围栅CMOS场效应晶体管的有益效果在于：
一方面，其PMOS区域和NMOS区域采用了不同晶向的Si材料，特别是第一沟道采用了n型的(110)Si材料，第二沟道采用了p型的(100)Si材料，在反型模式的CMOS器件中导电载流子为少数载流子(少子)，即第一沟道的导电载流子为n型(110)Si材料中的空穴，第二沟道的导电载流子为p型(100)Si材料中的电子。经过多次的实验表明：空穴迁移率在(110)Si衬底电流沿<110>晶向流动与传统的(100)Si衬底相比增加一倍以上。而电子迁移率在(100)Si衬底是最高的。本发明有针对性的采用两种不同晶向的S i材料，有利于进一步提高其载流子的迁移速率；另一方面，PMOS区域和NMOS区域同时具有埋层氧化层将其与衬底隔离，能有效的减少漏电流，使器件具备更好的性能及进一步按比例缩小的能力。此外，本发明还采用了横截面为腰形(跑道形)的全包围栅沟道结构，如图5所示，其可分解成独立并行工作的一个双栅沟道结构和一个圆柱体全包围栅沟道结构。这种结构的优点在于：暨增大了沟道横截面积(增加了矩形部分)，提高了器件的驱动电流，而同时又保持器件的电完整性(圆形沟道)。
相较于现有技术，本发明的器件结构简单、紧凑，集成度高，在反型工作模式下，采用不同晶向的沟道、跑道形全包围栅结构、高介电常数栅介质和金属栅，具备高载流子迁移率，可避免多晶硅栅耗尽及短沟道效应等。
附图说明
图1为背景技术中互补金属氧化物半导体器件结构示意图。
图2a-2c为本发明实施例一的器件结构示意图：
图2a为俯视图；
图2b为图2a沿XX’的剖面图；
图2c为图2a沿ZZ’方向的剖视图。
图3a-3c为本发明实施例二的器件结构示意图：
图3a为俯视图；
图3b为图3a沿XX’的剖面图；
图3c为图3a沿ZZ’方向的剖视图。
图4为本发明的器件结构沟道部分的立体示意图。
图5为本发明的沟道结构的横截面示意图。
图6a为本发明实施例一中晶体管的俯视图。
图6b为图6a沿XX’的剖视图。
图7a为本发明实施例二中晶体管的俯视图。
图7b为图7a沿XX’的剖视图。
图中标记说明：
100底层半导体衬底    201第一埋层氧化层
202第二埋层氧化层    300NMOS区域
301第二沟道          302NMOS区域的漏区
303NMOS区域的源区    400PMOS区域
401第一沟道          402PMOS区域的漏区
403PMOS区域的源区    500栅区域
501栅介质层          502栅材料层
503绝缘体介质侧墙隔离结构
具体实施方式
下面结合附图进一步说明本发明的器件结构，为了示出的方便附图并未按照比例绘制。
图2a-2c，图3a-3c为本发明器件结构的示意图：图2a为俯视图；图2b为图2a沿XX’的剖面图；图2c为图2a沿ZZ’方向的剖视图。图3a为俯视图；图3b为图3a沿XX’的剖面图；图3c为图3a沿ZZ’方向的剖视图，沿ZZ’方向的剖视图，主要表示的是沟道部分的截面情况。其中，本发明的器件结构可以有两种表示形态，图2a-2c和图3a-3c分别表示了这两种形态。图4为沟道部分的立体形态示意图。图5为沟道的截面示意图。
实施例一
如图2a-2c所示，本实施例的混合晶向反型模式全包围栅CMOS场效应晶体管包括：底层半导体衬底100、具有第一沟道401的PMOS区域400、具有第二沟道301的NMOS区域300及一个栅区域500。所述第一沟道401及第二沟道301的横截面均为腰形(跑道形)，且所述第一沟道401优选为n型(110)Si材料，所述第二沟道301优选为p型(100)Si材料。所述栅区域500将所述第一沟道401及第二沟道301的表面完全包围。其中，所述第一沟道401及第二沟道301横截面的形状，由左右两端的半圆以及中部的与左右两端半圆过渡连接的矩形共同构成。如图5所示，其可分解成独立并行工作的一个双栅沟道结构和一个圆柱体全包围栅沟道结构。其中d为横截面左右两端半圆的直径，w为中部矩形的宽 度，该跑道形横截面的总宽度则为d+w，tox是栅介质层的厚度。
在所述PMOS区域400与NMOS区域300之间，除了栅区域500覆盖的区域以外，还设有第一埋层氧化层201(BOX)将它们隔离，以避免区域之间的相互干扰。在所述NMOS区域300与所述底层半导体衬底100(即Si衬底)之间，除了栅区域500所覆盖的部分以外，还设有第二埋层氧化层202。所述的第二埋层氧化层202可以将所述NMOS区域300或所述PMOS区域400与所述底层半导体衬底100隔离，有效的减少漏电流，从而提高器件性能。
其中，所述PMOS区域400和NMOS区域300还包括分别位于其沟道两端的源区及漏区。PMOS区域的源区403及PMOS区域的漏区402为重掺杂的p型(110)Si材料或GeSi材料；NMOS区域的源区303及NMOS区域的漏区302为重掺杂的n型(100)Si材料或SiC材料。位于下层的源漏区平行于沟道方向的长度大于位于其上层源漏区的长度，使下层的源漏区暴露出来，从而方便电极的引出。参看图2a，所述的源漏区两端垂直于沟道方向的宽度大于沟道的直径，即所述PMOS区域400和NMOS区域300呈中间细两端宽大的鳍形。
请继续参看图2b、2c，所述栅区域500包括：将所述第一沟道401及第二沟道301的表面完全包围的栅介质层501以及将所述栅介质层501完全包围的栅材料层502。其中，所述的栅材料层502为金属或全金属硅化物；所述的金属或全金属硅化物选自钛、镍、钽、钨、氮化钽、氮化钨、氮化钛、硅化钛、硅化钨、硅化镍中的一种或其组合；所述的栅介质层502的材料可以是二氧化硅、氮氧硅化合物、碳氧硅化合物或铪基的高介电常数材料中的一种，优选高介电常数的绝缘介质材料。另外，所述底层半导体衬底100为Si衬底，也可为Ge、Ga、In等其他半导体材料。
在器件尺寸设计上，请参看图2c、图4及图5，所述第一沟道401及第二沟道402长度L为10-50nm，其横截面左右两端半圆的直径d均为10-80nm，中部矩形的宽度W为10-200nm。所述第一埋层氧化层201或第二埋层氧化层202的厚度均为10-200nm，其材料均为二氧化硅。
在上述图2b所示器件结构的基础上，经后续半导体制造工艺即可得到完整 的晶体管。图6a为本实施例晶体管的俯视图，图6b为其剖视图。其中，所述的后续半导体制造工艺包括：在所述栅材料层502上制作栅极、在所述PMOS区域的源区403、NMOS区域的源区303、PMOS区域的漏区402、NMOS区域的漏区302上分别制作源极、漏极。为优化器件性能，栅极两侧还设有绝缘体介质侧墙隔离结构503，其材料可以是二氧化硅、氮化硅等。
实施例二
本发明的另一种表示形态如图3a-3c所示，本实施例的混合晶向反型模式全包围栅CMOS场效应晶体管的器件结构包括：底层半导体衬底100、具有第一沟道401的PMOS区域400、具有第二沟道301的NMOS区域300及一个栅区域500。所述第一沟道401及第二沟道301的横截面均为腰形，由左右两端的半圆，及中部的与左右两端半圆过渡连接的矩形共同构成，且所述第一沟道401优选为n型(110)Si材料，所述第二沟道301优选为p型(100)Si材料。所述栅区域500将所述第一沟道401及第二沟道301的表面完全包围。在所述PMOS区域400与NMOS区域300之间，除了栅区域500覆盖的区域以外，还设有第一埋层氧化层201(BOX)将它们隔离，以避免区域之间的相互干扰。
与实施例一的不同之处在于：在所述NMOS区域300与PMOS区域400之间，除了栅区域500覆盖的区域以外，设有第一埋层氧化层201；在所述PMOS区域400与所述底层半导体衬底100之间，除了栅区域500所覆盖的部分以外，设有第二埋层氧化层202。也就是说本发明的器件结构由上至下可以如实施例一，依次为PMOS区域400、第一埋层氧化层201、NMOS区域300、第二埋层氧化层202及底层半导体衬底100；或如实施例二，依次为NMOS区域300、第一埋层氧化层201、PMOS区域400、第二埋层氧化层202及底层半导体衬底100。除此之外，实施例二与实施例一的其他技术方案相同。
在图3c所示器件结构的基础上，经后续半导体制造工艺即可得到完整的晶体管。图7a为本实施例晶体管的俯视图，图7b为其剖视图。其中，所述的后续半导体制造工艺包括：在所述栅材料层502上制作栅极、在所述PMOS区域的源区403、NMOS区域的源区303、PMOS区域的漏区402、NMOS区域的漏区302上分 别制作源极、漏极。栅极两侧还制备有绝缘体介质侧墙隔离结构503，其材料可以是二氧化硅、氮化硅等。
至此本发明的器件结构介绍完毕，本发明中涉及的其他技术属于本领域技术人员熟悉的范畴，在此不再赘述。
为了进一步分析实施例一及实施例二中器件的性能，本发明采用了较为精准的流体力学模型和量子力学密度渐变模型，考虑并应用了与掺杂以及表面粗糙有关的迁移率退化模型进行三维技术仿真。仿真结果表明本发明的混合晶向反型模式全包围栅CMOS场效应晶体管具备许多常规鳍形场效应管器件(其中包括长方体、圆柱体全包围栅场效应管)所不具备的优点。
由于本发明采用了跑道形全包围栅结构，器件沟道的电完整性得到很大改善，相对于圆柱体全包围栅结构而言，其优点在于：增大了沟道横截面积，提高了器件的驱动电流而同时又保持器件的电完整性。
这使本发明的CMOS管在反型工作模式下，具备高载流子迁移率，低低频器件噪声，并可避免多晶硅栅耗尽及短沟道效应，增大了器件的阈值电压。
上述实施例仅用以说明而非限制本发明的技术方案。任何不脱离本发明精神和范围的技术方案均应涵盖在本发明的专利申请范围当中。

Claims (10)

1.一种混合晶向反型模式全包围栅CMOS场效应晶体管，其包括：底层半导体衬底、具有第一沟道的PMOS区域、具有第二沟道的NMOS区域及一个栅区域，其特征在于：
所述第一沟道及第二沟道的横截面均为跑道形，由左右两端的半圆，及中部的与左右两端半圆过渡连接的矩形共同构成，且所述第一沟道采用n型(110)Si材料，所述第二沟道采用p型(100)Si材料；
所述栅区域将所述第一沟道及第二沟道的表面完全包围；
在所述PMOS区域与NMOS区域之间，除栅区域以外，设有第一埋层氧化层；
在所述PMOS区域与所述底层半导体衬底之间或NMOS区域与所述底层半导体衬底之间，除栅区域以外，设有第二埋层氧化层。
2.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述PMOS区域和NMOS区域还包括分别位于其沟道两端的源区及漏区。
3.根据权利要求2所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述PMOS区域的源区及漏区为重掺杂的p型(110)Si材料或GeSi材料；所述NMOS区域的源区及漏区为重掺杂的n型(100)Si材料或SiC材料。
4.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述第一沟道及第二沟道的长度L均为10-50nm，其横截面左右两端半圆的直径d均为10-80nm，中部矩形的宽度w为10-200nm。
5.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述栅区域包括：将所述第一沟道及第二沟道的表面完全包围的栅介质层以及将所述栅介质层完全包围的栅材料层。 
6.根据权利要求5所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述的栅介质层的材料为二氧化硅、氮氧硅化合物、碳氧硅化合物或铪基的高介电常数材料中的一种。
7.根据权利要求5所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述的栅材料层选自钛、镍、钽、钨、氮化钽、氮化钨、氮化钛、硅化钛、硅化钨或硅化镍中的一种或其组合。
8.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述底层半导体衬底的材料为Si。
9.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述第一埋层氧化层或第二埋层氧化层的厚度均为10-200nm。
10.根据权利要求1所述混合晶向反型模式全包围栅CMOS场效应晶体管，其特征在于：所述第一埋层氧化层或第二埋层氧化层的材料均为二氧化硅。 
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