CN109244073A - 半导体器件结构及其制作方法 - Google Patents
半导体器件结构及其制作方法 Download PDFInfo
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- CN109244073A CN109244073A CN201811023031.3A CN201811023031A CN109244073A CN 109244073 A CN109244073 A CN 109244073A CN 201811023031 A CN201811023031 A CN 201811023031A CN 109244073 A CN109244073 A CN 109244073A
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Abstract
本发明提供一种半导体器件结构及其制作方法,半导体器件结构包括:衬底;半导体沟道,悬空于所述衬底之上;第一半导体层,包围于所述半导体沟道;第二半导体层,包围于所述第一半导体层;栅介质层,包围于所述第二半导体层;以及栅电极层,包围于所述栅介质层;其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度。本发明同时包含二维空穴气的量子阱及二位电子气的量子阱,可以大大提高空穴及电子的迁移率,提高N型场效应晶体管及P型场效应晶体管的电流承载能力,降低电阻及功耗。
Description
技术领域
本发明属于集成电路设计制造,特别是涉及一种三维堆叠的量子阱互补型半导体器件结构及其制作方法。
背景技术
鳍式场效应晶体管(Fin Field-Effect Transistor,FinFET)是一种新的互补式金氧半导体晶体管。FinFET的形状与鱼鳍相,这种设计可以改善电路控制并减少漏电流,缩短晶体管的闸长。
FinFET是源自于传统标准的晶体管—场效应晶体管(Field-Effect Transistor;FET)的一项创新设计。在传统晶体管结构中,栅极只能控制电流在沟道区的一个表面的接通与断开,属于平面的架构。在FinFET的架构中,栅极被设计呈鱼鳍状的3D架构,可于鱼鳍状的栅极的两侧控制电路的接通与断开。这种设计可以大幅改善电路控制并减少漏电流(leakage),也可以大幅缩短晶体管的沟道长度。
在2011年初,英特尔公司推出了商业化的FinFET,使用在其22纳米节点的工艺上,为未来的移动处理器等提供更快,更省电的处理器。从2012年起,FinFET已经开始向20纳米节点和14纳米节点推进。2015年三星率先将FinFET技术用于10nm制程,2016年台积电也将FinFET技术用于10nm制程节点。
作为FinFET技术的一个改进,三面包围栅场效应晶体管可以有效提高场效应晶体管的功率和效率,是最近才开始用于服务器、计算机和设备等领域,三面包围栅场效应晶体管将会是未来几年的主流技术。
随着对器件集成度、功率及性能需求的进一步提高,通过将硅纳米片层叠在一起,可以进一步提高功率和性能。在美国专利US8350298中,肖德元等提出了一种混合晶向积累型全包围栅CMOS场效应晶体管,如图1所示,其包括:底层半导体衬底1010、具有第一沟道401的PMOS区域400、具有第二沟道301的NMOS区域300及一个栅区域500。所述第一沟道401及第二沟道301的横截面均为跑道形。所述栅区域500将所述第一沟道401及第二沟道301的表面完全包围。该器件可避免多晶硅栅耗尽及短沟道效应,增大器件的阈值电压。然而,该器件在沟道电子迁移率上存在较大的限制,该器件依然不能完全满足功率及性能进一步提升的需求。
基于以上所述,提供一种可以进一步提高器件功率及性能的半导体器件结构实属必要。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种半导体器件结构及其制作方法,用于解决现有技术中器件的载流子迁移率较低的问题。
为实现上述目的及其他相关目的,本发明提供一种半导体器件结构,包括:衬底;半导体沟道,悬空于所述衬底之上;第一半导体层,包围于所述半导体沟道;第二半导体层,包围于所述第一半导体层;栅介质层,包围于所述第二半导体层;以及栅电极层,包围于所述栅介质层;其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
优选地,所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
进一步地,所述半导体沟道的材质包含硅,所述第一半导体层的材质包含锗。
进一步地,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
优选地,所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
进一步地,所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
进一步地,所述第一半导体层的材质包含锗,所述第二半导体层的材质包含硅。
进一步地,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
优选地,所述半导体沟道经过圆角化处理而具有圆角矩形的截面形状。
优选地,所述半导体器件结构包括至少两个所述半导体沟道,其中,基于第一半导体沟道形成P型场效应晶体管,基于第二半导体沟道形成N型场效应晶体管,所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极由一共用电极连接,以形成倒相器。
优选地,所述半导体器件结构包括至少两个自所述衬底向上堆叠的N型场效应晶体管以及至少两个自所述衬底向上堆叠的P型场效应晶体管,且相邻两N型场效应晶体管之间及相邻两P型场效应晶体管之间均具有间距。
优选地,所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述共用电极的材质包括Al、W及Cu中的一种。
本发明还提供一种半导体器件结构的制作方法,包括步骤:1)提供一衬底,于所述衬底上形成悬空于所述衬底之上的半导体沟道;2)形成包围于所述半导体沟道的第一半导体层,其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度;3)形成包围于所述第一半导体层的第二半导体层;4)形成包围于所述第二半导体层的栅介质层;以及5)形成包围于所述栅介质层的栅电极层。
优选地,所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
优选地,所述半导体沟道的材质包含硅,所述第一半导体层的材质包含锗。
优选地,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
优选地,所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
优选地,所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
优选地,所述第一半导体层的材质包含锗,所述第二半导体层的材质包含硅。
优选地,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
优选地,步骤1)还包括对所述半导体沟道经过圆角化处理的步骤,使得所述半导体沟道具有圆角矩形的截面形状。
优选地,步骤1)于所述衬底上形成至少两个半导体沟道,步骤5)之后还包括:基于第一半导体沟道形成P型场效应晶体管,以及基于第二半导体沟道形成N型场效应晶体管,并沉积共用电极,所述共用电极连接所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极,以形成倒相器。
优选地,步骤1)于所述衬底上形成至少两个自所述衬底向上堆叠的第一半导体沟道以及至少两个自所述衬底向上堆叠的第二半导体沟道,且相邻两第一半导体沟道之间及相邻两第二半导体沟道之间均具有间距,步骤5)之后还包括:基于第一半导体沟道形成至少两个自所述衬底向上堆叠P型场效应晶体管,以及基于第二半导体沟道形成至少两个自所述衬底向上堆叠N型场效应晶体管,并沉积共用电极,所述共用电极连接所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极,以形成倒相器。
优选地,所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述共用电极的材质包括Al、W及Cu中的一种。
本发明还提供一种半导体器件结构的制作方法,所述制作方法包括:1)提供一衬底,于所述衬底上形成堆叠的若干基体结构层,所述基体结构层包括牺牲层以及位于所述牺牲层上的沟道层;2)刻蚀所述若干基体结构层,以在所述衬底上形成相邻的第一鳍形结构及第二鳍形结构,所述第一鳍形结构包括交替层叠的若干第一牺牲单元及若干第一半导体沟道,所述第二鳍形结构包括交替层叠的若干第二牺牲单元及若干第二半导体沟道;3)选择性去除所述第一鳍形结构中的第一牺牲单元及所述第二鳍形结构中的第二牺牲单元,以获得悬空的若干第一半导体沟道及悬空的若干第二半导体沟道;4)形成包围所述第一半导体沟道及所述第二半导体沟道的第一半导体层,其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度;以及5)形成包围所述第一半导体层的第二半导体层,其中,所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
优选地,所述制作方法还包括:6)形成包围所述第二半导体层的栅介质层;7)形成包围所述栅介质层的栅电极层;以及8)基于所述第一半导体沟道形成P型场效应晶体管,基于所述第二半导体沟道形成N型场效应晶体管,所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极由一共用电极连接,以形成倒相器。
优选地,所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
优选地,所述半导体沟道的材质包含硅,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
优选地,所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
优选地,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
如上所述,本发明的半导体器件结构及其制作方法,具有以下有益效果:
本发明提出了一种三维堆叠结构的全包围栅场效应晶体管结构,可以在单位面积下实现器件的多层堆叠,有效提高器件的集成度,大大提高器件的功率。
本发明通过在硅纳米沟道外先包覆一层第一半导体层,如锗等,使第一半导体层的禁带宽度小于半导体沟道的禁带宽度,形成二维空穴气的量子阱,可以大大提高空穴的迁移率,提高P型场效应晶体管的电流承载能力,降低电阻及功耗;然后在第一半导体层外再包覆一层第二半导体层,如硅等,使得第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,形成二维电子气的量子阱,可以大大提高电子的迁移率,提高N型场效应晶体管的电流承载能力,降低电阻及功耗。
附图说明
图1显示为现有技术中的一种混合晶向积累型全包围栅CMOS场效应晶体管的结构示意图。
图2显示为本发明的三维堆叠的量子阱互补型半导体器件结构的结构示意图。
图3显示为本发明的三维堆叠的量子阱互补型半导体器件结构通过共用电极连接所述N型场效应晶体管及所述P型场效应晶体管所形成结构的电路原理图。
图4显示为本发明的三维堆叠的量子阱互补型半导体器件结构的带隙示意图。
图5~图14显示为本发明的三维堆叠的量子阱互补型半导体器件结构的制作方法各步骤所呈现的结构示意图。
元件标号说明
10 衬底
102 隔离层
20 基体结构层
201 牺牲层
202 沟道层
30 第一鳍形结构
301 第一牺牲单元
302 第一半导体沟道
40 第二鳍形结构
401 第二牺牲单元
402 第二半导体沟道
303、403 第一半导体层
304、404 第二半导体层
305、405 栅介质层
306、406 栅电极层
501、502 量子阱层
60 共用电极
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2~图14。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
如图2所示,本实施例提供一种三维堆叠的量子阱互补型半导体器件结构,包括:衬底101、半导体沟道、第一半导体层303、403、第二半导体层304、404、栅介质层305、405以及栅电极层306、406。
所述衬底101可以为硅衬、碳化硅衬底101、锗硅衬底101等。在本实施例中,所述衬底101为硅衬底101,所述衬底101表面还形成有隔离层102,以隔离衬底101与器件的有源区及后续形成的共用电极60,提高器件的性能。
如图2所示,所述半导体沟道悬空于所述衬底101之上。所述半导体沟道经过圆角化处理而具有圆角矩形的截面形状。所述半导体沟道的材料可以为硅。在本实施例中,所述半导体器件结构包括两个自所述衬底101向上堆叠的第一半导体沟道302,以及两个自所述衬底101向上堆叠的第二半导体沟道402,所述第一半导体沟道302用以形成P型场效应晶体管,所述第二半导体沟道402用以形成N型场效应晶体管。
如图2所示,所述第一半导体层303、403包围于所述半导体沟道,所述第一半导体层303、403的禁带宽度小于所述半导体沟道的禁带宽度,使得所述第一半导体层303、403包含量子阱层501,所述量子阱层501内形成二维空穴气。所述第一半导体层303、403的材质包含锗。例如,所述第一半导体层303、403的材质可以包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。例如,所述锗硅中的锗原子含量可以为50%、60%、75%、85%等,通过调节所述锗硅中的锗原子含量,可以调节其晶格常数、应变程度、禁带宽度以及空穴迁移率等,以满足实际的生产需求。
如图2所示,所述第二半导体层304、404包围于所述第一半导体层303、403。所述第二半导体层304、404的禁带宽度大于所述第一半导体层303、403的禁带宽度,且所述第二半导体层304、404的禁带宽度小于所述半导体沟道的禁带宽度,以使得所述第二半导体层304、404包含量子阱层502,所述量子阱层502内形成二维电子气。
所述第二半导体层304、404的材质包含硅,例如,所述第二半导体层304、404的材质可以为,具有拉伸应变的硅。
如图2所示,所述栅介质层305、405包围于所述第二半导体层304、404。所述栅介质层305、405可以为可以是二氧化硅、氧化铝、氮氧硅化合物、碳氧硅化合物或铪基的等高介电常数材料中的一种。
所述栅电极层306、406包围于所述栅介质层305、405,所述栅电极层306、406包括N型场效应晶体管的栅电极层406以及P型场效应晶体管的栅电极层306,所述P型场效应晶体管的栅电极层306与所述第一半导体沟道302对应设置,所述N型场效应晶体管的栅电极层406与所述第二半导体沟道402对应设置。
所述N型场效应晶体管的栅电极层406的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。
所述P型场效应晶体管的栅电极层306的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。
例如,所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极层306可以具有不同的材质。
如图2所示,所述第一半导体沟道302、依次包围所述第一半导体沟道302的第一半导体层303、第二半导体层304、栅介质层305以及栅电极层306构成P型场效应晶体管,所述第二半导体沟道402、依次包围所述第二半导体沟道402的第一半导体层403、第二半导体层404、栅介质层405以及栅电极层406构成N型场效应晶体管,所述半导体器件结构包括至少两个自所述衬底101向上堆叠的N型场效应晶体管以及至少两个自所述衬底101向上堆叠的P型场效应晶体管,且相邻两N型场效应晶体管之间及相邻两P型场效应晶体管之间均具有间距。所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极由一共用电极60连接,以形成倒相器,所述共用电极60的材质包括Al、W及Cu中的一种。
图3显示为通过共用电极60连接的所述N型场效应晶体管及所述P型场效应晶体管所形成结构的电路原理图。该电路中,所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极相连后作为输入端Vin,所述P型场效应晶体管的源极与电源VDD相连,所述N型场效应晶体管的漏极与所述P型场效应晶体管的漏极相连,并作为输出端Vout,所述N型场效应晶体管的源极接地。
图4显示为本实施例的N型场效应晶体管或所述P型场效应晶体管的带隙示意图,以所述半导体沟道为硅层,所述第一半导体层303、403为具有压缩应变的锗层,所述第二半导体层304、404为具有拉伸应变的硅层,所述栅介质层305、405为二氧化硅层为例,由图4可见,所述锗层的价带能Ev和导带能Ec均高于所述硅层的价带能Ev和导带能Ec,并高于所述具有拉伸应变的硅层的价带能Ev和导带能Ec,以在所述锗层内形成二维空穴气的量子阱层,从而大大提高空穴的迁移率,所述具有拉伸应变的硅的导带能Ec低于所述锗层的导带能Ec及所述二氧化硅层的导带能Ec,以在所述具有拉伸应变的硅层内形成二维电子气的量子阱层,从而大大提高电子的迁移率。
如图5~图14所示,本实施例还提供一种三维堆叠的量子阱互补型半导体器件结构的制作方法,所述制作方法包括:
如图5所示,首先进行步骤1),提供一衬底101,于所述衬底101上形成堆叠的若干基体结构层20,所述基体结构层20包括牺牲层201以及位于所述牺牲层201上的沟道层202。
所述衬底101可以为硅衬、碳化硅衬底101、锗硅衬底101等。在本实施例中,所述衬底101为硅衬底101。然后采用如化学气相沉积法等工艺于所述衬底101上重复形成牺牲层201及沟道层202,所述牺牲层201的材料可以为二氧化硅层,所述沟道层202的材料可以为硅。
在本实施例中,所述牺牲层201的厚度范围可以为10~200纳米,如50纳米、100纳米、150纳米等,所述沟道层202的厚度范围可以为10~100纳米,如25纳米、50纳米、75纳米等。
如图6所示,然后进行步骤2),采用光刻工艺及刻蚀工艺刻蚀所述若干基体结构层20,以在所述衬底101上形成相邻的第一鳍形结构30及第二鳍形结构40,所述第一鳍形结构30包括交替层叠的若干第一牺牲单元301及若干第一半导体沟道302,所述第二鳍形结构40包括交替层叠的若干第二牺牲单元401及若干第二半导体沟道402。所述第一牺牲单元301及第二牺牲单元401为由所述牺牲层201刻蚀而成,所述第一半导体沟道302及所述第二半导体沟道402为由所述沟道层202刻蚀而成。
如图7所示,接着进行步骤3),选择性去除所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401,以获得悬空的若干第一半导体沟道302及悬空的若干第二半导体沟道402。
具体地,采用稀释氢氟酸溶液DHF对所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401进行湿法腐蚀,以选择性去除所述第一鳍形结构30中的第一牺牲单元301及所述第二鳍形结构40中的第二牺牲单元401,以获得悬空的若干第一半导体沟道302及悬空的若干第二半导体沟道402。
如图8所示,接着,对所述半导体沟道经过圆角化处理,使得所述半导体沟道具有圆角矩形的截面形状。具体地,包括:a)采用热氧化工艺对所述第一半导体沟道302及第二半导体沟道402进行氧化,形成包围所述第一半导体沟道302及第二半导体沟道402的热氧化层,所述热氧化工艺的氧化温度可以为800℃~1200℃之间,氧化时间可以为5分钟~8小时之间;b)采用稀释氢氟酸溶液DHF对所述热氧化层进行湿法腐蚀,以将其去除,获得具有圆角矩形(或跑道形)的截面形状的第一半导体沟道302及第二半导体沟道402。
在本实施例中,所述半导体器件结构包括两个自所述衬底101向上堆叠的第一半导体沟道302,以及两个自所述衬底101向上堆叠的第二半导体沟道402,所述第一半导体沟道302用以形成P型场效应晶体管,所述第二半导体沟道402用以形成N型场效应晶体管。
如图9所示,接着进行步骤4),形成包围所述第一半导体沟道302及所述第二半导体沟道402的第一半导体层303、403,其中,所述第一半导体层303、403的禁带宽度小于所述半导体沟道的禁带宽度。
例如,可以采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)形成包围所述第一半导体沟道302及所述第二半导体沟道402的第一半导体层303、403,所述第一半导体层303、403的禁带宽度小于所述第一半导体沟道302及所述第二半导体沟道402的禁带宽度,使得所述第一半导体层303、403包含量子阱层,所述量子阱层内形成二维空穴气。所述第一半导体层303、403的材质包含锗。例如,所述第一半导体层303、403的材质可以包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。例如,所述锗硅中的锗原子含量可以为50%、60%、75%、85%等,通过调节所述锗硅中的锗原子含量,可以调节其晶格常数、应变程度、禁带宽度以及空穴迁移率等,以满足实际的生产需求,同时,所述锗硅中的锗原子含量还能调节后续沉积的具有拉伸应变的硅的应变程度。
如图10所示,接着进行步骤5),形成包围所述第一半导体层303、403的第二半导体层304、404,其中,所述第二半导体层304、404的禁带宽度大于所述第一半导体层303、403的禁带宽度,且所述第二半导体层304、404的禁带宽度小于所述半导体沟道的禁带宽度,以使得所述第二半导体层304、404包含量子阱层,所述量子阱层内形成二维电子气。
例如,可以采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)形成包围所述第一半导体层303、403的第二半导体层304、404,所述第二半导体层304、404的材质包含硅,例如,所述第二半导体层304、404的材质可以为具有拉伸应变的硅。
如图11所示,然后进行步骤6),形成包围所述第二半导体层304、404的栅介质层305、405。
例如,可以采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)形成包围所述第二半导体层304、404的栅介质层305、405。所述栅介质层305、405可以为可以是二氧化硅、氧化铝、氮氧硅化合物、碳氧硅化合物或铪基的等高介电常数材料中的一种。
形成所述栅介质层305、405的同时,于所述衬底101表面形成隔离层102,以隔离衬底101与器件的有源区及后续形成的共用电极60,提高器件的性能。
如图12~图13所示,接着进行步骤7),形成包围所述栅介质层305、405的栅电极层306、406,包括如下步骤:
如图12所示,首先进行步骤7-1),采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)沉积电极材料层,然后仅保留所述第一半导体沟道302外的栅电极层306、406,并作为P型场效应晶体管的栅电极层306,选择性去除其他的栅电极层306、406。
如图13所示,然后进行步骤7-2),采用化学气相沉淀工艺(CVD)或原子层沉积工艺(ALD)沉积电极材料层,然后仅保留所述第二半导体沟道402外的栅电极层306、406,选择性去除其他的栅电极层306、406。
所述N型场效应晶体管的栅电极层406的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。
所述P型场效应晶体管的栅电极层306的材质包括氮化钛(TiN)、氮化钽(TaN)、铝化钛(TiAl)及钛(Ti)中的一种。
例如,所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极层306可以具有不同的材质。
如图14所示,最后进行步骤8),基于所述第一半导体沟道302形成P型场效应晶体管,基于所述第二半导体沟道402形成N型场效应晶体管,所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极由一共用电极60连接,以形成倒相器。
所述第一半导体沟道302、依次包围所述第一半导体沟道302的第一半导体层303、第二半导体层304、栅介质层305以及栅电极层306构成P型场效应晶体管,所述第二半导体沟道402、依次包围所述第二半导体沟道402的第一半导体层403、第二半导体层404、栅介质层405以及栅电极层406构成N型场效应晶体管,所述半导体器件结构包括至少两个自所述衬底101向上堆叠的N型场效应晶体管以及至少两个自所述衬底101向上堆叠的P型场效应晶体管,且相邻两N型场效应晶体管之间及相邻两P型场效应晶体管之间均具有间距。所述N型场效应晶体管的栅电极层406与所述P型场效应晶体管的栅电极由一共用电极60连接,以形成倒相器,所述共用电极60的材质包括Al、W及Cu中的一种。
如上所述,本发明的半导体器件结构及其制作方法,具有以下有益效果:
本发明提出了一种三维堆叠结构的全包围栅场效应晶体管结构,可以在单位面积下实现器件的多层堆叠,有效提高器件的集成度,大大提高器件的功率。
本发明通过在硅纳米沟道外先包覆一层第一半导体层303、403,如锗等,使第一半导体层303、403的禁带宽度小于半导体沟道的禁带宽度,形成二维空穴气的量子阱,可以大大提高空穴的迁移率,提高P型场效应晶体管的电流承载能力,降低电阻及功耗;然后在第一半导体层303、403外再包覆一层第二半导体层304、404,如硅等,使得第二半导体层304、404的禁带宽度大于所述第一半导体层303、403的禁带宽度,形成二维电子气的量子阱,可以大大提高电子的迁移率,提高N型场效应晶体管的电流承载能力,降低电阻及功耗。
所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (30)
1.一种半导体器件结构,其特征在于,包括:
衬底;
半导体沟道,悬空于所述衬底之上;
第一半导体层,包围于所述半导体沟道;
第二半导体层,包围于所述第一半导体层;
栅介质层,包围于所述第二半导体层;以及
栅电极层,包围于所述栅介质层;
其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
2.根据权利要求1所述的半导体器件结构,其特征在于:所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
3.根据权利要求2所述的半导体器件结构,其特征在于:所述半导体沟道的材质包含硅,所述第一半导体层的材质包含锗。
4.根据权利要求3所述的半导体器件结构,其特征在于:所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
5.根据权利要求1所述的半导体器件结构,其特征在于:所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
6.根据权利要求5所述的半导体器件结构,其特征在于:所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
7.根据权利要求6所述的半导体器件结构,其特征在于:所述第一半导体层的材质包含锗,所述第二半导体层的材质包含硅。
8.根据权利要求7所述的半导体器件结构,其特征在于:所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
9.根据权利要求1所述的半导体器件结构,其特征在于:所述半导体沟道经过圆角化处理而具有圆角矩形的截面形状。
10.根据权利要求1~9任意一项所述的半导体器件结构,其特征在于:包括至少两个所述半导体沟道,其中,基于第一半导体沟道形成P型场效应晶体管,基于第二半导体沟道形成N型场效应晶体管,所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极由一共用电极连接,以形成倒相器。
11.根据权利要求10所述的半导体器件结构,其特征在于:包括至少两个自所述衬底向上堆叠的N型场效应晶体管以及至少两个自所述衬底向上堆叠的P型场效应晶体管,且相邻两N型场效应晶体管之间及相邻两P型场效应晶体管之间均具有间距。
12.根据权利要求10所述的半导体器件结构,其特征在于:所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述共用电极的材质包括Al、W及Cu中的一种。
13.一种半导体器件结构的制作方法,其特征在于,包括步骤:
1)提供一衬底,于所述衬底上形成悬空于所述衬底之上的半导体沟道;
2)形成包围于所述半导体沟道的第一半导体层,其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度;
3)形成包围于所述第一半导体层的第二半导体层;
4)形成包围于所述第二半导体层的栅介质层;以及
5)形成包围于所述栅介质层的栅电极层。
14.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
15.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述半导体沟道的材质包含硅,所述第一半导体层的材质包含锗。
16.根据权利要求15所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
17.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
18.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
19.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层的材质包含锗,所述第二半导体层的材质包含硅。
20.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
21.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:步骤1)还包括对所述半导体沟道经过圆角化处理的步骤,使得所述半导体沟道具有圆角矩形的截面形状。
22.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:步骤1)于所述衬底上形成至少两个半导体沟道,步骤5)之后还包括:基于第一半导体沟道形成P型场效应晶体管,以及基于第二半导体沟道形成N型场效应晶体管,并沉积共用电极,所述共用电极连接所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极,以形成倒相器。
23.根据权利要求13所述的半导体器件结构的制作方法,其特征在于:步骤1)于所述衬底上形成至少两个自所述衬底向上堆叠的第一半导体沟道以及至少两个自所述衬底向上堆叠的第二半导体沟道,且相邻两第一半导体沟道之间及相邻两第二半导体沟道之间均具有间距,步骤5)之后还包括:基于第一半导体沟道形成至少两个自所述衬底向上堆叠P型场效应晶体管,以及基于第二半导体沟道形成至少两个自所述衬底向上堆叠N型场效应晶体管,并沉积共用电极,所述共用电极连接所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极,以形成倒相器。
24.根据权利要求22或23所述的半导体器件结构的制作方法,其特征在于:所述N型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述P型场效应晶体管的栅电极层的材质包括TiN、TaN、TiAl及Ti中的一种,所述共用电极的材质包括Al、W及Cu中的一种。
25.一种半导体器件结构的制作方法,其特征在于,包括步骤:
1)提供一衬底,于所述衬底上形成堆叠的若干基体结构层,所述基体结构层包括牺牲层以及位于所述牺牲层上的沟道层;
2)刻蚀所述若干基体结构层,以在所述衬底上形成相邻的第一鳍形结构及第二鳍形结构,所述第一鳍形结构包括交替层叠的若干第一牺牲单元及若干第一半导体沟道,所述第二鳍形结构包括交替层叠的若干第二牺牲单元及若干第二半导体沟道;
3)选择性去除所述第一鳍形结构中的第一牺牲单元及所述第二鳍形结构中的第二牺牲单元,以获得悬空的若干第一半导体沟道及悬空的若干第二半导体沟道;
4)形成包围所述第一半导体沟道及所述第二半导体沟道的第一半导体层,其中,所述第一半导体层的禁带宽度小于所述半导体沟道的禁带宽度;以及
5)形成包围所述第一半导体层的第二半导体层,其中,所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度,且所述第二半导体层的禁带宽度小于所述半导体沟道的禁带宽度。
26.根据权利要求25所述的半导体器件结构的制作方法,其特征在于,还包括:
6)形成包围所述第二半导体层的栅介质层;
7)形成包围所述栅介质层的栅电极层;以及
8)基于所述第一半导体沟道形成P型场效应晶体管,基于所述第二半导体沟道形成N型场效应晶体管,所述N型场效应晶体管的栅电极层与所述P型场效应晶体管的栅电极由一共用电极连接,以形成倒相器。
27.根据权利要求25所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层包含量子阱层,所述量子阱层内形成二维空穴气。
28.根据权利要求27所述的半导体器件结构的制作方法,其特征在于:所述半导体沟道的材质包含硅,所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%。
29.根据权利要求25所述的半导体器件结构的制作方法,其特征在于:所述第二半导体层包含量子阱层,所述量子阱层内形成二维电子气。
30.根据权利要求29所述的半导体器件结构的制作方法,其特征在于:所述第一半导体层的材质包括具有压缩应变的锗及锗硅中的一种,其中,所述锗硅中的锗原子含量不低于50%,所述第二半导体层的材质包括具有拉伸应变的硅。
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