CN108346666A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN108346666A
CN108346666A CN201710058332.9A CN201710058332A CN108346666A CN 108346666 A CN108346666 A CN 108346666A CN 201710058332 A CN201710058332 A CN 201710058332A CN 108346666 A CN108346666 A CN 108346666A
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barrier layer
conductive material
substrate
groove
production method
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CN108346666B (zh
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吴家伟
钟定邦
詹电鍼
詹书俨
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。首先提供一基底，具有一上表面。在基底中形成至少一沟槽，并于沟槽中形成一阻障层以及一导电材料填满该沟槽。接着凹陷导电材料以及阻障层至低于该上表面，然后进行一氧化制作工艺，氧化暴露的导电材料以及阻障层以形成一绝缘层。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，尤其是涉及一种动态随机存取存储器(DRAM)元件及其制作方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)属于一种挥发性存储器，包含由多个存储单元(memory cell)构成的阵列区(array area)以及由控制电路构成的周边区(peripheral area)。各存储单元包含一晶体管(transistor)电连接至一电容器(capacitor)，由该晶体管控制该电容器中电荷的存储或释放来达到存储数据的目的。控制电路通过横跨阵列区并与各存储单元电连接的字符线(word line,WL)与位线(bitline,BL)，可定位至每一存储单元以控制其数据的存取。
随着制作工艺世代演进，为了缩小存储单元尺寸而获得更高的密集度，存储器的结构已朝向三维(three-dimensional)发展。埋入式字符线(buried wordline)结构即是将字符线与晶体管整合制作在基底的沟槽中并且横切各存储单元的主动区，形成沟槽式栅极，不仅可提升存储器的操作速度与密集度，还能避免短通道效应造成的漏电情形。
然而，现有的沟槽式栅极仍存在一些问题。现有为了减少漏极引发漏电(draininduced gate leakage,GIDL)的问题而选择将栅极顶面凹陷至沟槽内更深的位置，但却导致栅极电阻增加或通道区电阻增加，或者选择增加栅极介电层的厚度，但却导致导通电流(on current,Ion)下降并影响到元件开关的速度。因此，如何避免上述漏电问题又不造成其他不良的影响，仍为本领积极研究的课题。
发明内容
本发明一方面提供一种半导体元件的制作方法。首先提供一基底，具有一上表面。在该基底中形成至少一沟槽，并于该沟槽中形成一阻障层以及一导电材料填满该沟槽。接着，凹陷该导电材料以及该阻障层至低于该上表面，然后进行一氧化制作工艺，氧化暴露的该导电材料以及该阻障层以形成一绝缘层。
本发明另一方面提供一种半导体元件，包含一基底，其中包含至少一沟槽。一导电材料，填充该沟槽的一下部。一阻障层，介于该导电材料以及该基底之间。一绝缘层，位于该沟槽中并且完全覆盖该导电材料和该阻障层，其中该绝缘层覆盖该阻障层的部分具有一喙状轮廓。
附图说明
图1为本发明一较佳实施例的半导体元件的顶视布局图；
图2至图7为沿着图1中A-A’切线的剖面示意图，说明本发明较佳实施例的半导体元件的制作方法。
主要元件符号说明
1 半导体元件
100 基底
101 主动区
120 浅沟绝缘结构
102 字符线
104 位线
106 存储节点接触插塞
108 位线接触插塞
100a 上表面
110 垫层
10 沟槽
20、21 栅极介电层
30、31、31’ 阻障层
40、41、41’ 导电材料
31a、31a’ 顶面
41a、41a’ 顶面
50 氧化制作工艺
52 绝缘层
52a 部分
54 盖层
具体实施方式
请参考图1，为本发明一较佳实施例的半导体元件1的顶视布局图。半导体元件1可以是如图所示的动态随机存取存储器2中的控制栅极，具体来说是一种沟槽式栅极。
如图1所示，动态随机存取存储器2包含一基底100，例如是一硅基底或硅覆绝缘(SOI)基底，且基底100中形成有浅沟绝缘结构120，以于基底100上定义出多个主动区101。多条位于基底100中的字符线(word line,WL)102以及多条位于基底100上的位线(bitline,BL)104横跨各主动区101，其中各字符线102与各主动区101重叠的部分形成动态随机存取存储器2的控制栅极，其一侧的主动区101通过存储节点接触插塞106与一电容器(图未示)电连接，另一侧的主动区101则是通过位线接触插塞108与一位线104电连接。通过字符线102来控制该控制栅极通道的开或关，可控制电容器与位线104之间的电连接。
图2至图7为沿着图1中A-A’切线的剖面示意图，用来说明半导体元件1的制作方法。
请参考图2。首先提供基底100，具有一上表面100a。如前所述，基底100中形成有浅沟绝缘结构120，以于基底100中定义出各主动区101。上表面100a上可包含一垫层110，材质例如是氧化硅。垫层110可于后续制作工艺中起到保护基底100的作用。
请参考图3。接着于基底100中形成多条沟槽10。沟槽10的位置即为图1中字符线102的位置，因此沿着A-A’切线的剖视图会包含不同条沟槽10切过主动区101或切过浅沟绝缘结构120的部分。如图3所示，沟槽10的深度会小于浅沟绝缘结构120的深度。形成沟槽10前可包含对基底100进行一离子注入制作工艺，以将具有第一导电型的离子，例如具有P型导电型的硼(B)离子注入基底100中形成具有第一导电型的阱区(图未示)。若基底100中包含阱区，则沟槽10的深度须小于阱区的深度。
请参考图4。接着依序于基底100上形成栅极介电层20和阻障层30，沿着垫层110和沟槽10的底面和侧壁覆盖，然后再于阻障层30上形成导电材料40，完全覆盖阻障层30并填满沟槽10。栅极介电层20可以是利用原子层沉积(atomic layer deposition,ALD)或现场蒸气成长(in-situ steam generation,ISSG)制作工艺形成的氧化硅层或其他介电材料层。阻障层30可包含钛(Ti)、钽(Ta)、氮化钛(TiN)或氮化钽(TaN)等材料，可以是利用原子层沉积制作工艺、化学气相沉积制作工艺(CVD)或物理气相沉积(PVD)形成的单层或多层结构。导电材料40可包含钨(W)、铜(Cu)、铝(Al)、钛(Ti)等材料，但不限于此。
请参考图5。接着可利用化学机械研磨(CMP)制作工艺或回蚀刻制作工艺移除沟槽10外多余的导电材料40、阻障层30和栅极介电层20至显露出垫层110，然后进一步凹陷填充在沟槽10中的导电材料40和阻障层30，至剩余的导电材料41和阻障层31仅填充沟槽10的一下部。导电材料41的顶面41a和阻障层31的顶面31a均低于上表面100a，暴露出覆盖沟槽10上部侧壁的栅极介电层20。导电材料41的顶面41a和阻障层31的顶面31a可以是齐平的，或者，在其他实施例中，阻障层31的顶面31a可略高于或略低于导电材料41的顶面41a。本实施例中覆盖沟槽10上部侧壁的栅极介电层20并未被移除，可于后续制作工艺中作为沟槽10侧壁的保护层。在其他实施例中，覆盖沟槽10上部侧壁的栅极介电层20也会被移除而暴露出沟槽10上侧壁的基底100。
请参考图6。接着，可利用现场蒸气成长(in-situ steam generation,ISSG)制作工艺或顺流式等离子体氧化(downstream plasma oxidation)制作工艺进行一氧化制作工艺50，氧化导电材料41和阻障层31暴露的部分以形成一绝缘层52。氧化制作工艺50包含利用特定比例的氧气及氢气，以对导电材料41和阻障层31具有不同的氧化速率，较佳者，是使阻障层31的氧化速率大于导电材料41的氧化速率，使得氧化制作工艺50中较厚的阻障层31会被氧化，因此氧化制作工艺50后剩余的阻障层31’的顶面31a’会低于剩余的导电材料41’的顶面41a’。根据本发明一实施例，氧化制作工艺50中氢气的比例为氢气和氧气整体的3％至50％之间。若利用现场蒸气成长制作工艺进行氧化制作工艺50，其制作工艺温度较佳介于摄氏950度至摄氏1050度之间。若利用顺流式等离子体氧化制作工艺进行氧化制作工艺50，其制作工艺温度较佳介于摄氏250度至摄氏350度之间。绝缘层52包含阻障层31以及导电材料41的氧化物。绝缘层52完全覆盖在阻障层31’和导电材料41’上，其中绝缘层52覆盖阻障层31’的部分52a具有一喙状轮廓，往阻障层31’和基底100之间延伸。根据本发明一实施例，覆盖沟槽10上侧壁的栅极介电层20甚至被栅极介电层20覆盖的部分基底100也会于氧化制作工艺50被进一步氧化，因此绝缘层52也可能包含栅极介电层20甚至基底100的氧化物。
请参考图7。接着，在沟槽10中形成盖层54，例如一氧化硅层或氮化硅层，以将沟槽10填满至与垫层110齐平，或至少与上表面100a齐平。后续可进行另一离子注入制作工艺以将具有与第一导电型相反的第二导电型的离子，例如具有N型导电型的磷(P)离子或砷(As)离子，注入沟槽10开口两侧的基底100中，形成源/汲区(S/D region)(图未示)，完成本发明的半导体元件1。根据本发明另一实施例，也可选择在形成沟槽10前就形成源/汲区，例如在形成第一导电型的阱区后，接着进行另一离子注入制作工艺注入第二导电型的离子以形成源/汲区。后续，可于源/汲区上形成存储节点接触插塞(图未示)或位线接触插塞(图未示)以与电容器或位于线电连接，在此并不赘述。
本发明的半导体元件1是一种沟槽式栅极，其中位于沟槽10中的导电材料41’是栅极电极，与导电材料41’重叠的沟槽10的侧壁和底部区域的基底100是通道区。本发明直接氧化导电材料41和阻障层31以形成绝缘层52，完全覆盖剩余的导电材料41’和阻障层31’以作为栅极电极的保护层，不仅制作工艺较便捷且成本较低，同时还可利用调整导电材料41和阻障层31的氧化速率使得氧化制成后剩余的阻障层31’的顶面31a’会低于导电材料41’的顶面41a’，因此可减少源/汲区与阻障层31’重叠的机会进而减少发生在栅极边缘处的漏电。另外，绝缘层52具有喙状轮廓的部分52a延伸至阻障层31’和基底100之间，可增加栅极边缘处的栅极介电层21的有效厚度，因此也可减少漏电。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种半导体元件的制作方法，包含:
提供一基底，具有一上表面；
在该基底中形成至少一沟槽；
在该沟槽中形成一阻障层；
在该阻障层上形成一导电材料，填满该沟槽；
凹陷该导电材料以及该阻障层至低于该上表面；以及
进行一氧化制作工艺以氧化部分该导电材料以及该阻障层，形成一绝缘层。
2.如权利要求1所述的制作方法，其中该绝缘层覆盖该阻障层的部分具有一喙状轮廓，往该阻障层以及该基底之间延伸。
3.如权利要求1所述的制作方法，其中该阻障层的氧化速率大于该导电材料的氧化速率。
4.如权利要求1所述的制作方法，其中该氧化制作工艺后，该阻障层的顶面低于该导电材料的顶面。
5.如权利要求1所述的制作方法，其中该阻障层包含钛或氮化钛，该导电材料包含钨。
6.如权利要求1所述的制作方法，其中该氧化制作工艺为现场蒸气成长制作工艺。
7.如权利要求6所述的制作方法，其中该现场蒸气成长制作工艺包含氧气及氢气，其中该氢气的比例介于3％至50％之间。
8.如权利要求6所述的制作方法，其中该现场蒸气成长制作工艺的温度介于摄氏950度至摄氏1050度之间。
9.如权利要求1所述的制作方法，其中该绝缘层包含该阻障层以及该导电材料的氧化物。
10.如权利要求1所述的制作方法，另包含形成一盖层，位于该氧化物层上并填满该沟槽。
11.如权利要求1所述的制作方法，其中另包含形成一栅极介电层，介于该阻障层与该基底之间。
12.一种半导体元件，包含：
基底，包含至少一沟槽；
导电材料，填充该沟槽的一下部；
阻障层，介于该导电材料以及该基底之间；
绝缘层，位于该沟槽中并且完全覆盖该导电材料和该阻障层，其中该绝缘层覆盖该阻障层的部分具有一喙状轮廓。
13.如权利要求12所述的半导体元件，其中该绝缘层具有喙状轮廓的部分往该阻障层以及该基底之间延伸。
14.如权利要求12所述的半导体元件，其中该阻障层的顶面低于该导电材料的顶面。
15.如权利要求12所述的半导体元件，其中该绝缘层包含该阻障层以及该导电材料的氧化物。
16.如权利要求12所述的半导体元件，其中该阻障层包含钛或氮化钛，该导电材料包含钨。
17.如权利要求12所述的半导体元件，其中该基底还包含栅极介电层，介于该阻障层与该基底之间。
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