CN110246842A - 一种制作半导体元件的方法 - Google Patents

一种制作半导体元件的方法 Download PDF

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CN110246842A
CN110246842A CN201810189348.8A CN201810189348A CN110246842A CN 110246842 A CN110246842 A CN 110246842A CN 201810189348 A CN201810189348 A CN 201810189348A CN 110246842 A CN110246842 A CN 110246842A
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groove
layer
amorphous silicon
manufacture craft
substrate
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陈柏均
张家隆
陈意维
刘玮鑫
蔡函原
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to US15/943,717 priority patent/US10903328B2/en
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Abstract

本发明公开一种制作半导体元件的方法，其主要先形成一凹槽于一基底内，然后形成一非晶硅层于凹槽内，接着进行一氧化制作工艺将非晶硅层转换为一氧化硅层，再依序形成一阻障层以及导电层于凹槽内以形成一栅极结构。

Description

一种制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存取存储器(Dynamic Random Access Memory,DRAM)元件的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明公开一种制作半导体元件的方法，其主要先形成一凹槽于一基底内，然后形成一非晶硅层于凹槽内，接着进行一氧化制作工艺将非晶硅层转换为一氧化硅层，再依序形成一阻障层以及导电层于凹槽内以形成一栅极结构。
依据本发明一实施利，氧化制作工艺较佳包含一现场蒸气成长(in-situ steamgeneration,ISSG)制作工艺，另外阻障层较佳包含氮化钛，而导电层则较佳包含钨。
附图说明
图1为本发明一实施例的动态随机存取存储器元件的上视图；
图2至图4为图1中沿着切线A-A’方向制作动态随机存取存储器元件的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线
14 字符线 16 基底
18 主动区(有源区) 20 存储器区
22 栅极 24 浅沟绝缘
26 第一凹槽 28 第二凹槽
30 非晶硅层 32 现场蒸气成长制作工艺
34 氧化硅层 36 阻障层
38 导电层 40 第一栅极结构
42 第二栅极结构 44 硬掩模
具体实施方式
请参照图1至图4，图1至图4为本发明优选实施例制作一动态随机存取存储器元件的方法示意图，其中图1为俯视图，图2至图4则显示图1中沿着切线A-A’方向制作动态随机存取存储器元件的剖视图。整体而言，本实施例是提供一存储器元件，例如是具备凹入式栅极的动态随机存取存储器元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示，动态随机存取存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(active area,AA)18。此外，基底16上还定义有一存储器区20以及一周边区(图未示)。其中，动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)12较佳形成于存储器区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储器区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向，例如Y方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线12是相互平行地形成在基底16上沿着一第三方向，例如X方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向，并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此都不同，且第一方向与第二方向及第三方向都不垂直。此外，字符线14两侧的主动区18内较佳设有接触插塞，例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋藏式字符线)的制作进行说明。首先如图2所示，先于基底16内形成第一凹槽26与第二凹槽28且第一凹槽26底部设有浅沟隔离24，其中浅沟隔离24上表面较佳略低于第二凹槽28底部或下表面。在本实施例中，第一凹槽26、第二凹槽28以及浅沟隔离24的制作可先去除部分基底16形成由例如氧化硅所构成的浅沟隔离24于基底16内且浅沟隔离24上表面较佳切齐基底16上表面，然后利用蚀刻同时去除部分浅沟隔离24以及部分浅沟隔离24旁的基底16形成凹槽，其中剩余的浅沟隔离24正上方的凹槽即为第一凹槽26而去除部分基底16后所形成的凹槽即为第二凹槽28。
接着进行一原子层沉积(atomic layer deposition,ALD)制作工艺或化学气相沉积(chemical vapor deposition,CVD)制作工艺形成一非晶硅层30于各凹槽内以及基底16表面。在本实施例中，非晶硅层30较佳填入第一凹槽26以及第二凹槽28内但不填满各凹槽，其中填入第一凹槽26内的非晶硅层30较佳设于第一凹槽26侧壁以及浅沟隔离24上表面，而填入第二凹槽28内的非晶硅层30则较佳设于第二凹槽28侧壁以及第二凹槽28底部。另外本实施例分别形成于第一凹槽26以及第二凹槽28内的非晶硅层30厚度较佳介于5埃至30埃或更佳约15埃。
随后如图3所示，进行一氧化制作工艺或更具体而言一现场蒸气成长(in-situsteam generation,ISSG)制作工艺32将非晶硅层30转换为一氧化硅层34作为后续所制作栅极结构的栅极介电层。更具体而言，本实施例较佳于现场蒸气成长制作工艺32时通入氧气，使氧气与非晶硅层30反应形成氧化硅层34但并不与任何由硅所构成的基底16反应，其中所形成的氧化硅层34即取代原本非晶硅层30的位置。换句话说，本实施例较佳在不消耗任何基底16的情况下控制所通入的氧气流量使所有的非晶硅层30与氧气反应形成氧化硅层34，因此将非晶硅层30转换为氧化硅层34后所有的非晶硅层30较佳被消耗殆尽且无任何非晶硅层30留下，而所形成的氧化硅层34则较佳取代原本非晶硅层30的位置且与原本的非晶硅层30具有相同厚度，亦即具有约略介于5埃至30埃或更佳约15埃的厚度。
需注意的是，本实施例虽较佳在进行现场蒸气成长制作工艺32时在不消耗任何由硅所构成的基底16情况下仅将非晶硅层30转换为氧化硅层34，但不局限于此方式，依据本发明一实施利又可选择将所有非晶硅层30转换为氧化硅层34之后再将一小部分的基底16与氧气反应并转换为氧化硅层34。换句话说，依据此方式所形成的氧化硅层34厚度可能比原本非晶硅层30的厚度略微增加例如5％至10％，此实施例也属本发明所涵盖的范围。
然后如图4所示，依序沉积一阻障层36以及一导电层38于氧化硅层34上，接着进行一回蚀刻制作工艺去除部分导电层38以及部份阻障层36，使剩余的导电层38以及阻障层36略低于基底16上表面以形成第一栅极结构40于第一凹槽26内以及第二栅极结构42于第二凹槽28内，其中第一栅极结构40以及第二栅极结构42即构成图1的位线12。之后再形成一硬掩模44于第一栅极结构40与第二栅极结构42上方，并使硬掩模44上表面切齐基底12上表面。
在本实施例中，阻障层36可依据制作工艺或产品需求选用N型功函数金属层或P型功函数金属层，其中N型功函数金属层可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限。另外P型功函数金属层可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。导电层38可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。硬掩模44则较佳由例如氮化硅等介电材料所构成。
之后可依据制作工艺需求进行一离子注入制作工艺，以于第一栅极结构40或第二栅极结构42两侧的基底16内形成一掺杂区(图未示)，例如一轻掺杂漏极或源极/漏极区域。最后进行接触插塞制作工艺，例如可分别于第二栅极结构42两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线，以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
综上所述，本发明主要在制备动态随机存取存储器元件的字符线时先形成一非晶硅层于凹槽内，然后进行一现场蒸气成长制作工艺将非晶硅层转换为氧化硅层，之后再填入阻障层以及导电层形成栅极或字符线结构。由于本发明较佳以沉积非晶硅层的方式取代现有以ALD制作工艺沉积氧化硅层的步骤，因此后续进行现场蒸气成长制作工艺时所通入的氧气便不致与硅基底反应形成氧化硅而消耗过多的基底，如此除了可提升氧化硅层的整体强度外又可大幅改善线宽的控制。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (6)

1.一种制作半导体元件的方法，其特征在于，包含：
形成一凹槽于一基底内；
形成一非晶硅层于该凹槽内；
进行一氧化制作工艺将该非晶硅层转换为一氧化硅层；以及
形成一阻障层于该凹槽内。
2.如权利要求1所述的方法，其中该氧化制作工艺包含一现场蒸气成长(in-situsteam generation,ISSG)制作工艺。
3.如权利要求1所述的方法，另包含于形成该阻障层之后形成一导电层于该凹槽内以形成一栅极结构。
4.如权利要求1所述的方法，另包含：
形成一浅沟隔离于该基底内；
去除部分该浅沟隔离以形成该凹槽；
形成该非晶硅层于该凹槽内并位于该浅沟隔离上；以及
进行该氧化制作工艺以形成该氧化硅层于该浅沟隔离上。
5.如权利要求1所述的方法，其中该非晶硅层的厚度介于5埃至30埃。
6.如权利要求1所述的方法，其中该阻障层包含氮化钛。
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