CN109659275B - 动态随机存取存储器的制作方法 - Google Patents

动态随机存取存储器的制作方法 Download PDF

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CN109659275B
CN109659275B CN201710933813.XA CN201710933813A CN109659275B CN 109659275 B CN109659275 B CN 109659275B CN 201710933813 A CN201710933813 A CN 201710933813A CN 109659275 B CN109659275 B CN 109659275B
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CN109659275A (zh
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吴姿锦
刘照恩
张景翔
陈意维
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种动态随机存取存储器的制作方法，包含提供一基底，然后，形成一第一掩模层，其中形成第一掩模层的步骤包含先形成一含氢氮化硅层，再形成一氧化硅层覆盖并接触含氢氮化硅层，其中含氢氮化硅层的化学式为SixNyHz，X的数值介于4至8之间、Y的数值介于3.5至9.5之间、Z的数值等于1，然后图案化第一掩模层以形成一图案化第一掩模层，接着以图案化第一掩模层为掩模，蚀刻基底以形成一字符线沟槽，然后完全移除图案化第一掩模层，最后形成一字符线于字符线沟槽。

Description

动态随机存取存储器的制作方法
技术领域
本发明涉及一种动态随机存取存储器的制作方法，特别是涉及一种避免字符线断裂的制作方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)属于一种挥发性存储器，其是由多个存储单元构成。每一个存储单元主要是由一个晶体管与一个由晶体管所操控的电容所构成，且每一个存储单元通过字符线与位线彼此电连接。
为提高动态随机存取存储器的集成度以加快元件的操作速度，以及符合消费者对于小型化电子装置的需求，近年来发展出埋入式字符线(buried word line)，以满足上述种种需求。在制作埋入式字符线时，需要形成字符线沟槽，使用传统制作工艺所形成的字符线沟槽经常发生字符线沟槽断裂或是同一条字符线沟槽宽度不一的情况，如此将会造成后续所形成的字符线的电性问题。
发明内容
有鉴于此，本发明提供一种避免字符线沟槽缺陷的制作方法。
根据本发明的一优选实施例，一种动态随机存取存储器的制作方法，包含提供一基底，然后，形成一第一掩模层，其中形成第一掩模层的步骤包含先形成一含氢氮化硅层，再形成一氧化硅层覆盖并接触该含氢氮化硅层，其中含氢氮化硅层的化学式为SixNyHz，X的数值介于4至8之间、Y的数值介于3.5至9.5之间、Z的数值等于1，然后图案化第一掩模层以形成一图案化第一掩模层，接着以图案化第一掩模层为掩模，蚀刻基底以形成一字符线沟槽，然后完全移除图案化第一掩模层，最后形成一字符线于字符线沟槽。
附图说明
图1至图7为本发明的优选实施例所绘示的动态随机存取存储器的制作方法的示意图。
主要元件符号说明
10 基底 12 半导体基底
14 保护层 16 浅沟槽绝缘
18 掺杂区 20 第二掩模层
22 第一掩模层 24 含氢氮化硅层
26 氧化硅层 28 字符线沟槽
30 栅极介电层 32 字符线
34 功函数层 36 帽盖层
38 层间介电层 40 位线插塞
42 电容插塞 44 电容
100 动态随机存取存储器 118 源极/漏极掺杂区
120 图案化第二掩模层 122 图案化第一掩模层
具体实施方式
图1至图7为根据本发明的优选实施例所绘示的动态随机存取存储器的制作方法。如图1所示，首先提供一基底10，基底10包含一半导体基底12以及选择性包含一保护层14，半导体基底10可能为一硅基底或一硅锗基底，保护层14可以例如为氧化硅、氮化硅、氮氧化硅或是其它绝缘材料，根据本发明的优选实施例，保护层14的厚度较佳介于470埃(angstrom)至580埃之间，半导体基底12上设置有至少一浅沟槽绝缘16以在半导体基底12中定义出主动区域，然后进行一离子注入制作工艺，在半导体基底12中形成一掺杂区18，所注入的掺质可以为N型掺质或是P型掺质。
如图2所示，形成一第二掩模层20覆盖保护层14，第二掩模层20可以为一先进曝光图样薄膜(advanced patterning film,APF)或是其它掩模材层，例如氧化硅、氮化硅或是氮氧化硅等，然后形成一第一掩模层22覆盖第二掩模层20，第一掩模层22包含一含氢氮化硅层(hydrogen-contain silicon nitride)24和一氧化硅层26，其中先形成含氢氮化硅层24才形成氧化硅层26，根据本发明的优选实施例，第二掩模层20的厚度介于1350埃至1650埃之间，含氢氮化硅层24的厚度介于630埃至700埃之间，氧化硅层26的厚度介于380埃至460埃之间。
一般而言，在含氢氮化硅层24中的硅原子和氢原子之间会形成悬挂键(danglingbond)，在形成氧化硅层26时，氧化硅层26中的氧原子会和这些悬挂键产生反应，造成氧化硅层26的表面粗糙，也就是说在含氢氮化硅层24中若是有越多的氢原子，后续氧化硅层26的表面就会越粗糙。因此为了避免在氧化硅层26产生粗糙，本发明的含氢氮化硅层24特别控制氢含量，详细来说含氢氮化硅层24的化学式为SixNyHz，X的数值介于4至8之间、Y的数值介于3.5至9.5之间、Z的数值等于1，根据本发明的优选实施例，形成含氢氮化硅层24是利用沉积制作工艺形成，例如：原子层沉积(Atomic Layer Deposition,ALD)、化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)等，沉积制作工艺的步骤包含：将半导体基底12放入一腔室(图未示)，接着在腔室内通入硅甲烷和氨作为前驱物以形成含氢氮化硅层24，硅甲烷的流量介于22.5至27.5每分钟标准毫升(standard cubic centimeter per minute,sccm)之间，氨流量介于45至55每分钟标准毫升之间，此外沉积制作工艺的操作温度介于360至440度之间，操作压力介于5.4至6.6托耳(torr)之间，操作功率介于72至88瓦特(walt)之间。在形成含氢氮化硅层24之后，形成一氧化硅层26覆盖含氢氮化硅层24，氧化硅层26较佳利用原子层沉积、化学气相沉积、物理气相沉积。由于含氢氮化硅层24的氢原子含量控制在一定的比例之下，在本实施例中所形成的氧化硅层26其表面平坦。
如图3所示，图案化第一掩模层22以形成一图案化第一掩模层122，图案化第一掩模层122的步骤可包含形成一光致抗蚀剂(图未示)覆盖第一掩模层22，接着利用曝光显影步骤，图案化光致抗蚀剂，在光致抗蚀剂上形成字符线沟槽的图案，由于本发明的氧化硅层26的表面平坦，因此形成在氧化硅层26上的光致抗蚀剂表面也是平坦的，如此，曝光显影步骤后所形成的图案化后的光致抗蚀剂才不会扭曲，然后经由一蚀刻步骤，将光致抗蚀剂上的图案转印到第一掩模层22，使得第一掩模层22转变为图案化第一掩模层122，此时平坦的氧化硅层26的表面，可以使光致抗蚀剂上的图案准确地转印到第一掩模层22上，之后将光致抗蚀剂移除。
如图4所示，以图案化第一掩模层122为掩模，蚀刻第二掩模层20，以形成一图案化第二掩模层120。如第5图所示，移除图案化第一掩模层122，然后以图案化第二掩模层120为掩模，蚀刻保护层14、半导体基底12和浅沟槽绝缘16，以在半导体基底12和浅沟槽绝缘16中形成字符线沟槽28，在本实施中以形成三个字符线沟槽28为例，字符线沟槽28将掺杂区18分为多个源极/漏极掺杂区118，源极/漏极掺杂区118分别在一个字符线沟槽28的两侧。
如图6所示，移除图案化第二掩模层120，接着形成一栅极介电层30于字符线沟槽28的侧壁和底部，栅极介电层30可以为氧化硅、氮氧化硅、氮化硅或高介电常数等，栅极介电层30可以利用氧化制作工艺或是沉积制作工艺形成，接着，形成一字符线32和一功函数层34于字符线沟槽28的下半部。形成字符线32和功函数层34的步骤包含：形成功函数材料层顺应地覆盖栅极介电层30，然后再形成一导电层填入字符线沟槽28，之后回蚀刻功函数材料层和导电层直到移除位于字符线沟槽28上半部的功函数材料层和导电层，余留在字符线沟槽28的下半部的功函数材料层则作为功函数层34，余留在字符线沟槽28的下半部的导电层，则作为字符线32。功函数层34可以为氮化钛、氮化钽或氮化钨(WN)等，字符线32包含钨、铜或铝等其它导电材料。
如图7所示，形成一帽盖层36填入在字符线沟槽28的上半部中，帽盖层36可以为氮化硅或是其它绝缘材料，之后形成一层间介电层38、位线插塞40、电容插塞42和电容44，至此本发明的一动态随机存取存储器100业已完成，其中电容插塞42电连接电容44和一源极/漏极掺杂区118，而位线插塞40电连接另一源极/漏极掺杂区118。
本发明采用特殊比例的含氢氮化硅层，降低氢原子在含氢氮化硅层中的比例，因此含氢氮化硅层中氢原子和硅原子之间所形成的悬挂键数量下降，如此一来，就降低氧化硅层中氧原子和悬挂键产生反应的机率，所以可以避免氧化硅层的表面粗糙的现象，平坦的氧化硅层表面有助于准确形成字符线沟槽。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (6)

1.一种动态随机存取存储器的制作方法，包含：
提供一基底；
形成一第一掩模层，其中形成该第一掩模层的步骤包含：
形成一含氢氮化硅层覆盖该基底，以及形成一氧化硅层覆盖并接触该含氢氮化硅层，其中该含氢氮化硅层的化学式为SixNyHz，X的数值介于4至8之间、Y的数值介于3.5至9.5之间、Z的数值等于1；
图案化该第一掩模层以形成一图案化第一掩模层；
以该图案化第一掩模层为掩模，蚀刻该基底以形成一字符线沟槽；
完全移除该图案化第一掩模层；以及
形成一字符线于该字符线沟槽。
2.如权利要求1所述的动态随机存取存储器的制作方法，其中该基底包含一半导体基底和一第二掩模层覆盖该半导体基底。
3.如权利要求2所述的动态随机存取存储器的制作方法，其中形成该字符线沟槽的步骤包含：
以该图案化第一掩模层为掩模，蚀刻该第二掩模层以形成一图案化第二掩模层；
移除该图案化第一掩模层；
以该图案化第二掩模层为掩模，蚀刻该半导体基底以形成该字符线沟槽；以及
移除该图案化第二掩模层。
4.如权利要求1所述的动态随机存取存储器的制作方法，另包含：
在形成该第一掩模层之前，形成一掺杂区于该基底内；
在形成该字符线后，形成一电容插塞接触该掺杂区；
在形成该字符线后，形成一电容于该基底上以完成该动态随机存取存储器，其中该电容通过该电容插塞电连接该掺杂区。
5.如权利要求1所述的动态随机存取存储器的制作方法，其中形成该含氢氮化硅层是利用沉积制作工艺形成，该沉积制作工艺包含：以硅甲烷和氨作为前驱物以形成该含氢氮化硅层，硅甲烷的流量介于22.5至27.5每分钟标准毫升之间，氨流量介于45至55每分钟标准毫升之间。
6.如权利要求5所述的动态随机存取存储器的制作方法，其中该沉积制作工艺的操作温度介于360至440度之间，操作压力介于5.4至6.6托耳之间，操作功率介于72至88瓦特之间。
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