CN108346665B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN108346665B
CN108346665B CN201710058125.3A CN201710058125A CN108346665B CN 108346665 B CN108346665 B CN 108346665B CN 201710058125 A CN201710058125 A CN 201710058125A CN 108346665 B CN108346665 B CN 108346665B
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trench
conductive material
substrate
semiconductor device
barrier layer
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CN108346665A (zh
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陈凯评
冯立伟
游奎轩
叶秋显
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。首先提供一基底，并于基底中形成至少一沟槽。形成一导电材料填充沟槽后，移除部分导电材料至暴露出基底的上表面和沟槽的顶角和上侧壁。接着进行一掺杂制作工艺，以沿着基底的上表面、沟槽的顶角和上侧壁形成一倒L型的掺杂区。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，尤其是涉及一种动态随机存取存储器(DRAM)元件及其制作方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)属于一种挥发性存储器，包含由多个存储单元(memory cell)构成的阵列区(array area)以及由控制电路构成的周边区(peripheral area)。各存储单元包含一晶体管(transistor)电连接至一电容器(capacitor)，由该晶体管控制该电容器的电荷存储或释放来达到存储数据的目的。控制电路通过横跨阵列区并与各存储单元电连接的字符线(word line,WL)与位线(bit line,BL)，可定位至每一存储单元以控制其数据的存取。
随着制作工艺世代演进，为了缩小存储单元尺寸而获得更高的密集度，存储器的结构已朝向三维(three-dimensional)发展。埋入式字符线(buried wordline)结构即是将字符线与晶体管整合制作在基底的沟槽中并且横切各存储单元的主动区，形成沟槽式栅极，不仅可提升存储器的操作速度与密集度，还能避免短通道效应造成的漏电情形。
然而，现有的沟槽式栅极仍存在一些缺陷。现有的平面式栅极通过形成轻掺杂区(LDD region)和间隙壁以拉开源/漏区(S/D region)与栅极的距离，避免源/漏区扩散至与栅极重叠而导致漏极引发漏电(drain induced gate leakage,GIDL)问题。但是，目前沟槽式栅极的轻掺杂区和源/漏区是以离子注入的方法形成在紧邻沟槽开口两侧的基底中，容易往深处扩散而与栅极重叠导致严重的漏电问题。因此，如何避免上述漏电问题，提升沟槽式栅极的效能，仍为本领积极研究的课题。
发明内容
本发明一方面提供一种半导体元件的制作方法，步骤包含提供一基底，具有一上表面。在该基底中形成至少一沟槽，并形成一导电材料填充该沟槽。移除部分该导电材料至其顶面低于该上表面，暴露出该上表面以及该沟槽的顶角和上侧壁。接着进行一掺杂制作工艺，在暴露的该上表面、该沟槽的顶角和上侧壁形成一倒L型的掺杂区，其中，该掺杂制作工艺较佳为等离子体掺杂制作工艺(PLAD)。
本发明另一方面提供一种半导体元件，包含一基底，具有一上表面。至少一沟槽位于该基底中。一导电材料，位于该沟槽中，其中该导电材料的顶面低于该上表面，暴露出该沟槽的顶角和上侧壁。一倒L型的掺杂区位于该沟槽的顶角，包含一水平部沿着该上表面延伸，以及一垂直部沿着该沟槽的上侧壁延伸。
附图说明
图1至图6为本发明第一实例的半导体元件的制作方法剖面示意图；
图7至图10为本发明第二实例的半导体元件的制作方法剖面示意图。
主要元件符号说明
1、2 半导体元件
100 基底
100a 上表面
110 阱区
10 沟槽
10a 顶角
10b 上侧壁
20、21 栅极介电层
30、31 阻障层
40、41 导电材料
21a、31a、41a 顶面
60 掺杂制作工艺
62 掺杂区
62a 水平部
62b 垂直部
63 扩散区
50 绝缘层
52、54 盖层
70 离子注入制作
工艺
72 源/漏区
具体实施方式
图1至图6为本发明第一实例的半导体元件1的制作方法剖面示意图。半导体元件1例如是一动态随机存取存储器的沟槽式栅极。
请参考图1。首先，提供基底100，例如是一硅基底或硅覆绝缘(SOI)基底。然后进行一离子注入制作工艺，将具有第一导电型的离子，例如具有P导电型的硼(B)离子，自基底100的上表面100a注入至基底100中，形成具有第一导电型的阱区110。接着进行一图案化制作工艺以于基底100中形成至少一沟槽10，其深度小于阱区110的深度并且完全被阱区110包围。形成沟槽10的方法可包含于基底100上形成一图案化掩模层(图未示)，例如一图案化光致抗蚀剂层，然后利用该图案化掩模层为蚀刻掩模对基底100进行蚀刻以形成沟槽10。根据一较佳实施例，基底100的上表面100a包含一硬掩模层(图未示)，可将该图案化掩模层的图案转移至该硬掩模层后，再以该硬掩模层作为蚀刻硬掩模对基底100进行蚀刻。
请参考图2。接着依序于基底100上形成栅极介电层20和阻障层30，沿着基底100的上表面100a和沟槽10的底面和侧壁覆盖，然后再于基底100上形成导电材料40并填满各沟槽10。栅极介电层20可以是利用原子层沉积(atomic layer deposition,ALD)制作工艺或现场蒸气成长(in-situ steam generation,ISSG)制作工艺形成的氧化硅层或其他介电材料层。阻障层30可包含钛(Ti)、钽(Ta)、氮化钛(TiN)或氮化钽(TaN)等材料，可以是利用原子层沉积制作工艺或化学气相沉积制作工艺形成的单层或多层结构。导电材料40可包含钨(W)、铜(Cu)、铝(Al)、钛(Ti)等材料，但不限于此。
请参考图3。接着可利用化学机械研磨(CMP)制作工艺或回蚀刻制作工艺移除沟槽10外多余的导电材料40、阻障层30和栅极介电层20至暴露出基底100的上表面100a，然后进一步移除填充在沟槽10上部的部分导电材料40并移除覆盖沟槽10的上侧壁10b的阻障层30和栅极介电层20，以暴露出沟槽10的顶角10a和上侧壁10b。沟槽10中剩余的导电材料41的顶面41a、阻障层31的顶面31a和栅极介电层21的顶面21a大致上齐平，并且都低于上表面100a。根据本发明一实施例，可选择性保留覆盖上侧壁10b的栅极介电层20，以于后续制作工艺中作为上侧壁10b的保护层。
请参考图4。接着，可选择性地于沟槽10中形成一低于上表面100a的绝缘层50，例如一氧化硅层或氮化硅层，完全覆盖导电材料41、阻障层31和栅极介电层21，然后进行一掺杂制作工艺60，较佳是一等离子体掺杂(plasma doping,PLAD)制作工艺，以将具有与第一导电型相反的第二导电型的离子，例如具有N导电型的磷(P)或砷(As)离子，注入暴露的上侧壁10b、顶角10a和上表面100a中的浅层区域，形成一倒L型的掺杂区62，与阱区110直接接触。掺杂区62包含一水平部62a，是沿着上表面100a延伸并且其底面高于阻障层31的顶面31a，以及一垂直部62b，是沿着上侧壁10b延伸。较佳者，垂直部62b的底面会与阻障层31的顶面31a切齐。掺杂制作工艺60后可选择性地进行一回火制作工艺(anneal)以活化掺杂区62中的离子。上述回火制作工艺可能使垂直部62b中的部分离子沿着沟槽10的侧壁些微往下扩散，因此形成一低于阻障层31的顶面31a的扩散区63。
请参考图5。接着于沟槽10中形成盖层52，例如一氧化硅层或氮化硅层，以将沟槽10填满，完成本发明第一实施例的半导体元件1。半导体元件1可以是一动态随机存取存储器的沟槽式栅极，其中位于沟槽10中的导电材料41是栅极电极，与导电材料41重叠的沟槽10的侧壁和底部区域的基底100是通道区，位于沟槽10开口两侧的掺杂区62是源/漏区(S/Dregion)。相邻的两半导体元件1的掺杂区62可彼此连接而形成一倒U型的掺杂区。
请参考图6，根据本发明另一实施例，掺杂区62是作为半导体元件1的轻掺杂区(LDD region)，其包含的离子浓度相较于作为源/漏区时低，例如介于十分之一或百分之一之间，因此形成盖层52后还包含进行一离子注入制作工艺70，注入更多具有第二导电型的离子以形成源/漏区72。可通过控制离子注入制作工艺70的能量使源/漏区72的深度等于或较佳小于垂直部62b的深度，避免源/漏区72与阻障层31重叠而造成漏电。
本发明特征之一在于，利用等离子体掺杂(PLAD)制作工艺于暴露的基底表面和沟槽侧壁形成一倒L型的浅层的掺杂区，作为沟槽式栅极的轻掺杂区或源/漏区。相较于现有离子束离子注入的方法，本发明的方法形成的掺杂区不仅浓度分布均匀，也较不易扩散，可减少发生在栅极电极与源/漏区重叠处的漏电。此外，由于倒L型的掺杂区的垂直部会延伸至与通道区接壤，因此即使后续以额外的离子注入制作工艺形成源/漏区(图6所示实施例)，也可采用较低的能量以形成较浅的源/漏区以确保不会扩散至与阻障层重叠而产生漏电。
图7至图10，为根据本发明第二实例的半导体元件2的制作方法剖面示意图。
请参考图7，类似的，形成沟槽10并依序形成栅极介电层和阻障层并形成导电材料填充沟槽10后，移除沟槽10外多余的导电材料、阻障层和栅极介电层，并进一步移除填充沟槽10上部的部分导电材料、阻障层和栅极介电层至剩余的导电材料41的顶面41a、阻障层31的顶面31a和栅极介电层21的顶面21a都低于基底100的上表面100a。与前文所述第一实施例不同处在于，阻障层31和栅极介电层21的顶面31a和21a是低于导电材料41的顶面41a。
请参考图8，接着，进行一掺杂制作工艺60，较佳是一等离子体掺杂(plasmadoping,PLAD)制作工艺，以将第二导电型的离子注入暴露的上侧壁10b、顶角10a和上表面100a，形成倒L型的掺杂区62。掺杂区62的水平部62a是沿着上表面100a延伸，垂直部62b是沿着上侧壁10b延伸，较佳延伸至与阻障层31的顶面31a切齐。同样的，掺杂制作工艺60后可选择性地进行一回火制作工艺(anneal)，以活化掺杂区62中的离子。回火制作工艺后垂直部62b中的部分离子会沿着沟槽10侧壁往下扩散，因此形成一低于阻障层31的顶面31a的扩散区63。须注意的是，在掺杂制作工艺60前可选择于沟槽10中形成一低于上表面100a的绝缘层(图未示)。
请参考图9。接着于沟槽10中形成一倒U型的盖层54，例如一氧化硅或氮化硅层，完全覆盖导电材料41、阻障层31和栅极介电层21并且将沟槽10填满，完成根据本发明第二实施例的半导体元件2。半导体元件2为一沟槽式栅极，其中位于沟槽10中的导电材料41是栅极电极，与导电材料41重叠的沟槽10的侧壁和底部的区域的基底100为通道区，位于沟槽10开口两侧的掺杂区62是源/漏区。在另一实施例中，如图10所示，若掺杂区62是作为轻掺杂区，则形成盖层54后可另外进行一离子注入制作工艺70以形成源/漏区72，其深度等于或较佳小于垂直部62b的深度。本实施例将阻障层31和栅极介电层21的顶面31a和21a制作成低于导电材料41的顶面41a，可更确保源/漏区72不会与阻障层31重叠而发生漏电。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种半导体元件的制作方法，包含:
提供一基底，具有一上表面；
形成一阱区于该基底中，该阱区具有第一导电型；
在该基底的该阱区中形成一沟槽；
形成一导电材料，填充该沟槽；
移除部分该导电材料至其顶面低于该上表面，暴露出该上表面以及该沟槽的顶角和上侧壁；以及
进行一掺杂制作工艺，在暴露的该上表面、该沟槽的顶角和上侧壁形成一倒L型的掺杂区，该倒L型的掺杂区具有第二导电型并且包含沿该上表面的水平部和沿该沟槽的该上侧壁的垂直部，该水平部的底面高于该垂直部的底面。
2.如权利要求1所述的制作方法，其中该掺杂制作工艺为等离子体掺杂制作工艺(PLAD)。
3.如权利要求1所述的制作方法，其中形成该导电材料之前，另包含形成一阻障层，介于该基底以及该导电材料之间。
4.如权利要求3所述的制作方法，其中移除部分该导电材料的步骤包含:
移除部分该阻障层至与该导电材料的顶面齐平。
5.如权利要求4所述的制作方法，另包含形成一绝缘层，覆盖该导电材料的顶面和该阻障层。
6.如权利要求3所述的制作方法，其中移除部分该导电材料的步骤包含:
移除部分该阻障层至低于该导电材料的顶面。
7.如权利要求3所述的制作方法，另包含形成一栅极介电层，介于该基底与该阻障层之间。
8.如权利要求1所述的制作方法，其中形成该倒L型的掺杂区之后，另包含形成一盖层，位于该导电材料上并填满该沟槽。
9.一种半导体元件，包含:
基底，具有一上表面；
阱区，设于该基底中，并且具有第一导电型；
沟槽，位于该基底的该阱区中；
导电材料，位于该沟槽中，其中该导电材料的顶面低于该上表面，暴露出该沟槽的顶角和上侧壁；以及
倒L型的掺杂区，位于该沟槽的顶角，该倒L型的掺杂区具有第二导电型并且包含一水平部沿着该上表面，一垂直部沿着该沟槽的上侧壁，其中该水平部的底面高于该垂直部的底面。
10.如权利要求9所述的半导体元件，另包含阻障层，介于该基底与该导电材料之间。
11.如权利要求10所述的半导体元件，其中该阻障层的顶面与该导电材料的顶面齐平。
12.如权利要求11所述的半导体元件，另包含绝缘层，覆盖该导电材料的顶面以及该阻障层。
13.如权利要求10所述的半导体元件，其中该阻障层的顶面低于该导电材料的顶面。
14.如权利要求10所述的半导体元件，其中该垂直部延伸至与该阻障层的顶面切齐。
15.如权利要求10所述的半导体元件，其中该垂直部包含扩散区，低于该阻障层的顶面。
16.如权利要求10所述的半导体元件，另包含栅极介电层，介于该基底以及该阻障层之间。
17.如权利要求9所述的半导体元件，另包含盖层，位于该导电材料上并填满该沟槽。
18.如权利要求9所述的半导体元件，另包含源/漏区，设于该基底的该阱区中并邻近该沟槽的上侧壁，其中该源/漏区的深度小于或等于该垂直部的深度。
19.如权利要求9所述的半导体元件，其中该水平部与该阱区直接接触。
20.如权利要求9所述的半导体元件，其中两相邻的该半导体元件的该倒L型的掺杂区互相连接而形成一倒U型掺杂区。
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