CN108231863A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108231863A
CN108231863A CN201710048777.9A CN201710048777A CN108231863A CN 108231863 A CN108231863 A CN 108231863A CN 201710048777 A CN201710048777 A CN 201710048777A CN 108231863 A CN108231863 A CN 108231863A
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layer
semiconductor device
ferroelectric material
barrier layer
groove
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CN108231863B (zh
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张翼
刘世谦
黄崇愷
吴佳勳
韩秉承
林岳钦
谢廷恩
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Spring Foundation of NCTU
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Abstract

一种半导体装置及其制造方法。半导体装置包含：基材、通道层、阻障层、凹槽、电荷陷阱层、铁电材料、栅极、源极和漏极。通道层配置于基材上；阻障层配置于通道层上，阻障层具有凹槽，且凹槽下方的阻障层具有一厚度；漏极和源极配置于阻障层上；电荷陷阱层覆盖凹槽的底面；铁电材料配置于电荷陷阱层上；以及栅极配置于铁电材料上。本发明提供的半导体装置具有高临界电压，而且能同时维持高输出电流。

Description

半导体装置及其制造方法
技术领域
本发明是有关一种半导体装置及其制造方法，特别是关于一种高电子迁移率晶体管。
背景技术
在半导体技术中，III-V族半导体化合物可用于形成各种集成电路装置，例如高功率场效晶体管、高频晶体管或高电子迁移率晶体管(High electron mobilitytransistor,HEMT)，此III-V族半导体化合物具有取代传统硅晶体管的潜力。
然而，当III-V族半导体化合物为氮化镓或氧化镓时，通道将呈现常开型(normally-on)的状态，由于常开模式的晶体管其临界电压(threshold voltage)为负值，即晶体管在零栅极偏压时，晶体管仍会导通电流并形成额外的功率损耗。目前，解决此问题的方法，例如减薄氮化镓层、离子布植、或利用p型氧化镓调整能带结构使其临界电压大于0V，但由于晶体管在应用时，栅极电压会随着漏极偏压有一不稳定的扰动造成误启动的现象，故其晶体管的临界电压需大于6V以上才能有效避免误启动现象发生，故需要进行改良。目前学术及业界所使用避免误启动的方式大多属于增加额外电路进行改良，但此方法会形成寄生效应造成不必要的能量耗损，此外也会增加制造成本。本专利阐述的技术不但能够使临界电压大于6V且具有良好的元件特性。
发明内容
根据本发明的多个实施方式，是提供一种半导体装置，包含：基材、通道层、阻障层、凹槽、漏极、源极、电荷陷阱层、铁电材料和栅极；通道层配置于基材上；阻障层配置于通道层上，阻障层具有凹槽，且凹槽下方的阻障层具有一厚度；漏极和源极配置于阻障层上；电荷陷阱层覆盖凹槽的底面；铁电材料配置于电荷陷阱层上；以及栅极配置于铁电材料上。本发明提供的半导体装置具有高临界电压，而且能同时维持高输出电流。
在某些实施方式中，半导体装置还包含第一介电层配置于凹槽的底面和电荷陷阱层之间。
在某些实施方式中，半导体装置还包含第二介电层配置于铁电材料和栅极之间。
在某些实施方式中，第一介电层具有一能隙(bandgap)，能隙介于7-12eV。
在某些实施方式中，凹槽下方的阻障层厚度介于5-12nm。
在某些实施方式中，铁电材料为BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9或PbZrTiO3。
本发明的多个实施方式，是提供一种制造半导体装置的方法，包含：提供一基材；形成通道层于基材上；形成阻障层于通道层上；形成源极和漏极于阻障层上；形成凹槽于阻障层中，凹槽具有底面，凹槽下方的阻障层具有厚度；形成电荷陷阱层覆盖凹槽的底面；形成铁电材料于电荷陷阱层上；将铁电材料加热至第一温度，第一温度大于铁电材料的结晶温度；将铁电材料降温至第二温度，使铁电材料结晶；以及形成栅极于铁电材料上。
在某些实施方式中，在形成凹槽于阻障层后，还包含形成第一介电层覆盖凹槽的底面。
在某些实施方式中，形成铁电材料的方法包含等离子辅助原子层沉积、有机金属化学气相沉积、化学气相沉积、物理气相沉积、溅镀或脉冲激光蒸镀。
在某些实施方式中，第一温度介于400-600℃。
为使本发明的上述及其他目的、特征和优点更明显易懂，下文特举出较佳实施例，并配合所附附图详细说明如下。
附图说明
图1至图4C是绘示依照本发明各种实施方式的一种半导体装置的制造方法的各制程阶段的剖面示意图；
图5A及图5B为根据本发明某些实施方式的半导体装置的ID-VGS特性曲线。
具体实施方式
以下将详细讨论本实施例的制造与使用，然而，应了解到，本发明提供实务的创新概念，其中可以用广泛的各种特定内容呈现。下文叙述的实施方式或实施例仅为说明，并不能限制本发明的范围。
此外，在本文中，为了易于描述附图所绘的某个元件或特征和其他元件或特征的关系，可能会使用空间相对术语，例如“在…下方”、“在…下”、“低于”、“在…上方”、“高于”和类似用语。这些空间相对术语意欲涵盖元件使用或操作时的所有不同方向，不只限于附图所绘的方向而已。装置可以其他方式定向(旋转90度或定于另一方向)，而本文使用的空间相对描述语则可相应地进行解读。
以下提供各种关于半导体装置及其制作方法的实施例，其中详细说明此半导体装置的结构和性质以及此半导体装置的制备步骤或操作。
高电子迁移率晶体管(High electron mobility transistor,HEMT)由于具有高输出功率、高崩溃电压、耐高温等优良特性，近年来已被广泛应用于高功率电路系统中。而传统的高电子迁移率晶体管由于结构中通道层和阻障层之间具大量极化电荷，这些极化电荷形成二维电子气(two dimensional electron gas,2DEG)，使电子具有高迁移率。此时晶体管在无施加栅极偏压时，仍会导通电流，因此被称为常开式(normally-on)晶体管。常开式晶体管的临界电压(threshold voltage)为负值，即晶体管在零栅极偏压时，晶体管仍会导通电流，形成额外的功率损耗，此外，常开式晶体管无法避免失效安全的意外，具有潜在危险性。因此，常关式晶体管的技术发展为目前高功率晶体管的重要课题，此外，由于高功率电路系统需在高偏压的环境下进行操作，在此高偏压环境下，容易产生瞬间脉冲电压，如果晶体管的临界电压不够高，容易导致高功率元件不正常导通，造成电路的误动作并影响电路系统的稳定度。因此本发明提供一种具有高临界电压的高电子迁移率晶体管装置，即常关式(normally-off)的高电子迁移率晶体管，而且能同时维持高输出电流。
图1至图4C是绘示依照本发明各种实施方式的一种半导体装置的制造方法的各制程阶段的剖面示意图。
在图1中，提供基材110，基材110包含基板112和缓冲层114，缓冲层114配置于基板112上。基板112可为硅(Si)基材、碳化硅(SiC)基材、蓝宝石(sapphire)基材、氮化镓(GaN)基材、氮化铝镓(AlGaN)基材、氮化铝(AlN)基材、磷化镓(GaP)基材、砷化镓(GaAs)基材、砷化铝镓(AlGaAs)基材或其他包含III-V族元素的化合物形成的基材。在某些实施方式中，缓冲层114包含GaN或p型掺质掺杂的GaN。可使用磊晶制程或其他适当的方法形成缓冲层114。在一实施例中，p型掺质包含碳、铁、镁、锌或其他适当的p型掺质。缓冲层可降低漏电流及避免形成通道层120时的磊晶制程中发生龟裂现象。在另一实施例中，基材110包含基板112、晶种层(未绘示)和缓冲层114。晶种层配置于基板112上，缓冲层114配置于晶种层上。晶种层有助于补偿基板112和缓冲层114间晶格结构的错配(mismatch)。
接着形成通道层120于基材110上，再形成阻障层130于通道层120上。基材通道层120可为氮化铝镓(AlGaN)、氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝铟镓(AlInGaN)或其他包含III-V族元素的化合物。障壁层130可为氮化铝(AlN)、氮化铝铟(AlInN)、AlGaN、GaN、InGaN、AlInGaN或其他包含III-V族元素的化合物。通道层120的能隙小于阻障层130的能隙，且通道层120和阻障层130的组合和厚度必须能够产生二维电子气。在一实施方式中，通道层120或/及阻障层130可为多层结构。在另一实施方式中，可再形成其他层，例如在通道层120和阻障层130之间形成一中间层(未绘示)、形成一掺杂层(未绘示)于阻障层130上方以增加二维电子气的电子或形成一覆盖层(未绘示)于阻障层130上以防止阻障层130氧化。
请参照图2，形成源极S和漏极D于阻障层130上。源极S和漏极D各自选于下列组合，包含但不限于银(Ag)、铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、铝(Al)、镍(Ni)、钌(Ru)、钯(Pd)、铂(Pt)、锰(Mn)、氮化钨(WN)、氮化钛(TiN)、氮化钽(TaN)、氮化铝(AlN)、硅化钨(WSi)、氮化钼(MoN)、硅化镍(Ni2Si)、硅化钛(TiSi2)、铝化钛(TiAl)、砷(As)掺杂的多晶硅、氮化锆(ZrN)、TaC、TaCN、TaSiN、TiAlN、硅化物或其任意的组合。形成源极S和漏极D的方法可使用任何已知的制程。
如图3所示，利用图案化制程在阻障层130中形成凹槽R。在一实施方式中，可在阻障层130上形成遮罩层，遮罩层例如为硬遮罩或光阻，并在遮罩层上形成图案，再利用蚀刻制程将图案转移至底下的阻障层130中形成凹槽R，其中蚀刻制程可为反应式离子蚀刻、等离子干式蚀刻或其他非等向性蚀刻方式，蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。在另一实施方式中，在形成遮罩层后使用湿式蚀刻制程蚀刻出凹槽R，使凹槽R的底角圆滑化。
凹槽R具有深度d1和宽度w，深度d1介于15-25nm，例如15nm、20nm或25nm；宽度w介于0.1μm-3μm，例如0.5μm、1μm、2μm、2.5μm。凹槽R位于源极S和漏极D的中间而且并未贯穿阻障层130，目的在于削弱阻障层130的极化现象并消除二维电子气通道的载子，使之临界电压大于0V。因较薄的阻障层会提升导带能阶，故减少栅极区域底下的阻障层厚度可驱赶(deplete)二维电子气。凹槽R的底面和通道层120上表面之间的阻障层130具有厚度d2，厚度d2介于0-10nm，例如1nm、3nm、5nm或8nm。需要注意的是，若厚度d2的厚度大于10nm，会使阻障层130仍具有大量极化电荷，进而使通道成为常开型的状态。
在某些实施方式中，凹槽R的宽度小于3μm，例如0.05μm、0.5μm、1μm或2μm。在某些实施方式中，凹槽R和源极S、漏极D的距离不同，在一实施例中，凹槽R的边缘和源极S的距离介于1～3μm，例如1.5μm、2μm或2.5μm。凹槽R的边缘和漏极D的距离介于5～15μm，例如7.5μm、10μm或12.5μm。
图4A-图4C是提供不同的铁电材料复合层实施方式。如图4A-图4C所示，在形成凹槽R之后，形成铁电材料复合层于凹槽内。形成铁电材料复合层的方式包含但不限于等离子辅助原子层沉积、有机金属化学气相沉积、化学气相沉积、物理气相沉积、溅镀或脉冲激光蒸镀。形成铁电材料复合层之后可以选择性地使用图案化制程使铁电材料复合层的侧面与凹槽R的侧面切齐。在一实施方式中，铁电材料复合层的宽度等于凹槽R的宽度w。
在图4A中，铁电材料复合层包含电荷陷阱层220(或称电荷储存层)和铁电材料230。电荷陷阱层220覆盖凹槽R的底面，铁电材料230配置于电荷陷阱层220上。栅极250配置于铁电材料230上。钝化层260覆盖阻障层130。电荷陷阱层220可例如为氮化硅、HfON、HfO2、ZrO2、介电层或被绝缘材料所环绕的纳米晶体层。电荷陷阱层220的厚度介于1-4nm，例如1.5nm、2nm、2.5nm或3nm，取决于选用的材料的特性。在一实施方式中，电荷陷阱层220为多层结构，此多层结构可包含上述电荷陷阱层220材料的组合。在一实施方式中，钝化层260可为AlN、Al2O3、AlON、SiN、SiO2、SiON或Si3N4。
在各种实施方式中，铁电材料230可为BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9(SBT)、PbZrTiO3(PZT)或其他可引发铁电效应的材料。所谓的铁电效应，是指材料本身在外加电场之下，具备自发性极化(spontaneous polarization)及极化转换(polarizationtransition)的特性。当施加外电场时，会使电偶极顺着电场方向排列，而在电场移去后，仍能保持极化方向的残留极化(remnant polarization,Pr)，此一效应称为铁电效应。对于任何铁电材料而言，具有残留极化表示其拥有永久极化能力。在形成铁电材料230后，使用热退火处理，将铁电材料230升温至第一温度，第一温度高于铁电材料230的结晶温度，再将铁电材料230降温至一第二温度，使铁电材料230结晶形成铁电材料。在实施方式中，第一温度介于400-600℃，例如450℃、500℃或550℃。第二温度介于25-100℃，例如25℃或80℃。
在图4B中，提供另一种铁电材料复合层的实施方式。在此实施方式中，先形成第一介电层210于凹槽R内，再形成电荷陷阱层220于第一介电层210上，接着形成铁电材料230于电荷陷阱层220上。之后形成栅极250于铁电材料230上。钝化层260覆盖阻障层130。第一介电层210的功能为宽能隙阻挡层，具有一能隙(bandgap)，且此能隙介于7-12eV，例如8eV、9eV、11eV、13eV或15eV。第一介电层210能降低漏电流以及提升栅极崩溃电压。第一介电层210可为Al2O3、SiO2或其他能隙介于7-12eV的材料。形成电荷陷阱层220和铁电材料230的方法已在前文叙述过，故不再重复叙述。
在图4C中，提供另一种铁电材料复合层的实施方式。铁电材料复合层包含第一介电层210配置于凹槽内，电荷陷阱层220配置于第一介电层210，铁电材料230配置于电荷陷阱层220上，第二介电层240配置于铁电材料230上。栅极250配置于第二介电层240上。钝化层260覆盖阻障层130。第二介电层240和第一介电层210皆为宽能隙阻挡层，具有一能隙(bandgap)，且此能隙介于7-12eV，例如8eV、9eV、11eV、13eV或15eV。第二介电层240能降低漏电流以及提升栅极崩溃电压。第二介电层240可为Al2O3、SiO2或其他能隙介于7-12eV的材料。
在此半导体装置中，当施加正电压于栅极250时，铁电材料230会极化并抓取电荷，而电荷陷阱层220提供储存电荷的地方。此时栅极250和铁电材料复合层下方的能隙便会开始改变，阻障层130的表面负电位开始增加，进而使半导体装置的临界电压值往正方向移动。
在一实施方式中，铁电材料230极化后，半导体装置的临界电压变化值可大于5V，其临界电压从接近0V改变为大于5V，即成为增强型的半导体装置。在另一实施方式中，可通过调整凹槽R的深度来调整临界电压。在阻障层130厚度相同的情况下，当厚度d2越薄，半导体装置的临界电压值会越往正值方向移动，但其最大漏极电流也会降低，因此厚度d2必须控制在一定的范围内。
图5A及图5B为根据本发明某些实施方式的半导体装置的ID-VGS特性曲线。曲线A代表铁电材料230极化前，曲线B则代表铁电材料230极化后。如图5A所示，铁电材料230极化后，半导体装置的临界电压(Vth)从极化前的2.5V变为10V。如图5B所示，此半导体装置的Ion/Ioff比值为6x108。
综上所述，本发明的各实施例提供一种半导体装置，利用铁电材料的永久极化效应造成能带变化，使半导体装置拥有高临界电压以减低额外功率耗损并增加电路系统稳定度。
上文概述若干实施例的特征结构，使得熟悉此项技术者可更好地理解本发明的态样。熟悉此项技术者应了解，可轻易使用本发明作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本发明的精神及范畴，且可在不脱离本发明的精神及范畴的情况下做出对本发明的各种变化、替代及更改。

Claims (10)

1.一种半导体装置，其特征在于，包含：
一基材；
一通道层配置于该基材上；
一阻障层配置于该通道层上，该阻障层具有一凹槽，且该凹槽下方的该阻障层具有一厚度；
一漏极和一源极配置于该阻障层上；
一电荷陷阱层覆盖该凹槽的一底面；
一铁电材料配置于该电荷陷阱层上；以及
一栅极配置于该铁电材料上。
2.如权利要求1所述的半导体装置，其特征在于，还包含一第一介电层配置于该凹槽的该底面和该电荷陷阱层之间。
3.如权利要求2所述的半导体装置，其特征在于，还包含一第二介电层配置于该铁电材料和该栅极之间。
4.如权利要求1所述的半导体装置，其特征在于，该第一介电层具有一能隙，该能隙介于7-12eV。
5.如权利要求1所述的半导体装置，其特征在于，该厚度介于5-15nm。
6.如权利要求1所述的半导体装置，其特征在于，该铁电材料为BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9或PbZrTiO3。
7.一种制造半导体装置的方法，其特征在于，包含：
提供一基材；
形成一通道层于该基材上；
形成一阻障层于该通道层上；
形成一源极和一漏极于该阻障层上；
形成一凹槽于该阻障层中，该凹槽具有一底面，该凹槽下方的该阻障层具有一厚度；
形成一电荷陷阱层覆盖该凹槽的该底面；
形成一铁电材料于该电荷陷阱层上；
将该铁电材料加热至一第一温度，该第一温度大于该铁电材料的一结晶温度；
将该铁电材料降温至一第二温度，使该铁电材料结晶；以及
形成一栅极于该铁电材料上。
8.如权利要求7所述的制造半导体装置的方法，其特征在于，在形成一凹槽于该阻障层后，还包含形成一第一介电层于该覆盖该凹槽的该底面。
9.如权利要求7所述的制造半导体装置的方法，其特征在于，形成该铁电材料的方法包含等离子辅助原子层沉积、有机金属化学气相沉积、化学气相沉积、物理气相沉积、溅镀或脉冲激光蒸镀。
10.如权利要求7所述的制造半导体装置的方法，其特征在于，该第一温度介于400-600℃。
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