TW202103268A - 高電子遷移率電晶體及其製作方法 - Google Patents

高電子遷移率電晶體及其製作方法 Download PDF

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TW202103268A
TW202103268A TW108124137A TW108124137A TW202103268A TW 202103268 A TW202103268 A TW 202103268A TW 108124137 A TW108124137 A TW 108124137A TW 108124137 A TW108124137 A TW 108124137A TW 202103268 A TW202103268 A TW 202103268A
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barrier layer
layer
hard mask
mobility transistor
electron mobility
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TWI811394B (zh
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黃信川
葉治東
張峻銘
陳柏榮
廖文榮
侯俊良
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聯華電子股份有限公司
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Priority to US16/533,812 priority patent/US11264492B2/en
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Abstract

本發明揭露一種製作高電子遷移率電晶體的方法。首先形成一緩衝層於一基底上，然後形成一阻障層於緩衝層上，形成一硬遮罩於阻障層上，再進行一離子佈植製程穿過硬遮罩以形成一摻雜區於阻障層及緩衝層內。接著去除硬遮罩及阻障層以形成一凹槽，形成一閘極介電層於硬遮罩上並填入該凹槽內，形成一閘極電極於閘極介電層上，再形成一源極電極以及一汲極電極於閘極電極兩側。

Description

高電子遷移率電晶體及其製作方法
本發明是關於一種高電子遷移率電晶體及其製作方法。
以氮化鎵基材料(GaN-based materials)為基礎的高電子遷移率電晶體具有於電子、機械以及化學等特性上之眾多優點，例如寬能隙、高崩潰電壓、高電子遷移率、大彈性模數(elastic modulus)、高壓電與壓阻係數(high piezoelectric and piezoresistive coefficients)等與化學鈍性。上述優點使氮化鎵基材料可用於如高亮度發光二極體、功率開關元件、調節器、電池保護器、面板顯示驅動器、通訊元件等應用之元件的製作。
本發明一實施例揭露一種製作高電子遷移率電晶體的方法。首先形成一緩衝層於一基底上，然後形成一阻障層於緩衝層上，形成一硬遮罩於阻障層上，再進行一離子佈植製程穿過硬遮罩以形成一摻雜區於阻障層及緩衝層內。接著去除硬遮罩及阻障層以形成一凹槽，形成一閘極介電層於硬遮罩上並填入該凹槽內，形成一閘極電極於閘極介電層上，再形成一源極電極以及一汲極電極於閘極電極兩側。
本發明另一實施例揭露一種高電子遷移率電晶體，其主要包含一緩衝層設於一基底上，一阻障層設於該緩衝層上，一閘極電極設於該阻障層上，一閘極介電層設於該阻障層以及該閘極電極之間，一硬遮罩設於該閘極介電層以及該阻障層之間以及一源極電極以及一汲極電極分別設於該閘極電極兩側之該緩衝層上。
請參照第1圖至第5圖，第1圖至第5圖為本發明一實施例製作應用於射頻元件(RF device)之一高電子遷移率電晶體之方法示意圖。如第1圖所示，首先提供一基底12，例如一由矽、碳化矽或氧化鋁(或可稱藍寶石)所構成的基底，其中基底12可為單層基底、多層基底、梯度基底或上述之組合。依據本發明其他實施例基底12又可包含一矽覆絕緣(silicon-on-insulator, SOI)基底。
然後於基底12表面形成一緩衝層14。在一實施例中，緩衝層14包含III-V族半導體例如氮化鎵，其厚度可藉於0.5微米至10微米之間。在一實施例中，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於基底12上形成緩衝層14。
接著形成一阻障層16於緩衝層14表面。在本實施例中阻障層16較佳包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，其中0>x>1，且阻障層16較佳包含一由磊晶成長製程所形成之磊晶層。如同上述形成緩衝層14的方式，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於緩衝層14上形成阻障層16。
然後形成一硬遮罩18於阻障層16上並完全覆蓋阻障層16表面，再形成一圖案化遮罩20，例如一圖案化光阻於硬遮罩18上，其中圖案化遮罩20包含一開口22暴露出部分硬遮罩18表面。接著以圖案化遮罩20為遮罩進行一離子佈植製程24，將氟離子穿過硬遮罩18並植入阻障層16及緩衝層14，以於阻障層16及緩衝層14內形成一摻雜區26。在本實施例中，由氟所構成的摻雜區26底部較佳略低於阻障層16底部或緩衝層14上表面，且摻雜區26的氟濃度較佳由阻障層16至緩衝層14遞減。換句話說，靠近阻障層16與硬遮罩18交界處的摻雜區26較佳包含較高濃度的氟離子，而靠近阻障層16與緩衝層14交界處的摻雜區26則包含較低濃度的氟離子。
如第2圖所示，接著可再利用圖案化遮罩20為遮罩進行一蝕刻製程去除部分硬遮罩18及部分阻障層16形成凹槽28，其中蝕刻的過程中較佳僅去除部分摻雜區26，使剩餘摻雜區26仍設於凹槽28正下方。在本實施例中，凹槽28底部較佳略高於阻障層16底部，但不侷限於此，依據本發明其他實施例又可於蝕刻的過程中調整凹槽28深度，例如使凹槽28底部高於、切齊甚至低於於阻障層16底部或緩衝層14頂部，這些實施例均屬本發明所涵蓋的範圍。
隨後如第3圖所示，形成一閘極介電層30於硬遮罩18上並填入凹槽28內但不填滿凹槽28。在本實施例中，閘極介電層30較佳包含金屬氮化物如氮化鋁(AlN)，但又可包含其他介電材料例如但不侷限於二氧化矽(SiO2 )、氮化矽(SiN)或高介電常數(high dielectric constant, high-k)材料，其中高介電常數介電層較佳包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶(strontium titanate oxide, SrTiO3 )、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
接著如第4圖所示，先進行一微影暨蝕刻製程去除凹槽28兩側的部分閘極介電層30、部分硬遮罩18以及部分阻障層16，以於凹槽28兩側分別形成二凹槽(圖未示)，再形成一閘極電極32於凹槽28內以及一源極電極34與汲極電極36於閘極電極32兩側的凹槽內。在本實施例中，閘極電極32、源極電極34與汲極電極36均較佳由金屬所構成，其中源極電極34與汲極電極36較佳包含相同材料，但源極電極34與汲極電極36兩者可與閘極電極32包含相同或不同材料。依據本發明一實施例，閘極電極32、源極電極34及汲極電極36可各自包含金、銀、鉑、鈦、鋁、鎢、鈀或其組合。在一些實施例中，可利用電鍍製程、濺鍍製程、電阻加熱蒸鍍製程、電子束蒸鍍製程、物理氣相沉積(physical vapor deposition, PVD)製程、化學氣相沉積製程(chemical vapor deposition, CVD)製程、或上述組合於凹槽內以及硬遮罩30表面形成電極材料，然後再利用單次或多次蝕刻將電極材料圖案化以形成閘極電極32、源極電極34以及汲極電極36。
如第5圖所示，隨後進行一金屬內連線製程，以形成複數層金屬間介電層38(inter-metal dielectric, IMD)以及金屬內連線40鑲嵌於金屬間介電層38內分別電連接閘極電極32、源極電極34以及汲極電極36。在本實施例中，金屬內連線結構中的各金屬內連線40均可依據單鑲嵌製程或雙鑲嵌製程鑲嵌於金屬間介電層38中並彼此電連接。例如各金屬內連線40更細部包含一阻障層以及一金屬層，其中阻障層可選自由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)以及氮化鉭(TaN)所構成的群組，而金屬層可選自由鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等所構成的群組，但不侷限於此。由於單鑲嵌或雙鑲嵌製程乃本領域所熟知技藝，在此不另加贅述。
請繼續參照第5圖，第5圖另揭露本發明一實施例之一高電子遷移率電晶體之結構示意圖。如第5圖所示，高電子遷移率電晶體主要包含緩衝層14設於基底12上，阻障層16設於緩衝層14上，閘極電極32設於阻障層16上，閘極介電層30設於阻障層16以及閘極電極32之間，硬遮罩18設於閘極介電層30與阻障層16之間，摻雜區26設於閘極介電層30與緩衝層14之間，以及源極電極34與汲極電極36分別設於閘極電極32兩側的緩衝層14上。
在本實施例中，緩衝層14較佳包含III-V族半導體例如氮化鎵，阻障層16較佳包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，且硬遮罩18與閘極介電層30較佳包含不同材料，其中硬遮罩18較佳包含氮化矽但又可包含其他介電材料例如但不侷限於氧化矽、氮氧化矽或氮碳化矽，閘極介電層30較佳包含金屬氮化物如氮化鋁但又可包含其他介電材料例如但不侷限於氧化矽、氮化矽或高介電常數介電層。摻雜區26較佳包含氟，且摻雜區26的氟濃度較佳由阻障層16至緩衝層14遞減。換句話說，靠近阻障層16與硬遮罩18交界處的摻雜區26較佳包含較高濃度的氟離子，而靠近阻障層16與緩衝層14交界處的摻雜區則包含較低濃度的氟離子。
從細部來看，閘極介電層30包含一U形部42以及第一水平部44與第二水平部46連接U形部42，其中硬遮罩18是設於第一水平部44、第二水平部46以及阻障層16之間。源極電極34與汲極電極36直接接觸閘極介電層30與硬遮罩18，源極電極34與汲極電極36頂部較佳切齊閘極電極32頂部但源極電極34與汲極電極36底部較佳低於閘極電極32底部，且硬遮罩18側壁較佳切齊摻雜區26側壁於源極電極34與汲極電極36下方。另外本實施例的源極電極34與汲極電極36底部雖較佳切齊阻障層16底部，但不侷限於此，依據本發明其他實施例源極電極34與汲極電極36底部又可約略高於阻障層16底部或低於阻障層16底部，這些變化型均屬本發明所涵蓋的範圍。
請再參照第6圖，第6圖另揭露本發明一實施例之一高電子遷移率電晶體之結構示意圖。如第6圖所示，相較於前述實施例之閘極電極層之側壁切齊正下方的摻雜區，依據本發明一實施例又可於第1圖進行離子佈植製程時以斜角離子佈植方式將氟離子植入阻障層16及緩衝層14內，或可選擇以兩道具有不同開口寬度的遮罩來分別形成摻雜區26以及凹槽28，使凹槽28寬度約略小於摻雜區26寬度。如此後續形成閘極介電層30與閘極電極32後摻雜區26便較佳環繞閘極介電層30與閘極電極32底部而形成約略U形的摻雜區26，此變化型也屬本發明所涵蓋的範圍。
一般而言，由於緩衝層與阻障層的材料能帶間隙(band gap)不同之故，緩衝層與阻障層的介面數較佳形成異質接面(heterojunction)。異質接面處的能帶彎曲，導帶(conduction band)彎曲深處形成量子井(quantum well)，將壓電效應(piezoelectricity)所產生的電子約束於量子井中，因此在緩衝層與阻障層的介面處形成通道區58或二微電子氣(two-dimensional electron gas, 2DEG)，進而形成導通電流。
現行製備高電子遷移率電晶體時將電晶體由正常開啟(Normally on)操作模式轉換為正常關閉(Normally off)操作方式的手段之一是先形成一硬遮罩於阻障層上，圖案化硬遮罩以形成一開口暴露出阻障層表面，再以離子佈植製程將氟離子直接植入阻障層內，其中所植入的氟離子較佳吸引一個自由電子並成為負固定電荷(negative fixed charge)調變其局部電位(local portion)進而耗盡2DEG。考量現行將離子直接植入阻障層所形成的摻雜區深度經常過深進而影響元件阻值，本發明較佳在不去除或不圖案化整個硬遮罩的情況下將氟離子穿過硬遮罩並植入下方的阻障層與緩衝層內。藉由硬遮罩作為阻隔本發明除了可省下一道用來圖案化硬遮罩的光罩又可使摻雜區的深度不致過深而影響元件表現。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:緩衝層 16:阻障層 18:硬遮罩 20:圖案化遮罩 22:開口 24:離子佈植製程 26:摻雜區 28:凹槽 30:閘極介電層 32:閘極電極 34:源極電極 36:汲極電極 38:金屬間介電層 40:金屬內連線 42:U形部 44:第一水平部 46:第二水平部
第1圖至第5圖為本發明一實施例製作一高電子遷移率電晶體之方法示意圖。 第6圖為本發明一實施例之一高電子遷移率電晶體之結構示意圖。
12:基底
14:緩衝層
16:阻障層
18:硬遮罩
26:摻雜區
30:閘極介電層
32:閘極電極
34:源極電極
36:汲極電極
38:金屬間介電層
40:金屬內連線
42:U形部
44:第一水平部
46:第二水平部

Claims (20)

  1. 一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其特徵在於，包含： 形成一緩衝層於一基底上； 形成一阻障層於該緩衝層上； 形成一硬遮罩於該阻障層上； 進行一離子佈植製程穿過該硬遮罩以形成一摻雜區於該阻障層以及該緩衝層內。
  2. 如申請專利範圍第1項所述之方法，另包含： 去除該硬遮罩以及該阻障層以形成一第一凹槽； 形成一閘極介電層於該硬遮罩上並填入該第一凹槽內； 形成一閘極電極於該閘極介電層上；以及 形成一源極電極以及一汲極電極於該閘極電極兩側。
  3. 如申請專利範圍第2項所述之方法，另包含： 去除該閘極介電層、該硬遮罩以及該阻障層以形成一第二凹槽及一第三凹槽於該閘極電極兩側； 形成該源極電極於該第二凹槽內以及該汲極電極於該第三凹槽內。
  4. 如申請專利範圍第1項所述之方法，其中該緩衝層包含III-V族半導體。
  5. 如申請專利範圍第4項所述之方法，其中該緩衝層包含氮化鎵。
  6. 如申請專利範圍第1項所述之方法，其中該阻障層包含氮化鋁鎵(Alx Ga1-x N)。
  7. 如申請專利範圍第1項所述之方法，其中該摻雜區包含氟。
  8. 如申請專利範圍第7項所述之方法，其中該氟濃度由該阻障層至該緩衝層降低。
  9. 一種高電子遷移率電晶體(high electron mobility transistor, HEMT)，其特徵在於，包含： 一緩衝層設於一基底上； 一阻障層設於該緩衝層上； 一閘極電極設於該阻障層上； 一閘極介電層設於該阻障層以及該閘極電極之間； 一硬遮罩設於該閘極介電層以及該阻障層之間；以及 一源極電極以及一汲極電極分別設於該閘極電極兩側之該緩衝層上。
  10. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該緩衝層包含III-V族半導體。
  11. 如申請專利範圍第10項所述之高電子遷移率電晶體，其中該緩衝層包含氮化鎵。
  12. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該阻障層包含氮化鋁鎵(Alx Ga1-x N)。
  13. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該閘極介電層包含一U形部。
  14. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該閘極介電層包含一第一水平部以及一第二水平部連接該U形部。
  15. 如申請專利範圍第14項所述之高電子遷移率電晶體，其中該硬遮罩係設於該第一水平部、該第二水平部以及該阻障層之間。
  16. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該源極電極接觸該閘極介電層以及該硬遮罩。
  17. 如申請專利範圍第9項所述之高電子遷移率電晶體，另包含一摻雜區設於該閘極介電層以及該緩衝層之間。
  18. 如申請專利範圍第17項所述之高電子遷移率電晶體，其中該硬遮罩側壁切齊該摻雜區側壁。
  19. 如申請專利範圍第17項所述之高電子遷移率電晶體，其中該摻雜區包含氟。
  20. 如申請專利範圍第19項所述之高電子遷移率電晶體，其中該氟濃度由該阻障層至該緩衝層降低。
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