JP6560112B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6560112B2 JP6560112B2 JP2015240421A JP2015240421A JP6560112B2 JP 6560112 B2 JP6560112 B2 JP 6560112B2 JP 2015240421 A JP2015240421 A JP 2015240421A JP 2015240421 A JP2015240421 A JP 2015240421A JP 6560112 B2 JP6560112 B2 JP 6560112B2
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- film
- semiconductor layer
- nitride semiconductor
- insulating film
- semiconductor device
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Description
以下、図面を参照しながら本実施の形態の半導体装置について詳細に説明する。
図1は、本実施の形態の半導体装置の構成を示す断面図である。
次に、図4〜図14を参照しながら、本実施の形態の半導体装置の製造方法を説明する。図4〜図7および図9〜図14は、本実施の形態の半導体装置の製造方法を示す断面図である。図8は、本実施の形態の半導体装置の製造工程で用いるスパッタリング装置の断面図である。
前記実施の形態1では、ゲート電極をバリアメタル膜およびタングステン膜の積層膜により構成することについて説明したが、ゲート電極は、図16および図17に示すように、タングステン膜WFのみにより構成されていてもよい。図16は、本実施の形態の半導体装置を示す断面図である。図17は、本実施の形態の半導体装置を示す断面図であって、図16に示すゲート電極GEの一部を拡大して示す断面図である。図17は断面図であるが、図を分かりやすくするため、ここではハッチングを省略している。
前記基板上に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された絶縁膜と、
前記絶縁膜および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝と、
前記溝内および前記絶縁膜上に、ゲート絶縁膜を介して形成されたゲート電極と、
を有し、
前記ゲート電極は、タングステン膜を有し、
前記第2窒化物半導体層の格子間距離は、1.2938Å以下である、半導体装置。
(b)前記基板上に第1窒化物半導体層を形成する工程、
(c)前記第1窒化物半導体層上に、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層を形成する工程、
(d)前記第2窒化物半導体層上に絶縁膜を形成する工程、
(e)前記絶縁膜および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝を形成する工程、
(f)前記溝内および前記絶縁膜上に、ゲート絶縁膜を形成する工程、
(g)前記ゲート絶縁膜上に、第1スパッタリングを行って導電膜を形成する工程、
(h)前記導電膜上に、第2スパッタリングを行ってタングステン膜を形成し、前記導電膜および前記タングステン膜を含むゲート電極を形成する工程、
を有し、
前記第2スパッタリングにおいて、スパッタ対象の第2ターゲットに印加する第1DCパワーは、前記第1スパッタリングにおいて、スパッタ対象の第1ターゲットに印加する第2DCパワーより小さい、半導体装置の製造方法。
BM バリアメタル膜
CH チャネル層
DE ドレイン電極
GE ゲート電極
GI ゲート絶縁膜
SE ソース電極
WF タングステン膜
Claims (12)
- 基板と、
前記基板上に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された絶縁膜と、
前記絶縁膜および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝と、
前記溝内および前記絶縁膜上に、ゲート絶縁膜を介して形成されたゲート電極と、
を有し、
前記ゲート電極は、導電膜と前記導電膜上に形成されたタングステン膜とを有し、
前記タングステン膜を構成する第1グレインの粒径は、前記導電膜を構成する第2グレインの粒径より小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記第1グレインの粒径は、5nm以下である、半導体装置。 - 請求項1記載の半導体装置において、
前記タングステン膜は、複数の前記第1グレインを有し、
複数の前記第1グレインのうち、一部の前記第1グレインは、前記タングステン膜の上面および下面を構成していない、半導体装置。 - 請求項1記載の半導体装置において、
前記第2窒化物半導体層上に形成され、前記第2窒化物半導体層の上面に接続されたソース電極と、
前記第2窒化物半導体層上に形成され、前記第2窒化物半導体層の上面に接続されたドレイン電極と、
をさらに有し、
前記ゲート電極は、前記ソース電極と前記ドレイン電極との間に配置され、
前記ゲート電極、前記ソース電極および前記ドレイン電極は、電界効果トランジスタを構成している、半導体装置。 - 請求項4記載の半導体装置において、
前記電界効果トランジスタのしきい値電圧は、0V以上である、半導体装置。 - 基板と、
前記基板上に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された絶縁膜と、
前記絶縁膜および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝と、
前記溝内および前記絶縁膜上に、ゲート絶縁膜を介して形成されたゲート電極と、
を有し、
前記ゲート電極は、タングステン膜を有し、
前記タングステン膜を構成する第1グレインの粒径は、5nm以下である、半導体装置。 - 請求項6記載の半導体装置において、
前記第2窒化物半導体層上に形成され、前記第2窒化物半導体層の上面に接続されたソース電極と、
前記第2窒化物半導体層上に形成され、前記第2窒化物半導体層の上面に接続されたドレイン電極と、
をさらに有し、
前記ゲート電極は、前記ソース電極と前記ドレイン電極との間に配置され、
前記ゲート電極、前記ソース電極および前記ドレイン電極は、電界効果トランジスタを構成している、半導体装置。 - 請求項7記載の半導体装置において、
前記電界効果トランジスタのしきい値電圧は、0V以上である、半導体装置。 - (a)基板を準備する工程、
(b)前記基板上に第1窒化物半導体層を形成する工程、
(c)前記第1窒化物半導体層上に、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層を形成する工程、
(d)前記第2窒化物半導体層上に絶縁膜を形成する工程、
(e)前記絶縁膜および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝を形成する工程、
(f)前記溝内および前記絶縁膜上に、ゲート絶縁膜を形成する工程、
(g)前記ゲート絶縁膜上に、第1スパッタリングを行ってタングステン膜を形成し、前記タングステン膜を含むゲート電極を形成する工程、
を有し、
前記第1スパッタリングにおいて、スパッタ対象の第1ターゲットに印加する第1DCパワーは、300W以下である、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記タングステン膜を構成する第1グレインの粒径は、5nm以下である、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
(h)前記ゲート電極から離間した位置において、前記第2窒化物半導体層に接続されたソース電極および前記第2窒化物半導体層に接続されたドレイン電極を形成する工程、
をさらに有し、
前記ゲート電極、前記ソース電極および前記ドレイン電極は、電界効果トランジスタを構成している、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(g)工程は、
(g1)前記ゲート絶縁膜上に、第2スパッタリングを行って導電膜を形成する工程、
(g2)前記導電膜上に、前記第1スパッタリングを行って前記タングステン膜を形成し、前記導電膜および前記タングステン膜を含む前記ゲート電極を形成する工程、
を含み、
前記第2スパッタリングにおいて、スパッタ対象の第2ターゲットに印加する第2DCパワーは、300Wより大きい、半導体装置の製造方法。
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