CN111146275A - 高电子迁移率晶体管元件及其制造方法 - Google Patents

高电子迁移率晶体管元件及其制造方法 Download PDF

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CN111146275A
CN111146275A CN201910752030.0A CN201910752030A CN111146275A CN 111146275 A CN111146275 A CN 111146275A CN 201910752030 A CN201910752030 A CN 201910752030A CN 111146275 A CN111146275 A CN 111146275A
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陈智伟
温文莹
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Nuvoton Technology Corp
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Abstract

本发明实施例提供一种高电子迁移率晶体管元件及其制造方法。高电子迁移率晶体管HEMT元件包括通道层、阻障层、第一栅极、第一漏极与第一源极。通道层设置于衬底上。通道层在HEMT元件的第一区内的表面包括极性面与非极性面。阻障层共形地设置于通道层上。第一栅极设置于阻障层上,且位于第一区内。第一漏极与第一源极设置于第一区内,且分别位于第一栅极的相对两侧。

Description

高电子迁移率晶体管元件及其制造方法
技术领域
本发明是有关于一种晶体管元件及其制造方法,且特别是有关于一种高电子迁移率晶体管(high electron mobility transistor,HEMT)元件及其制造方法。
背景技术
高电子迁移率晶体管(high electron mobility transistor,HEMT)是晶体管的一种。HEMT包括由两种具有不同能隙的半导体材料所形成的异质结(hetero junction)。异质结可产生二维电子气或二维电洞气,而可作为HEMT的导电通道。由于HEMT具有低阻值、高击穿电压以及快速开关切换频率等优点,故在高功率电子元件的领域中受到广泛的应用。
HEMT可依据通道的常开或常关而分别归类为耗尽型(depletion mode)或增强型(enhancement mode)HEMT。增强型晶体管元件因为其提供的附加安全性以及其更容易由简单、低成本的驱动电路来控制,故在业界获得相当大的关注。
发明内容
本发明提供一种HEMT元件及其制造方法,藉由设置立体的通道结构,而形成增强型HEMT。
本发明实施例的HEMT元件包括通道层、阻障层、第一栅极、第一漏极与第一源极。通道层设置于衬底上。通道层在HEMT元件的第一区内的表面包括极性面与非极性面。阻障层共形地设置于通道层上。第一栅极设置于阻障层上,且位于第一区内。第一漏极与第一源极设置于第一区内,且分别位于第一栅极的相对两侧。
在一些实施例中,极性面与非极性面实质上正交。
在一些实施例中,通道层包括主体部与突出部。突出部沿实质上垂直于衬底的表面的方向自主体部突出。突出部的侧壁为非极性面,且突出部的顶面为极性面的一部分。
在一些实施例中,第一栅极覆盖突出部的顶面。
在一些实施例中,第一栅极覆盖突出部的顶面与侧壁。
在一些实施例中,通道层具有凹陷。凹陷的侧壁为非极性面。凹陷的底面为极性面的一部分。第一栅极的至少一部分位于凹陷中。
在一些实施例中,通道层在HEMT元件的第二区内的顶面包括极性面,且HEMT元件更包括第二栅极、第二漏极与第二源极。第二栅极设置于阻障层的位于第二区内的部分上。第二漏极与第二源极设置于第二区内,且位于第二栅极的相对两侧。
在一些实施例中,通道层在HEMT元件的第三区内的顶面包括极性面,且HEMT元件更包括第一电极与第二电极。第一电极设置于通道层与阻障层中且位于第三区内。第二电极设置于阻障层的位于第三区内的部分上,且位于第一电极的一侧。
本发明实施例的HEMT元件的制造方法包括:在衬底上形成通道材料层;图案化通道材料层的位于高电子迁移率晶体管元件的第一区内的一部分,以形成通道层,其中通道层在第一区内的表面包括极性面与非极性面;在通道层上共形地形成阻障层;在第一区内的阻障层上形成第一栅极;以及在第一区内形成第一漏极与第一源极,其中第一漏极与第一源极分别位于第一栅极的相对两侧。
在一些实施例中,图案化通道材料层的位于第一区内的部分的方法包括自通道材料层的表面移除一些部分的通道材料层,以使通道层的顶部具有相邻的第一凹陷与第二凹陷。第一凹陷与第二凹陷的侧壁为非极性面,且第一凹陷与第二凹陷的底面为极性面的一部分。
在一些实施例中,第一栅极形成于通道层的位于第一凹陷与第二凹陷之间的部分上。
在一些实施例中,第一栅极更延伸至第一凹陷与第二凹陷中。
在一些实施例中,图案化通道材料层的位于第一区内的部分的方法包括在通道材料层的表面形成凹陷。凹陷的侧壁为非极性面。凹陷的底面为极性面的一部分。第一栅极形成于凹陷中。
在一些实施例中,HEMT元件的制造方法更包括:在HEMT元件的第二区内的阻障层上形成第二栅极;以及在第二区内形成第二漏极与第二源极,其中第二漏极与第二源极分别位于第二栅极的相对两侧。
在一些实施例中,HEMT元件的制造方法更包括:在HEMT元件的第三区内的通道层与阻障层中形成第一电极;以及在第三区内的阻障层上形成第二电极,其中第一电极位于第二电极的一侧。
基于上述,本发明实施例的HEMT具有立体的通道结构。此立体通道结构具有极性的表面与非极性的表面。阻障层与通道结构的具有极性表面的部分所形成的异质结在不施予偏压的情况下即可形成二维电子气(或二维电洞气)。另一方面,阻障层与通道结构的具有非极性表面的部分所形成的异质结在不施予偏压的情况下则不产生二维电子气(或二维电洞气)。换言之,在不施予栅极电压的情况下,此不连续的二维电子气(或二维电洞气)可视为中断的导电通道。需额外施加适当的栅极电压方可形成连续的导电通道。因此,上述的HEMT可为增强型HEMT,或称通道常关型HEMT。考虑起始电压,增强型HEMT有利于电路的设计,而可广泛受到应用。在一些实施例中,HEMT元件更可整合增强型HEMT、空乏型HEMT与萧特基二极管,而可作为逻辑集成电路。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附图式作详细说明如下。
附图说明
图1是依照本发明一些实施例的高电子迁移率晶体管(high electron mobilitytransistor,HEMT)元件的制造方法的流程图;
图2A至图2H是图1所示的HEMT元件的制造方法的各阶段的结构的剖视示意图;
图3是依照本发明一些实施例的HEMT元件的剖视示意图;
图4A与图4B是依照本发明一些实施例的HEMT元件的制造方法的一些阶段的结构的剖视示意图。
附图标号
10、20、30:HEMT元件
100:衬底
102:通道材料层
102a:通道层
102B:主体部
102E:突出部
104:阻障层
AR1、AR2、AR3:主动区
BS1、BS2:底面
C:内连线结构
D:二极管
DE1:第一漏极
DE2:第二漏极
DR1、DR2:漏极区
E1:第一电极
E2:第二电极
EG:二维电子气
ER:电极区
GE1、GE1a、GE1b:第一栅极
GE2:第二栅极
IS:隔离结构
R1:第一区
R2:第二区
R3:第三区
RS1:第一凹陷
RS2:第二凹陷
RS3:第三凹陷
RS4:第四凹陷
RS5、RS6:凹陷
S100、S102、S104、S106、S108、S110、S112、S114、S116、S118、S120:步骤
SE1:第一源极
SE2:第二源极
SR1、SR2:源极区
SW1、SW2:侧壁
T1、T2:晶体管
θ1、θ2:夹角
具体实施方式
图1是依照本发明一些实施例的高电子迁移率晶体管(high electron mobilitytransistor,HEMT)元件10的制造方法的流程图。图2A至图2H是图1所示的HEMT元件10的制造方法的各阶段的结构的剖视示意图。在一些实施例中,HEMT元件10的制造方法包括下列步骤。
请参照图1与图2A,进行步骤S100,提供衬底100。在一些实施例中,衬底100包括半导体衬底或半导体上覆绝缘体(semiconductor on insulator,SOI)衬底。半导体衬底或SOI衬底中的半导体材料可包括元素半导体、合金半导体或化合物半导体。举例而言,元素半导体可包括Si或Ge。合金半导体可包括SiGe、SiGeC等。化合物半导体可包括SiC、III-V族半导体材料或II-VI族半导体材料。III-V族半导体材料可包括GaN、GaP、GaAs、AlN、AlP、AlAs、InN、InP、InAs、GaNP、GaNAs、GaPAs、AlNP、AlNAs、AlPAs、InNP、InNAs、InPAs、GaAlNP、GaAlNAs、GaAlPAs、GaInNP、GaInNAs、GaInPAs、InAlNP、InAlNAs或InAlPAs。II-VI族半导体材料可包括CdS、CdSe、CdTe、ZnS、ZnSe、ZnTe、HgS、HgSe、HgTe、CdSeS、CdSeTe、CdSTe、ZnSeS、ZnSeTe、ZnSTe、HgSeS、HgSeTe、HgSTe、CdZnS、CdZnSe、CdZnTe、CdHgS、CdHgSe、CdHgTe、HgZnS、HgZnSe、HgZnTe、CdZnSeS、CdZnSeTe、CdZnSTe、CdHgSeS、CdHgSeTe、CdHgSTe、HgZnSeS、HgZnSeTe或HgZnSTe。此外,半导体材料可经掺杂为第一导电型或与第一导电型互补的第二导电型。举例而言,第一导电型可为N型,而第二导电型可为P型。
在一些实施例中,衬底100可具有第一区R1、第二区R2以及第三区R3。第一区R1、第二区R2以及第三区R3可彼此相连,也可彼此分离。在一些实施例中,第二区R2位于第一区R1与第三区R3之间,但本发明实施例并不以此为限。在后续的步骤中,可在第一区R1内形成增强型(enhancement mode)HEMT(如图2H所示的晶体管T1)。在一些实施例中,可在第二区R2内形成耗尽型(depletion mode)HEMT(如图2H所示的晶体管T2)。在其他实施例中,也可在第二区R2内形成另一增强型HEMT(未绘示),其导电型与第一区R1内的增强型HEMT(例如是图2H所示的晶体管T1)互补。此外,在一些实施例中,可在第三区R3内形成萧特基二极管(schottky diode)(例如是图2H所示的二极管D)。然而,所属领域中技术人员可依据设计需求在第二区R2与第三区R3内设置其他半导体元件,本发明实施例并不以此为限。
请参照图1与图2B,进行步骤S102,在衬底100上形成通道材料层102。在一些实施例中,通道材料层102可实质上全面地覆盖于衬底100上。换言之,通道材料层102可位于第一区R1、第二区R2与第三区R3内。在一些实施例中,通道材料层102的材料可包括III族氮化物或III-V族化合物半导体材料。举例而言,通道材料层102的材料包括GaN。通道材料层102的形成方法可包括外延工艺(epitaxial process)。此外,通道材料层102的厚度范围可为100nm至900nm。在一些实施例中,通道材料层102的顶面可为极性面。举例而言,通道材料层102的顶面可为{0001}面。由此可知,通道材料层102与另一III族氮化物或III-V族化合物半导体材料所形成的异质结(hetero junction)可产生自发性极化与压电极化效应,而在此介面附近形成高浓度的二维电子气(two dimensional electron gas,2DEG)或二维电洞气(two dimensional hole gas,2DHG)。
在一些实施例中,在形成通道材料层102之前,可在衬底100上形成缓冲层(未绘示)。如此一来,缓冲层可位于衬底100与通道材料层102之间。在一些实施例中,缓冲层可实质上全面地覆盖于衬底100上。换言之,缓冲层可位于第一区R1、第二区R2与第三区R3内。在一些实施例中,缓冲层的材料可包括III族氮化物或III-V族化合物半导体材料。举例而言,缓冲层的材料可包括InAlGaN、AlGaN、AlInN、InGaN、AlN、GaN或其组合。缓冲层的形成方法可包括外延工艺。藉由设置缓冲层,可降低由衬底100与通道材料层102之间的晶格常数差异及/或热膨胀系数差异所造成的应力。
请参照图1与图2C,进行步骤S104,图案化通道材料层102的位于第一区R1内的一部分,以形成通道层102a。在一些实施例中,图案化通道材料层102的方法包括自通道材料层102的位于第一区R1内的表面移除通道材料层102的一些部分,以使所形成的通道层102a的顶部具有第一凹陷RS1与第二凹陷RS2。第一凹陷RS1与第二凹陷RS2位于第一区R1内,且彼此相邻。此外,第一凹陷RS1与第二凹陷RS2可定义出后续形成于第一区R1内的晶体管(例如是图2G所示的晶体管T1)的主动区AR1、漏极区DR1以及源极区SR1。具体而言,主动区AR1包括通道层102a的交迭于第一凹陷RS1与第二凹陷RS2的部分,且包括通道层102a的位于第一凹陷RS1与第二凹陷RS2之间的部分。漏极区DR1位于通道层102a的第二凹陷RS2与第一区R1/第二区R2的交界之间的区域中,而源极区SR1位于通道层102a的第一凹陷RS1与第一区R1的另一边界之间的区域中。然而,漏极区DR1与源极区SR1的位置也可相互对调,本发明并不以此为限。在一些实施例中,第一凹陷RS1与第二凹陷RS2之间的间距可为0.5μm至5μm。第一凹陷RS1与第二凹陷RS2的宽度可分别为1μm至20μm。此外,第一凹陷RS1与第二凹陷RS2的深度可分别为50μm至500μm。
藉由形成第一凹陷RS1与第二凹陷RS2,通道层102a的表面不再全为极性面,而是包括极性面与实质上正交于极性面的非极性面。在一些实施例中,在主动区AR1内,通道层102a的表面包括极性面与非极性面。具体而言,第一凹陷RS1的侧壁SW1为非极性面,且第一凹陷RS1的底面BS1为极性面。举例来说,第一凹陷RS1的侧壁SW1为{10-10}面,而第一凹陷RS1的底面BS1为{0001}面。相似地,第二凹陷RS2的侧壁SW2为非极性面(例如是{10-10}面),且第二凹陷RS2的底面BS2为极性面(例如是{0001}面)。此外,通道层102a的第一凹陷RS1与第二凹陷RS2以外的表面亦属极性面。举例而言,通道层102a的位于第一凹陷RS1与第二凹陷RS2之间的部分的顶面为极性面,例如是{0001}面。在一些实施例中,第一凹陷RS1的侧壁SW1实质上垂直于底面BS1,且第二凹陷RS2的侧壁SW2实质上垂直于底面BS2。在其他实施例中,侧壁SW1与底面BS1之间的夹角θ1以及底面BS2与侧壁SW2之间的夹角θ2可分别为70°至90°。
此外,通道层102a的位于主动区AR1内的部分也可视为具有主体部102B与突出部102E。主体部102B沿着实质上平行于衬底100的表面的方向延伸,而突出部102E沿实质上垂直于衬底100的表面的方向自主体部102B突出。主体部102B的表面为极性面。另一方面,突出部102E的顶面为极性面,而突出部102E的侧壁为非极性面。在一些实施例中,突出部102E的高度范围为50μm至500μm。
在一些实施例中,在图案化通道材料层102的位于第一区R1内的部分时,也可一并对通道材料层102的位于第二区R2与第三区R3内的部分进行图案化。在一些实施例中,可自通道材料层102的位于第二区R2内的表面移除通道材料层102的一部分,以形成第三凹陷RS3。如此一来,可定义出后续形成于第二区R2内的晶体管(如图2G所示的晶体管T2)的主动区AR2、漏极区DR2以及源极区SR2。主动区AR2包括通道层102a的交迭于第三凹陷RS3的部分。漏极区DR2位于通道层102a的第三凹陷RS3与第二区R2/第三区R3的交界之间的区域中,而源极区SR2位于通道层102a的第三凹陷RS3与第一区R1/第二区R2的交界之间的区域中。然而,漏极区DR2与源极区SR2的位置也可相互对调,本发明并不以此为限。此外,可自通道材料层102的位于第三区R3内的表面移除通道材料层102的一部分,以形成第四凹陷RS4。第四凹陷RS4的一端可延伸至第三区R3的边界。藉由设置第四凹陷RS4,可定义出后续形成于第三区R3内的二极管(如图2G所示的二极管D)的主动区AR3以及电极区ER。主动区AR3包括通道层102a的交迭于第四凹陷RS4的部分,而电极区ER位于通道层102a的第四凹陷RS4与第二区R2/第三区R3的交界之间的区域中。相似于第一凹陷RS1与第二凹陷RS2,第三凹陷RS3与第四凹陷RS4的底面可为极性面,而侧壁可为非极性面。另外,相较于第一区R1内的主动区AR1,第二区R2与第三区R3内的主动区AR2与主动区AR3具有实质上平坦的表面,且均为极性面。
请参照图1与图2D,进行步骤S106,在通道层102a上共形地形成阻障层104。在一些实施例中,阻障层104可全面地覆盖于通道层102a上。换言之,阻障层104位于第一区R1、第二区R2以及第三区R3内。在一些实施例中,阻障层104的材料可包括III族氮化物或III-V族化合物半导体材料。举例而言,阻障层104的材料包括InAlGaN、AlGaN、AlInN、AlN或其组合。在一些实施例中,阻障层104的材料为AlxGa1-xN,其中x为0.1至0.9。在另一些实施例中,阻障层104的材料为InyAl1-yGaN,其中y为0.1至0.9。在一些实施例中,阻障层104的形成方法包括外延工艺。此外,阻障层104的厚度可大于10nm,例如是10nm至100nm。如此一来,阻障层104与通道层102a的具有极性表面的部分所形成的异质结可藉由自发性极化效应与压电性极化效应而产生二维电子气EG。二维电子气EG可位于通道层102a中,且靠近通道层102a与阻障层104之间的介面。另一方面,阻障层104与通道层102a的具有非极性表面的部分所形成的异质结则不产生二维电子气。换言之,二维电子气EG仅沿着通道层102a的极性面延伸,而在非极性面处中断。举例而言,在第一区R1内的主动区AR1中,二维电子气EG沿着通道层102a的主体部102B的表面以及突出部102E的顶面延伸,而在突出部102E的侧壁处中断。在不施加偏压的情况下,此不连续的二维电子气EG可视为中断的导电通道。需额外施加偏压方可形成连续的导电通道。因此,后续形成于第一区R1内的晶体管可为增强型HEMT,或称通道常关型(normally off)HEMT。此外,此增强型HEMT属于第一导电型(例如是N型)。
在第二区R2内的主动区AR2中,二维电子气EG则是连续地沿着通道层102a的表面延伸。在一些实施例中,后续形成于第二区R2内的晶体管可为耗尽型HEMT,或称通道常开型(normally on)HEMT。此外,此耗尽型HEMT可为第一导电型(例如是N型)。相似地,在第三区R3内的主动区AR3中,二维电子气EG亦连续地沿着通道层102a的表面延伸。在一些实施例中,可在第三区R3内形成萧特基二极管。
在替代实施例中,阻障层104可掺杂有第二导电型(例如是P型)掺质。举例而言,第二导电型掺质可为Mg。如此一来,阻障层104与通道层102a的具有极性表面的部分所形成的异质结可藉由自发性极化效应与压电性极化效应而产生二维电洞气(two dimensionalhole gas,2DHG)(未绘示)。二维电洞气的位置与图2D所示的二维电子气EG相同,惟所带电荷不同。在这些实施例中,形成于第一区R1与第二区R2内的晶体管可为第二导电型(例如是P型)。
请参照图1与图2E,进行步骤S108,在第一区R1内的阻障层104上形成第一栅极GE1。在一些实施例中,第一栅极GE1形成于通道层102a的突出部102E上。在一些实施例中,第一栅极GE1更延伸至突出部102E的侧壁上,且可覆盖通道层102a的主体部102B的一部分顶面。在这些实施例中,第一栅极GE1更延伸至第一凹陷RS1与第二凹陷RS2中。如此一来,第一栅极GE1覆盖通道层102a的非极性面与极性面。在第一栅极GE1并未被施予偏压时,在第一栅极GE1下方的二维电子气EG并非为连续,故可作为常关型导电通道。需对第一栅极GE1施加适当的偏压,方可形成连续的导电通道。在一些实施例中,第一栅极GE1的材料可包括金属或金属氮化物(例如Ta、TaN、Ti、TiN、W、Pd、Ni、Au、Al或其组合)、金属硅化物(例如WSix)或其他可与阻障层104形成萧特基接触(schottky contact)的材料。形成第一栅极GE1的方法可包括化学气相沉积法、物理气相沉积法(例如是溅射等)或其组合。在一些实施例中,第一栅极GE1的厚度范围可为0.3nm至1000nm。
在一些实施例中,进行步骤S110,在第二区R2内的阻障层104上形成第二栅极GE2。在一些实施例中,第二栅极GE2设置于主动区AR2内,且位于第三凹陷RS3的底面上。第三凹陷RS3的底面为极性面,且二维电子气EG沿第三凹陷RS3的底面连续地延伸。换言之,在第二栅极GE2并未被施予偏压时,第二栅极GE2下方的二维电子气EG即可为连续的,故可作为常开型的导电通道。第二栅极GE2的材料为能够与阻障层104形成萧特基接触的材料。在一些实施例中,第一栅极GE1与第二栅极GE2可由相同的材料构成。此外,在一些实施例中,可同时进行步骤S108与步骤S110,以同时形成第一栅极GE1与第二栅极GE2。在其他实施例中,第二栅极GE2的材料也可相异于第一栅极GE1的材料,且可在不同工艺步骤中形成第一栅极GE1与第二栅极GE2。
请参照图1与图2F,进行步骤S112,在第一区R1内形成第一漏极DE1与第一源极SE1。第一漏极DE1与第一源极SE1位于第一栅极GE1的相对两侧。此外,第一漏极DE1与第一源极SE1可分别与通道层102a及/或阻障层104形成欧姆接触(ohmic contact)。在一些实施例中,可藉由例如是离子掺杂的方法将掺质植入于通道层102a的位于漏极区DR1与源极区SR1内的部分以及上覆的阻障层104中,以分别形成第一漏极DE1与第一源极SE1。在一些实施例中,用于形成第一漏极DE1与第一源极SE1的掺质可包括Si、W或其类似者。第一漏极DE1与第一源极SE1的掺杂浓度范围可分别为1019至5×1020。在一些实施例中,第一漏极DE1与第一源极SE1可沿实质上垂直于衬底100的表面的方向贯穿通道层102a。至此,已在第一区R1内形成晶体管T1。晶体管T1包括通道层102a、阻障层104的位于第一区R1内的部分,且包括第一栅极GE1、第一漏极DE1与第一源极SE1。晶体管T1可为增强型HEMT(或称为常关型HEMT),且可属于第一导电型(例如是N型)。
进行步骤S114,在第二区R2内形成第二漏极DE2与第二源极SE2。第二漏极DE2与第二源极SE2位于第二栅极GE2的相对两侧。此外,第二漏极DE2与第二源极SE2可分别与通道层102a及/或阻障层104形成欧姆接触。在一些实施例中,可藉由例如是离子掺杂的方法将掺质植入于通道层102a的位于漏极区DR1与源极区SR2内的部分以及上覆的阻障层104中,以分别形成第二漏极DE2与第二源极SE2。在一些实施例中,可以相同的掺质以及实质上相同的掺杂浓度形成第一漏极DE1、第一源极SE1、第二漏极DE2与第二源极SE2。在一些实施例中,第二漏极DE2与第二源极SE2可沿实质上垂直于衬底100的表面的方向贯穿通道层102a。至此,已在第二区R2内形成晶体管T2。晶体管T2包括通道层102a、阻障层104的位于第二区R2内的部分,且包括第二栅极GE2、第二漏极DE2与第二源极SE2。晶体管T2可为耗尽型HEMT(或称为常开型HEMT),且可属于第一导电型(例如是N型)。
进行步骤S116,在第三区R3内形成第一电极E1。在一些实施例中,可藉由例如是离子掺杂的方法将掺质植入于通道层102a的位于电极区ER内的部分以及上覆的阻障层104中,以形成第一电极E1。在一些实施例中,可以相同的掺质以及实质上相同的掺杂浓度形成第一电极E1、第一漏极DE1、第一源极SE1、第二漏极DE2与第二源极SE2。在一些实施例中,第一电极E1可沿实质上垂直于衬底100的表面的方向贯穿通道层102a。第一电极E1可作为形成于第三区R3内的萧特基二极管(如图2G所示的二极管D)的其中一电极。
在一些实施例中,可同时进行步骤S112、步骤S114与步骤S116,以同时形成第一漏极DE1、第一源极SE1、第二漏极DE2、第二源极SE2以及第一电极E1。然而,所属领域中技术人员可依据工艺需求调整这些电极的形成顺序以及个别的工艺参数,本发明实施例并不以此为限。
在另一些实施例中,晶体管T1的漏极与源极也可经形成于第一栅极GE1的相对两侧的阻障层104上。相似地,晶体管T2的漏极与源极也可经形成于第二栅极GE2的相对两侧的阻障层104上。在这些实施例中,可藉由例如是化学气相沉积法或物理气相沉积法(例如是溅射)形成晶体管T1与晶体管T2的漏极与源极。此外,该漏极与源极的材料可为金属、金属氮化物、金属硅化物或其他可与阻障层104形成欧姆接触的材料。
请参照图1与图2G,进行步骤S118,在第三区R3内的阻障层104上形成第二电极E2。第二电极E2位于第一电极E1的一侧,且位于主动区AR3内。在一些实施例中,第二电极E2设置于通道层102a的第四凹陷RS4中,且交迭于通道层102a的极性面。第二电极E2可由能与阻障层104形成萧特基接触的材料构成。在一些实施例中,第二电极E2的材料可包括Ni、TiN、Pd、Pt、Cr、Mo、W、其类似者或其组合。形成第二电极E2的方法可包括化学气相沉积法、物理气相沉积法(例如是溅射等)或其组合。在一些实施例中,第二电极E2的厚度范围可为0.5nm至1000nm。至此,已在第三区R3内形成二极管D。二极管D可为萧特基二极管,且包括通道层102a与阻障层104的位于第三区R3内的部分,且包括第一电极E1与第二电极E2。
请参照图1与图2H,进行步骤S120,形成隔离结构IS以及内连线结构C。隔离结构IS经设置以电气隔离晶体管T1、晶体管T2与二极管D。在一些实施例中,形成隔离结构IS的方法包括移除位于第一区R1与第二区R2的交界处的第一漏极DE1的一部分与第二源极SE2的一部分,且填入绝缘材料。相似地,移除位于第二区R2与第三区R3的交界处的第二漏极DE2的一部分与第一电极E1的一部分,且填入绝缘材料。如此一来,可在晶体管T1与晶体管T2之间以及晶体管T2与二极管D之间形成隔离结构IS。在一些实施例中,隔离结构IS的材料可包括氧化硅、氮化硅、其类似者或其组合。在其他实施例中,也可藉由离子植入的方式形成隔离结构IS。离子植入工艺所使用的掺质可包括Ar、N2等。在这些实施例中,可省略移除部分的第一漏极DE1与第二源极SE2的步骤。另一方面,内连线结构C电连接于晶体管T1、晶体管T2与二极管D的各电极。在一些实施例中,形成内连线结构C的方法可包括在衬底100上形成一或多层绝缘层(省略绘示),接着在绝缘层中形成暴露出晶体管T1、晶体管T2与二极管D的各电极的开口(via)及/或沟渠(trench)。随后,在这些开口与沟渠中形成导电材料,而形成内连线结构C。
至此,已形成本发明一些实施例的HEMT元件10。HEMT元件10可包括晶体管T1、晶体管T2与二极管D。晶体管T1与晶体管T2可为HEMT。在一些实施例中,晶体管T1为增强型HEMT,而晶体管T2为耗尽型HEMT。此外,晶体管T1与晶体管T2均可为第一导电型(例如是N型)或均可为第二导电型(例如是P型)。在另一些实施例中,晶体管T1与晶体管T2均可为增强型HEMT,只彼此为互补的导电型(例如是N型与P型)。另一方面,二极管D可为萧特基二极管。
图3是依照本发明一些实施例的HEMT元件20的剖视示意图。
请参照图2H与图3,图3所示的HEMT元件20相似于图2H所示的HEMT元件10,只第一栅极的结构不同。具体而言,HEMT元件20的第一栅极GE1a设置于通道层102a的突出部102E上,但不延伸至突出部102E的侧壁。换言之,第一栅极GE1a并未延伸至第一凹陷RS1与第二凹陷RS2中。在这些实施例中,第一栅极GE1a仅覆盖通道层102a的极性面,而并未覆盖通道层102a的非极性面。相较于图2H所示的实施例,图3所示的第一栅极GE1a与二维电子气EG的中断处(靠近通道层102a的非极性面)之间的距离较长。因此,需提高栅极电压方可在晶体管T1的导通状态于通道层102a内形成连续的导电通道。
图4A与图4B是依照本发明一些实施例的HEMT元件30的制造方法的一些阶段的结构的剖视示意图。图4A与图4B所示的实施例与图1及图2A至图2H所示的实施例相似,以下仅描述两者的差异处,相同或相似处则不再赘述。
请参照图1、图2B以及图4A,在步骤S104中,图案化通道材料层102的方法包括自通道材料层102的位于第一区R1内的表面移除通道材料层102的一部分,以使所形成的通道层102a的顶部具有凹陷RS5与凹陷RS6。凹陷RS5与凹陷RS6彼此连通,且凹陷RS6位于凹陷RS5的底部。在一些实施例中,凹陷RS5定义出后续形成于第一区R1内的晶体管(例如是图4B所示的晶体管T1)的主动区AR1、漏极区DR1以及源极区SR1。凹陷RS6位于主动区AR1内。藉由形成凹陷RS6,可暴露出通道层102的非极性面。具体而言,凹陷RS6的侧壁为非极性面(例如是{10-10}面),而凹陷RS6的底面为极性面(例如是{0001}面)。在一些实施例中,凹陷RS6的侧壁实质上垂直于底面。在其他实施例中,凹陷RS6的侧壁与底面之间的夹角可为70°至90°。
请参照图1与图4B,随后可进行如图1所示的步骤S106至步骤S120,以形成HEMT元件30。第一栅极GE1b形成于凹陷RS6中,而覆盖通道层102a的极性面与非极性面。在一些实施例中,第一栅极GE1b更延伸至凹陷RS5的底面上。在第一区R1内的主动区AR1中,阻障层104与通道层102的具有极性表面的部分所形成的异质结可形成二维电子气EG(或二维电洞气)。另一方面,阻障层104与通道层102a的具有非极性表面的部分所形成的异质结则不产生二维电子气(或二维电洞气)。在不施加偏压的情况下,此不连续的二维电子气EG(或二维电洞气)可视为中断的导电通道。需额外施加偏压方可形成连续的导电通道。因此,相似于图2H所示的实施例,形成于图4B所示的第一区R1内的晶体管T1亦可为增强型HEMT,或称通道常关型HEMT。
综上所述,本发明实施例的HEMT具有立体的通道结构。此立体通道结构具有极性的表面与非极性的表面。阻障层与通道结构的具有极性表面的部分所形成的异质结在不施予偏压的情况下即可形成二维电子气(或二维电洞气)。另一方面,阻障层与通道结构的具有非极性表面的部分所形成的异质结在不施予偏压的情况下则不产生二维电子气(或二维电洞气)。换言之,在不施予栅极电压的情况下,此不连续的二维电子气(或二维电洞气)可视为中断的导电通道。需额外施加适当的栅极电压方可形成连续的导电通道。因此,上述的HEMT可为增强型HEMT,或称通道常关型HEMT。考虑起始电压,增强型HEMT有利于电路的设计,而可受到广泛应用。在一些实施例中,HEMT元件更可整合增强型HEMT、耗尽型HEMT与萧特基二极管,而可作为逻辑集成电路。
虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视前附的权利要求所界定者为准。

Claims (16)

1.一种高电子迁移率晶体管元件,其特征在于,包括:
通道层,设置于衬底上,其中所述通道层在所述高电子迁移率晶体管元件的第一区内的表面包括极性面与非极性面;
阻障层,共形地设置于所述通道层上;
第一栅极,设置于所述阻障层上,且位于所述第一区内;以及
第一漏极与第一源极,设置于所述第一区内,且分别位于所述第一栅极的相对两侧。
2.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述阻障层全面地覆盖于所述通道层上。
3.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述极性面与所述非极性面实质上正交。
4.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述通道层包括主体部与突出部,所述突出部沿实质上垂直于所述衬底的表面的方向自所述主体部突出,所述突出部的侧壁为所述非极性面,且所述突出部的顶面为所述极性面的一部分。
5.如权利要求4所述的高电子迁移率晶体管元件,其特征在于,所述第一栅极覆盖所述突出部的所述顶面。
6.如权利要求4所述的高电子迁移率晶体管元件,其特征在于,所述第一栅极覆盖所述突出部的所述顶面与所述侧壁。
7.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述通道层具有凹陷,所述凹陷的侧壁为所述非极性面,所述凹陷的底面为所述极性面的一部分,且其中所述第一栅极的至少一部分位于所述凹陷中。
8.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述通道层在所述高电子迁移率晶体管元件的第二区内的顶面包括极性面,且所述高电子迁移率晶体管元件更包括:
第二栅极,设置于所述阻障层的位于所述第二区内的部分上;以及
第二漏极与第二源极,设置于所述第二区内,且位于所述第二栅极的相对两侧。
9.如权利要求1所述的高电子迁移率晶体管元件,其特征在于,所述通道层在所述高电子迁移率晶体管元件的第三区内的顶面包括极性面,且所述高电子迁移率晶体管元件更包括:
第一电极,设置于所述通道层与所述阻障层中且位于所述第三区内;以及
第二电极,设置于所述阻障层的位于所述第三区内的部分上,且位于所述第一电极的一侧。
10.一种高电子迁移率晶体管元件的制造方法,其特征在于,包括:
在衬底上形成通道材料层;
图案化所述通道材料层的位于所述高电子迁移率晶体管元件的第一区内的一部分,以形成通道层,其中所述通道层在所述第一区内的表面包括极性面与非极性面;
在所述通道层上共形地形成阻障层;
在所述第一区内的所述阻障层上形成第一栅极;以及
在所述第一区内形成第一漏极与第一源极,其中所述第一漏极与所述第一源极分别位于所述第一栅极的相对两侧。
11.如权利要求10所述的高电子迁移率晶体管元件的制造方法,其特征在于,图案化所述通道材料层的位于所述第一区内的所述部分的方法包括自所述通道材料层的表面移除一些部分的所述通道材料层,以使所述通道层的顶部具有相邻的第一凹陷与第二凹陷,其中所述第一凹陷与所述第二凹陷的侧壁为所述非极性面,且所述第一凹陷与所述第二凹陷的底面为所述极性面的一部分。
12.如权利要求11所述的高电子迁移率晶体管元件的制造方法,其特征在于,所述第一栅极形成于所述通道层的位于所述第一凹陷与所述第二凹陷之间的部分上。
13.如权利要求12所述的高电子迁移率晶体管元件的制造方法,其特征在于,所述第一栅极更延伸至所述第一凹陷与所述第二凹陷中。
14.如权利要求10所述的高电子迁移率晶体管元件的制造方法,其特征在于,图案化所述通道材料层的位于所述第一区内的所述部分的方法包括在所述通道材料层的表面形成凹陷,其中所述凹陷的侧壁为所述非极性面,且所述凹陷的底面为所述极性面的一部分,其中所述第一栅极形成于所述凹陷中。
15.如权利要求10所述的高电子迁移率晶体管元件的制造方法,其特征在于,更包括:
在所述高电子迁移率晶体管元件的第二区内的所述阻障层上形成第二栅极;以及
在所述第二区内形成第二漏极与第二源极,其中所述第二漏极与所述第二源极分别位于所述第二栅极的相对两侧。
16.如权利要求10所述的高电子迁移率晶体管元件的制造方法,其特征在于,更包括:
在所述高电子迁移率晶体管元件的第三区内的所述通道层与所述阻障层中形成第一电极;以及
在所述第三区内的所述阻障层上形成第二电极,其中所述第一电极位于所述第二电极的一侧。
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