TWI604605B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI604605B
TWI604605B TW105141643A TW105141643A TWI604605B TW I604605 B TWI604605 B TW I604605B TW 105141643 A TW105141643 A TW 105141643A TW 105141643 A TW105141643 A TW 105141643A TW I604605 B TWI604605 B TW I604605B
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layer
ferroelectric material
recess
semiconductor device
barrier layer
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TW105141643A
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TW201824542A (zh
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張翼
劉世謙
黃崇愷
吳佳勳
韓秉承
林岳欽
謝廷恩
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國立交通大學
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Priority to TW105141643A priority Critical patent/TWI604605B/zh
Priority to CN201710048777.9A priority patent/CN108231863B/zh
Priority to JP2017053220A priority patent/JP6305596B1/ja
Priority to US15/644,830 priority patent/US20180175185A1/en
Priority to DE102017119774.5A priority patent/DE102017119774B4/de
Priority to KR1020170118416A priority patent/KR101955195B1/ko
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Publication of TWI604605B publication Critical patent/TWI604605B/zh
Publication of TW201824542A publication Critical patent/TW201824542A/zh
Priority to US16/809,529 priority patent/US11670699B2/en
Priority to US18/303,585 priority patent/US20230261083A1/en

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Description

半導體裝置及其製造方法
本發明係有關一種半導體裝置及其製造方法，特別是關於一種高電子遷移率電晶體。
在半導體技術中，III-V族半導體化合物可用於形成各種積體電路裝置，例如高功率場效電晶體、高頻電晶體或高電子遷移率電晶體(High electron mobility transistor,HEMT)，此III-V族半導體化合物具有取代傳統矽電晶體之潛力。
然而，當III-V族半導體化合物為氮化鎵或氧化鎵時，通道將呈現常開型(normally-on)的狀態，由於常開模式之電晶體其臨界電壓(threshold voltage)為負值，即電晶體在零閘極偏壓時，電晶體仍會導通電流並形成額外之功率損耗。目前，解決此問題之方法，例如減薄氮化鎵層、離子佈植、或利用p型氧化鎵調整能帶結構使其臨界電壓大於0V，但由於電晶體在應用時，閘極電壓會隨著汲極偏壓 有一不穩定之擾動造成誤啟動之現象，故其電晶體之臨界電壓需大於6V以上才能有效避免誤啟動現象發生，故需要進行改良。目前學術及業界所使用避免誤啟動的方式大多屬於增加額外電路進行改良，但此方法會形成寄生效應造成不必要之能量耗損，此外也會增加製造成本。本專利闡述之技術不但能夠使臨界電壓大於6V且具有良好的元件特性。
根據本發明之多個實施方式，係提供一種半導體裝置，包含：基材、通道層、阻障層、凹槽、汲極、源極、電荷陷阱層、鐵電材料和閘極；通道層配置於基材上；阻障層配置於通道層上，阻障層具有凹槽，且凹槽下方之阻障層具有一厚度；汲極和源極配置於阻障層上；電荷陷阱層覆蓋凹槽的底面；鐵電材料配置於電荷陷阱層上；以及閘極配置於鐵電材料上。
在某些實施方式中，半導體裝置更包含第一介電層配置於凹槽的底面和電荷陷阱層之間。
在某些實施方式中，半導體裝置更包含第二介電層配置於鐵電材料和閘極之間。
在某些實施方式中，第一介電層具有一能隙(bandgap)，能隙介於7-12eV。
在某些實施方式中，凹槽下方之阻障層厚度介 於5-12nm。
在某些實施方式中，鐵電材料為BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9或PbZrTiO3。
本發明之多個實施方式，係提供一種製造半導體裝置的方法，包含：提供一基材；形成通道層於基材上；形成阻障層於通道層上；形成源極和汲極於阻障層上；形成凹槽於阻障層中，凹槽具有底面，凹槽下方之阻障層具有厚度；形成電荷陷阱層覆蓋凹槽的底面；形成鐵電材料於電荷陷阱層上；將鐵電材料加熱至第一溫度，第一溫度大於鐵電材料之結晶溫度；將鐵電材料降溫至第二溫度，使鐵電材料結晶；以及形成閘極於鐵電材料上。
在某些實施方式中，在形成凹槽於阻障層後，更包含形成第一介電層覆蓋凹槽的底面。
在某些實施方式中，形成鐵電材料的方法包含電漿輔助原子層沉積、有機金屬化學氣相沉積、化學氣相沉積、物理氣相沉積、濺鍍或脈衝雷射蒸鍍。
在某些實施方式中，第一溫度介於400-600℃。
為使本發明之上述及其他目的、特徵和優點更明顯易懂，下文特舉出較佳實施例，並配合所附圖示詳細說明如下。
110‧‧‧基材
112‧‧‧基板
114‧‧‧緩衝層
120‧‧‧通道層
130‧‧‧阻障層
210‧‧‧第一介電層
220‧‧‧電荷陷阱層
230‧‧‧鐵電材料
240‧‧‧第二介電層
250‧‧‧閘極
260‧‧‧鈍化層
R‧‧‧凹槽
S‧‧‧源極
D‧‧‧汲極
w‧‧‧寬度
d1‧‧‧深度
d2‧‧‧厚度
第1圖至第4C圖係繪示依照本發明各種實施方式之一種半導體裝置之製造方法之各製程階段的剖面示意圖。
第5A圖及第5B圖為根據本發明某些實施方式之半導體裝置的ID-VGS特性曲線。
以下將詳細討論本實施例的製造與使用，然而，應瞭解到，本發明提供實務的創新概念，其中可以用廣泛的各種特定內容呈現。下文敘述的實施方式或實施例僅為說明，並不能限制本發明的範圍。
此外，在本文中，為了易於描述圖式所繪的某個元件或特徵和其他元件或特徵的關係，可能會使用空間相對術語，例如「在…下方」、「在…下」、「低於」、「在…上方」、「高於」和類似用語。這些空間相對術語意欲涵蓋元件使用或操作時的所有不同方向，不只限於圖式所繪的方向而已。裝置可以其他方式定向(旋轉90度或定於另一方向)，而本文使用的空間相對描述語則可相應地進行解讀。
以下提供各種關於半導體裝置及其製作方法的實施例，其中詳細說明此半導體裝置的結構和性質以及此半導體裝置的製備步驟或操作。
高電子遷移率電晶體(High electron mobility transistor,HEMT)由於具有高輸出功率、高崩潰電壓、耐高溫等優良特性，近年來已被廣泛應用於高功率電路系統中。而傳統之高電子遷移率電晶體由於結構中通道層和阻障層之間具大量極化電荷，這些極化電荷形成二維電子氣(two dimensional electron gas,2DEG)，使電子具有高遷移率。此時電晶體在無施加閘極偏壓時，仍會導通電流，因此被稱為常開式(normally-on)電晶體。常開式電晶體的臨界電壓(threshold voltage)為負值，即電晶體在零閘極偏壓時，電晶體仍會導通電流，形成額外之功率損耗，此外，常開式電晶體無法避免失效安全之意外，具有潛在危險性。因此，常關式電晶體之技術發展為目前高功率電晶體之重要課題，此外，由於高功率電路系統需在高偏壓的環境下進行操作，在此高偏壓環境下，容易產生瞬間脈衝電壓，如果電晶體之臨界電壓不夠高，容易導致高功率元件不正常導通，造成電路之誤動作並影響電路系統之穩定度。因此本發明提供一種具有高臨界電壓的高電子遷移率電晶體裝置，即常關式(normally-off)的高電子遷移率電晶體，而且能同時維持高輸出電流。
第1圖至第4C圖係繪示依照本發明各種實施方式之一種半導體裝置之製造方法之各製程階段的剖面示意圖。
在第1圖中，提供基材110，基材110包含基板112和緩衝層114，緩衝層114配置於基板112上。基板112可為矽(Si)基材、碳化矽(SiC)基材、藍寶石(sapphire)基 材、氮化鎵(GaN)基材、氮化鋁鎵(AlGaN)基材、氮化鋁(AlN)基材、磷化鎵(GaP)基材、砷化鎵(GaAs)基材、砷化鋁鎵(AlGaAs)基材或其他包含III-V族元素之化合物形成之基材。在某些實施方式中，緩衝層114包含GaN或p型摻質摻雜的GaN。可使用磊晶製程或其他適當的方法形成緩衝層114。在一實施例中，p型摻質包含碳、鐵、鎂、鋅或其他適當的p型摻質。緩衝層可降低漏電流及避免形成通道層120時的磊晶製程中發生龜裂現象。在另一實施例中，基材110包含基板112、晶種層(未繪示)和緩衝層114。晶種層配置於基板112上，緩衝層114配置於晶種層上。晶種層有助於補償基板112和緩衝層114間晶格結構的錯配(mismatch)。
接著形成通道層120於基材110上，再形成阻障層130於通道層120上。基材通道層120可為氮化鋁鎵(AlGaN)、氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁銦鎵(AlInGaN)或其他包含III-V族元素之化合物。障壁層130可為氮化鋁(AlN)、氮化鋁銦(AlInN)、AlGaN、GaN、InGaN、AlInGaN或其他包含III-V族元素之化合物。通道層120之能隙小於阻障層130之能隙，且通道層120和阻障層130的組合和厚度必須能夠產生二維電子氣。在一實施方式中，通道層120或/及阻障層130可為多層結構。在另一實施方式中，可再形成其他層，例如在通道層120和阻障層130之間形成一中間層(未繪示)、形成一摻雜層(未繪示)於阻障 層130上方以增加二維電子氣的電子或形成一覆蓋層(未繪示)於阻障層130上以防止阻障層130氧化。
請參照第2圖，形成源極S和汲極D於阻障層130上。源極S和汲極D各自選於下列組合，包含但不限於銀(Ag)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、鋁(Al)、鎳(Ni)、釕(Ru)、鈀(Pd)、鉑(Pt)、錳(Mn)、氮化鎢(WN)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鋁(AlN)、矽化鎢(WSi)、氮化鉬(MoN)、矽化鎳(Ni2Si)、矽化鈦(TiSi2)、鋁化鈦(TiAl)、砷(As)摻雜之多晶矽、氮化鋯(ZrN)、TaC、TaCN、TaSiN、TiAlN、矽化物或其任意之組合。形成源極S和汲極D的方法可使用任何習知之製程。
如第3圖所示，利用圖案化製程在阻障層130中形成凹槽R。在一實施方式中，可在阻障層130上形成遮罩層，遮罩層例如為硬遮罩或光阻，並在遮罩層上形成圖案，再利用蝕刻製程將圖案轉移至底下的阻障層130中形成凹槽R，其中蝕刻製程可為反應式離子蝕刻、電漿乾式蝕刻或其他非等向性蝕刻方式，蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。在另一實施方式中，在形成遮罩層後使用濕式蝕刻製程蝕刻出凹槽R，使凹槽R的底角圓滑化。
凹槽R具有深度d1和寬度w，深度d1介於15-25nm，例如15nm、20nm或25nm；寬度w介於 0.1μm-3μm，例如0.5μm、1μm、2μm、2.5μm。凹槽R位於源極S和汲極D的中間而且並未貫穿阻障層130，目的在於削弱阻障層130之極化現象並消除二維電子氣通道之載子，使之臨界電壓大於0V。因較薄的阻障層會提升導帶能階，故減少閘極區域底下之阻障層厚度可驅趕(deplete)二維電子氣。凹槽R的底面和通道層120上表面之間的阻障層130具有厚度d2，厚度d2介於0-10nm，例如1nm、3nm、5nm或8nm。需要注意的是，若厚度d2的厚度大於10nm，會使阻障層130仍具有大量極化電荷，進而使通道成為常開型的狀態。
在某些實施方式中，凹槽R的寬度小於3μm，例如0.05μm、0.5μm、1μm或2μm。在某些實施方式中，凹槽R和源極S、汲極D的距離不同，在一實施例中，凹槽R的邊緣和源極S的距離介於1~3μm，例如1.5μm、2μm或2.5μm。凹槽R的邊緣和汲極D的距離介於5~15μm，例如7.5μm、10μm或12.5μm。
第4A-4C圖係提供不同的鐵電材料複合層實施方式。如第4A-4C圖所示，在形成凹槽R之後，形成鐵電材料複合層於凹槽內。形成鐵電材料複合層的方式包含但不限於電漿輔助原子層沉積、有機金屬化學氣相沉積、化學氣相沉積、物理氣相沉積、濺鍍或脈衝雷射蒸鍍。形成鐵電材料複合層之後可以選擇性地使用圖案化製程使鐵電材料複合 層的側面與凹槽R的側面切齊。在一實施方式中，鐵電材料複合層的寬度等於凹槽R的寬度w。
在第4A圖中，鐵電材料複合層包含電荷陷阱層220(或稱電荷儲存層)和鐵電材料230。電荷陷阱層220覆蓋凹槽R的底面，鐵電材料230配置於電荷陷阱層220上。閘極250配置於鐵電材料230上。鈍化層260覆蓋阻障層130。電荷陷阱層220可例如為氮化矽、HfON、HfO2、ZrO2、介電層或被絕緣材料所環繞之奈米晶體層。電荷陷阱層220的厚度介於1-4nm，例如1.5nm、2nm、2.5nm或3nm，取決於選用的材料之特性。在一實施方式中，電荷陷阱層220為多層結構，此多層結構可包含上述電荷陷阱層220材料的組合。在一實施方式中，鈍化層260可為AlN、Al2O3、AlON、SiN、SiO2、SiON或Si3N4。
在各種實施方式中，鐵電材料230可為BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9(SBT)、PbZrTiO3(PZT)或其他可引發鐵電效應的材料。所謂的鐵電效應，是指材料本身在外加電場之下，具備自發性極化(spontaneous polarization)及極化轉換(polarization transition)的特性。當施加外電場時，會使電偶極順著電場方向排列，而在電場移去後，仍能保持極化方向的殘留極化(remnant polarization,Pr)，此一效應稱為鐵電效應。對於任何鐵電材料而言，具有殘留極化表示其擁有永久極化 能力。在形成鐵電材料230後，使用熱退火處理，將鐵電材料230升溫至第一溫度，第一溫度高於鐵電材料230的結晶溫度，再將鐵電材料230降溫至一第二溫度，使鐵電材料230結晶形成鐵電材料。在實施方式中，第一溫度介於400-600℃，例如450℃、500℃或550℃。第二溫度介於25-100℃，例如25℃或80℃。
在第4B圖中，提供另一種鐵電材料複合層的實施方式。在此實施方式中，先形成第一介電層210於凹槽R內，再形成電荷陷阱層220於第一介電層210上，接著形成鐵電材料230於電荷陷阱層220上。之後形成閘極250於鐵電材料230上。鈍化層260覆蓋阻障層130。第一介電層210的功能為寬能隙阻擋層，具有一能隙(bandgap)，且此能隙介於7-12eV，例如8eV、9eV、11eV、13eV或15eV。第一介電層210能降低漏電流以及提升閘極崩潰電壓。第一介電層210可為Al2O3、SiO2或其他能隙介於7-12eV的材料。形成電荷陷阱層220和鐵電材料230的方法已在前文敘述過，故不再重複敘述。
在第4C圖中，提供另一種鐵電材料複合層的實施方式。鐵電材料複合層包含第一介電層210配置於凹槽內，電荷陷阱層220配置於第一介電層210，鐵電材料230配置於電荷陷阱層220上，第二介電層240配置於鐵電材料230上。閘極250配置於第二介電層240上。鈍化層260覆蓋 阻障層130。第二介電層240和第一介電層210皆為寬能隙阻擋層，具有一能隙(bandgap)，且此能隙介於7-12eV，例如8eV、9eV、11eV、13eV或15eV。第二介電層240能降低漏電流以及提升閘極崩潰電壓。第二介電層240可為Al2O3、SiO2或其他能隙介於7-12eV的材料。
在此半導體裝置中，當施加正電壓於閘極250時，鐵電材料230會極化並抓取電荷，而電荷陷阱層220提供儲存電荷的地方。此時閘極250和鐵電材料複合層下方的能隙便會開始改變，阻障層130之表面負電位開始增加，進而使半導體裝置之臨界電壓值往正方向移動。
在一實施方式中，鐵電材料230極化後，半導體裝置的臨界電壓變化值可大於5V，其臨界電壓從接近0V改變為大於5V，即成為增強型的半導體裝置。在另一實施方式中，可藉由調整凹槽R的深度來調整臨界電壓。在阻障層130厚度相同的情況下，當厚度d2越薄，半導體裝置的臨界電壓值會越往正值方向移動，但其最大汲極電流也會降低，因此厚度d2必須控制在一定的範圍內。
第5A圖及第5B圖為根據本發明某些實施方式之半導體裝置的ID-VGS特性曲線。曲線A代表鐵電材料230極化前，曲線B則代表鐵電材料230極化後。如第5A圖所示，鐵電材料230極化後，半導體裝置的臨界電壓(Vth)從極化前的2.5V變為10V。如第5B圖所示，此半導體裝置的 Ion/Ioff比值為6x108。
綜上所述，本發明之各實施例提供一種半導體裝置，利用鐵電材料之永久極化效應造成能帶變化，使半導體裝置擁有高臨界電壓以減低額外功率耗損並增加電路系統穩定度。
上文概述若干實施例之特徵結構，使得熟習此項技術者可更好地理解本發明之態樣。熟習此項技術者應瞭解，可輕易使用本發明作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本發明之精神及範疇，且可在不脫離本發明之精神及範疇的情況下做出對本發明的各種變化、替代及更改。
110‧‧‧基材
112‧‧‧基板
114‧‧‧緩衝層
120‧‧‧通道層
130‧‧‧阻障層
220‧‧‧電荷陷阱層
230‧‧‧鐵電材料
250‧‧‧閘極
260‧‧‧鈍化層
S‧‧‧源極
D‧‧‧汲極

Claims (10)

  1. 一種半導體裝置，包含：一基材；一通道層配置於該基材上；一阻障層配置於該通道層上，該阻障層具有一凹槽，且該凹槽下方之該阻障層具有一厚度；一汲極和一源極配置於該阻障層上；一電荷陷阱層覆蓋該凹槽的一底面；一鐵電材料配置於該電荷陷阱層上；以及一閘極配置於該鐵電材料上。
  2. 如請求項1所述之半導體裝置，更包含一第一介電層配置於該凹槽的該底面和該電荷陷阱層之間。
  3. 如請求項2所述之半導體裝置，更包含一第二介電層配置於該鐵電材料和該閘極之間。
  4. 如請求項2所述之半導體裝置，其中該第一介電層具有一能隙(bandgap)，該能隙介於7-12eV。
  5. 如請求項1所述之半導體裝置，其中該厚度介於5-15nm。
  6. 如請求項1所述之半導體裝置，其中該鐵電材料為BaTiO3、KH2PO4、HfZrO2、SrBi2Ta2O9或PbZrTiO3。
  7. 一種製造半導體裝置的方法，包含：提供一基材；形成一通道層於該基材上；形成一阻障層於該通道層上；形成一源極和一汲極於該阻障層上；形成一凹槽於該阻障層中，該凹槽具有一底面，該凹槽下方之該阻障層具有一厚度；形成一電荷陷阱層覆蓋該凹槽的該底面；形成一鐵電材料於該電荷陷阱層上；將該鐵電材料加熱至一第一溫度，該第一溫度大於該鐵電材料之一結晶溫度；將該鐵電材料降溫至一第二溫度，使該鐵電材料結晶；以及形成一閘極於該鐵電材料上。
  8. 如請求項7所述之方法，在形成一凹槽於該阻障層後，更包含形成一第一介電層覆蓋該凹槽的該底面。
  9. 如請求項7所述之方法，其中形成該鐵電材料的方法包含電漿輔助原子層沉積、有機金屬化學氣相沉積、化學氣相沉積、物理氣相沉積、濺鍍或脈衝雷射蒸鍍。
  10. 如請求項7所述之方法，其中該第一溫度介於400-600℃。
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