CN108206180B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN108206180B
CN108206180B CN201711337430.2A CN201711337430A CN108206180B CN 108206180 B CN108206180 B CN 108206180B CN 201711337430 A CN201711337430 A CN 201711337430A CN 108206180 B CN108206180 B CN 108206180B
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gate electrode
source
nanowire
region
substrate
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CN108206180A (zh
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梁正吉
裵金钟
裵东一
宋升珉
朴雨锡
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本公开涉及半导体器件。一种半导体器件包括第一区中的第一晶体管和第二区中的第二晶体管。第一晶体管包括：第一纳米线、第一栅电极、第一栅极电介质层、第一源极/漏极区和内绝缘间隔物。第一纳米线具有第一沟道区。第一栅电极围绕第一纳米线。第一栅极电介质层在第一纳米线与第一栅电极之间。第一源极/漏极区连接到第一纳米线的边缘。内绝缘间隔物在第一栅极电介质层与第一源极/漏极区之间。第二晶体管包括第二纳米线、第二栅电极、第二栅极电介质层和第二源极/漏极区。第二纳米线具有第二沟道区。第二栅电极围绕第二纳米线。第二栅极电介质层在第二纳米线与第二栅电极之间。第二源极/漏极区连接到第二纳米线的边缘。

Description

半导体器件
技术领域
本公开涉及半导体器件及制造其的方法。更具体地，本公开涉及包括纳米线晶体管的半导体器件及制造其的方法。
背景技术
电子装置已变得更小、更轻和更薄。结果，对半导体器件的高集成度的需求已经增加。由于半导体器件的缩小，短沟道效应在晶体管中产生，因而已出现了半导体器件已变得不太可靠的问题。因此，已经提出了具有多栅结构的半导体器件，诸如栅极环绕型纳米线晶体管，以减少晶体管中的短沟道效应。
发明内容
在此描述的构思提供半导体器件，其包括被构造为具有最佳性能的纳米线晶体管。
在此描述的构思还提供制造半导体器件的方法，所述半导体器件包括被构造为具有最佳性能的纳米线晶体管。
根据本公开的一方面，一种半导体器件包括第一晶体管和第二晶体管。第一晶体管在衬底的第一区中，第二晶体管在衬底的第二区中。第一晶体管包括第一纳米线、第一栅电极、第一栅极电介质层、第一源极/漏极区和内绝缘间隔物。第一纳米线具有第一沟道区。第一栅电极围绕第一纳米线。第一栅极电介质层在第一纳米线与第一栅电极之间。第一源极/漏极区连接到第一纳米线的边缘。内绝缘间隔物在第一栅极电介质层与第一源极/漏极区之间。第二晶体管包括第二纳米线、第二栅电极、第二栅极电介质层和第二源极/漏极区。第二纳米线具有第二沟道区。第二栅电极围绕第二纳米线。第二栅极电介质层在第二纳米线与第二栅电极之间。第二源极/漏极区连接到第二纳米线的边缘。
根据本公开的另一方面，一种半导体器件包括第一晶体管和第二晶体管。第一晶体管在衬底的第一区中，第二晶体管在衬底的第二区中。第一晶体管包括多个第一纳米线、第一栅电极、第一栅极电介质层、第一源极/漏极区和内绝缘间隔物。第一纳米线具有多个第一沟道区。第一栅电极围绕第一纳米线。第一栅极电介质层在第一纳米线与第一栅电极之间。第一源极/漏极区连接到第一纳米线的边缘。内绝缘间隔物在第一栅极电介质层与第一源极/漏极区之间。第二晶体管包括多个第二纳米线、第二栅电极、第二栅极电介质层和第二源极/漏极区。第二纳米线具有多个第二沟道区。第二栅电极围绕第二纳米线。第二栅极电介质层在第二纳米线与第二栅电极之间。第二源极/漏极区连接到第二纳米线的边缘。
根据本公开的另一方面，一种半导体器件包括：具有第一区和第二区的衬底；第一晶体管，其在衬底的第一区中，并且包括第一纳米线、围绕第一纳米线的第一栅电极、第一栅极电介质层、第一源极区、第一漏极区和内绝缘间隔物；以及衬底的第二区中的第二晶体管，其包括第二纳米线、围绕第二纳米线的第二栅电极、第二栅极电介质层、第二源极区和第二漏极区。第一纳米线在第一源极区与第一漏极区之间输送电子，第二纳米线在第二源极区与第二漏极区之间输送电子。第一栅极电介质层被提供在第一纳米线与第一栅电极之间以及在内绝缘间隔物与第一栅电极之间。内绝缘间隔物保持第一栅极电介质层与第一源极区和第一漏极区之间的间隔。第二栅极电介质层被提供在第二纳米线与第二栅电极之间、第二源极区与第二栅电极之间、以及第二漏极区与第二栅电极之间。
附图说明
由以下结合附图的详细描述，本公开的实施方式将被更清楚地理解，附图中：
图1是根据本公开一示例实施方式的半导体器件的俯视图；
图2是沿图1的线IIA-IIA'和IIB-IIB'截取的剖视图；
图3是沿图1的线IIIA-IIIA'和IIIB-IIIB'截取的剖视图；
图4是沿图1的线IVA-IVA'和IVB-IVB'截取的剖视图；
图5是根据本公开一示例实施方式的半导体器件的剖视图；
图6是根据本公开一示例实施方式的半导体器件的剖视图；
图7是根据本公开一示例实施方式的半导体器件的俯视图；
图8是沿图7的线VIIIA-VIIIA'和VIIIB-VIIIB'截取的剖视图；
图9是沿图7的线IXA-IXA'和IXB-IXB'截取的剖视图；
图10是沿图7的线XA-XA'和XB-XB'截取的剖视图；
图11是根据本公开一示例实施方式的半导体器件的剖视图；
图12是根据本公开一示例实施方式的半导体器件的剖视图；
图13是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图14是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图15是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图16是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图17是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图18是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图19是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；
图20是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图；以及
图21是示出根据本公开一示例实施方式的制造半导体器件的方法的剖视图。
具体实施方式
在下文中，将参照附图详细描述本公开的示例实施方式。
图1是根据本公开一示例实施方式的半导体器件100的俯视图。图2是沿图1的线IIA-IIA'和IIB-IIB'截取的剖视图。图3是沿图1的线IIIA-IIIA'和IIIB-IIIB'截取的剖视图。图4是沿图1的线IVA-IVA'和IVB-IVB'截取的剖视图。
参照图1至4，半导体器件100的衬底110包括第一区I和第二区II。有源区(未示出)可以由第一区I和第二区II中的每个中的隔离层112限定。第一晶体管TR1可以形成在第一区I的有源区中，第二晶体管TR2可以形成在第二区II的有源区中。在一示例实施方式中，第一晶体管TR1可以是n型金属氧化物半导体(NMOS)晶体管，第二晶体管TR2可以是p型金属氧化物半导体(PMOS)晶体管。
在一示例实施方式中，衬底110可以是硅衬底。在一示例实施方式中，衬底110可以构成从以下选择的至少一种器件：大规模集成(LSI)、逻辑电路、诸如CMOS成像传感器(CIS)的图像传感器、诸如闪速存储器、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、电可擦除可编程只读存储器(EEPROM)、相变RAM(PRAM)、磁性RAM(MRAM)和电阻式RAM(RRAM)的存储器件、以及微电子机械系统(MEMS)。
第一晶体管TR1可以包括第一纳米线120A、第一栅电极130A、第一栅极电介质层132A、一对第一源极/漏极区140A和内绝缘间隔物170。在图2中，第一栅电极130A被显示为在第一纳米线120A之上和之下。类似地，第一栅极电介质层132A被显示为在第一纳米线120A之上和之下，并且在第一纳米线120A之下围绕第一栅电极130A的全部四侧以及在第一纳米线120A之上围绕第一栅电极130A的四侧中的三侧。因此，如图2中所示，第一栅电极130A和第一栅极电介质层132A在Y和Z方向上的平行平面内围绕第一纳米线120A。
第一纳米线120A可以包括第一晶体管TR1的第一沟道区(未示出)。在一示例实施方式中，第一纳米线120A可以包括IV族半导体、II-IV族化合物半导体或III-V族化合物半导体。例如，第一纳米线120A可以包括Si、Ge、SiGe、InGaAs、InAs、GaSb、InSb或这些材料的组合。沟道区不相对于图1-12中的第一纳米线120A(或另外的纳米线)被详述，但是对应于关于图13-18描述的沟道层120P，并且通常用于在第一源极/漏极区140A之间输送能量(电子)。第一纳米线120A通常在X方向上比在YZ面中具有大得多的尺度(尺寸)，甚至处于1000或更大的比率。
第一栅电极130A可以包括掺杂多晶硅、金属或这些材料的组合。例如，第一栅电极130A可以包括Al、Cu、Ti、Ta、W、Mo、TaN、NiSi、CoSi、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN或这些材料的组合，但第一栅电极130A不限于此。
第一栅极电介质层132A可以包括硅氧化物膜、硅氮氧化物膜、高k膜、或这些材料的组合，高k膜具有比硅氧化物膜的介电常数更大的介电常数。例如，可以用作第一栅极电介质层132A的高k膜可以包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、锆氧化物、铝氧化物、HfO2-Al2O3合金、或这些材料的组合，但第一栅极电介质层132A和高k膜不限于此。
该对第一源极/漏极区140A可以形成在衬底110上。该对第一源极/漏极区140A可以沿着垂直于衬底110的主表面的方向(Z方向)延伸至第一纳米线120A的两边缘。在一示例实施方式中，该对第一源极/漏极区140A可以包括掺杂的SiGe膜、掺杂的Ge膜、掺杂的SiC膜或掺杂的InGaAs膜，但是该对第一源极/漏极区140A不限于此。该对第一源极/漏极区140A可以是使用外延工艺从衬底110和第一纳米线120A再生长的半导体层，并且该对第一源极/漏极区140A可以包括与衬底110和第一纳米线120A不同的材料。
该对第一源极/漏极区140A可以具有比第一纳米线120A的上水平面更高的上水平面。在一示例实施方式中，该对第一源极/极漏区140A的一部分可以是用作用于第一晶体管TR1的源极/漏极区的掺杂区。例如，当该对第一源极/漏极区140A的从该对第一源极/漏极区140A的底表面至某高度的部分用掺杂剂离子高度掺杂时，该部分可以是用作用于第一晶体管TR1的源极/漏极区的掺杂剂区。与此不同，当该对第一源极/漏极区140A的从中心区至某高度的部分用掺杂剂高度掺杂时，该部分可以是用作用于第一晶体管TR1的源极/漏极区的掺杂剂区。在另一示例实施方式中，该对第一源极/漏极区140A的整个可以是用作用于第一晶体管TR1的源极/漏极区的掺杂剂区。
第一外部绝缘间隔物150A可以在第一栅极电介质层132A的与第一栅电极130A相反的侧覆盖第一栅电极130A的一侧壁或多个侧壁。就是说，第一外部绝缘间隔物150A可以在第一纳米线120A之上围绕第一栅电极130A的在Z方向上的平行平面内的一侧或多侧。对于在此描述的第二外部绝缘间隔物150B同样如此。此外，第一纳米线120A的与该对第一源极/漏极区140A相邻的两边缘的上表面也可以被第一外部绝缘间隔物150A覆盖。
该对第一源极/漏极区140A和部分第一外部绝缘间隔物150A可以被第一绝缘层160A覆盖。第一接触162A可以穿过第一绝缘层160A连接到该对第一源极/漏极区140A。第一金属硅化物层164A可以形成在第一接触162A与该对第一源极/漏极区140A之间。
内绝缘间隔物170可以形成在衬底110与第一纳米线120A之间。内绝缘间隔物170可以被布置在第一栅电极130A与该对第一源极/漏极区140A之间。第一栅极电介质层132A可以被布置在内绝缘间隔物170与第一栅电极130A之间。在图2中，内绝缘间隔物170被显示为在第一纳米线120A的一侧(即在下面)而非另一侧(即在上面)。因此，虽然第一栅电极130A和第一栅极电介质层132A在图2中被显示为在第一纳米线120A的两侧(即在下面和在上面)，但是内绝缘间隔物170仅被显示在下面。就是说，第一栅极电介质层132A可以从第一纳米线120A的表面延伸至内绝缘间隔物170的侧壁的表面，使得在衬底110的上表面与第一纳米线120A(的在图2中的下表面)之间，第一栅极电介质层132A被插置在第一栅电极130A与内绝缘间隔物170之间。因此，该对第一源极/漏极区140A可以接触内绝缘间隔物170，并且可以不接触第一栅极电介质层132A。
内绝缘间隔物170可以包括与第一栅极电介质层132A不同的材料。在一示例实施方式中，内绝缘间隔物170可以包括比构成第一栅极电介质层132A的材料具有更小的介电常数的材料。在另一示例实施方式中，内绝缘间隔物170可以包括IV族半导体氧化物、II-IV族化合物半导体氧化物或III-V族化合物半导体氧化物、诸如硅氧化物的氧化物、或硅氮氧化物、硅氮化物、或这些材料的组合。
第一外部绝缘间隔物150A和内绝缘间隔物170可以沿着垂直于衬底110的主表面的方向(Z方向)分别布置在彼此垂直重叠的位置处并在彼此不同的高度。在一示例实施方式中，内绝缘间隔物170可以包括与构成第一外部绝缘间隔物150A的材料不同的材料。在一示例实施方式中，内绝缘间隔物170可以包括具有比构成第一外部绝缘间隔物150A的材料的介电常数更小的介电常数的材料。
第二晶体管TR2可以包括第二纳米线120B、第二栅电极130B、第二栅极电介质层132B和一对第二源极/漏极区140B。在图2中，第二栅电极130B被显示在第二纳米线120B上面和下面。类似地，第二栅极电介质层132B被显示为在第二纳米线120B上面和下面，并且在第二纳米线120B下面围绕第二栅电极130B的全部四侧以及在第二纳米线120B上面围绕第二栅电极130B的四侧中的三侧。因此，如图2中所示，第二栅电极130B和第二栅极电介质层132B在Y和Z方向上的平行平面中围绕第二纳米线120B。
第二纳米线120B可以包括第二晶体管TR2的第二沟道区(未示出)。沟道区不相对于图1-12中的第二纳米线120B(或另外的纳米线)被详细说明，但是对应于关于图13-18描述的沟道层120P，并且通常用于在第二源极/漏极区140B之间输送能量(电子)。第二纳米线120B通常在X方向上比在YZ平面中具有大得多的尺度(尺寸)，甚至处于1000或更大的比率。
第二栅电极130B和第二栅极电介质层132B可以具有关于第一栅电极130A和第一栅极电介质层132A描述的相似的特征。例如，第二栅电极130B可以包括掺杂多晶硅、金属或这些材料的组合，第二栅极电介质层132B可以包括硅氧化物膜、硅氮氧化物膜、具有比硅氧化物膜的介电常数更大的介电常数的高k膜、或这些材料的组合。
在一示例实施方式中，第二栅电极130B和第一栅电极130A可以包括相同的材料，第二栅极电介质层132B和第一栅极电介质层132A可以包括相同的材料。与此不同，第二栅电极130B和第一栅电极130A可以包括彼此不同的材料，第二栅极电介质层132B和第一栅极电介质层132A可以包括彼此不同的材料。
该对第二源极/漏极区140B可以形成在衬底110上。该对第二源极/漏极区140B可以沿着垂直于衬底110的主表面的方向(Z方向)延伸至第二纳米线120B的两边缘。该对第二源极/漏极区140B可以是使用外延工艺从衬底110和第二纳米线120B再生长的半导体层，并且该对第二源极/漏极区140B可以包括与衬底110和第二纳米线120B不同的材料。在一示例实施方式中，该对第二源极/漏极区140B可以包括掺杂的SiGe膜、掺杂的Ge膜、掺杂的SiC膜或掺杂的InGaAs膜，但是该对第二源极/漏极区140B不限于此。
在一示例实施方式中，该对第二源极/漏极区140B可以包括与该对第一源极/漏极区140A不同的材料。例如，该对第一源极/漏极区140A可以包括SiC，该对第二源极/漏极区140B可以包括SiGe或Ge。
第二外部绝缘间隔物150B、第二绝缘层160B、第二接触162B和第二金属硅化物层164B可以分别具有与第一外部绝缘间隔物150A、第一绝缘层160A、第一接触162A和第一金属硅化物层164A相似的特性。在一示例实施方式中，第二外部绝缘间隔物150B、第二绝缘层160B、第二接触162B和第二金属硅化物层164B可以分别在用于形成第一外部绝缘间隔物150A、第一绝缘层160A、第一接触162A和第一金属硅化物层164A的相同的工艺中形成。在另一示例实施方式中，第二外部绝缘间隔物150B可以在与用于形成第一外部绝缘间隔物150A的工艺不同的工艺中形成。此外，第二绝缘层160B可以在与用于形成第一绝缘层160A的工艺不同的工艺中形成。
与第一晶体管TR1不同，第二晶体管TR2可以不包括内绝缘间隔物170，内绝缘间隔物170可以不布置在衬底110与第二纳米线120B之间。如图2中所绘，第二栅极电介质层132B可以被布置在第二栅电极130B与该对第二源极/漏极区140B之间。就是说，第二栅极电介质层132B可以从衬底110与第二纳米线120B之间延伸至第二栅电极130B与该对第二源极/漏极区140B之间。该对第二源极/漏极区140B可以接触第二栅极电介质层132B。
第二外部绝缘间隔物150B和第二栅电极130B的一部分可以沿着垂直于衬底110的主表面的方向(Z方向)被分别布置在彼此垂直重叠的位置处并且在彼此不同的高度。
如图2中所绘，内绝缘间隔物170可以形成在第一栅电极130A与该对第一源极/漏极区140A之间，而内绝缘间隔物170可以不形成在第二栅电极130B与该对第二源极/漏极区140B之间。因此，第一晶体管TR1和第二晶体管TR2被不同地构造，而第二栅极电介质层132B在第二栅电极130B的每一侧接触第二源极/漏极区140B，第一栅极电介质层132A在第一栅极电极130A的每一侧通过内绝缘间隔物170与第一源极/漏极区140A间隔开。
因为内绝缘间隔物170形成在第一栅电极130A与该对第一源极/漏极区140A之间，所以可以增大第一栅电极130A与该对第一源极/漏极区140A之间的分隔距离。因此，在第一晶体管TR1中，可以减少第一栅电极130A与该对第一源极/漏极区140A之间的寄生电容的产生，并且第一晶体管TR1可以显示出快速的操作速度。具体地，当第一晶体管TR1是NMOS晶体管时，该NMOS晶体管的性能可以由于寄生电容的减小而被提高。
因为内绝缘间隔物170不形成在第二栅电极130B与该对第二源极/漏极区140B之间，所以该对第二源极/漏极区140B可以具有高的晶体质量。如果内绝缘间隔物170在用于生长该对第二源极/漏极区140B的工艺中被布置在一对第二源极/漏极凹陷区140RB(参照图15)的暴露表面上，则多个堆垛层错或位错可以在该对第二源极/漏极区140B中产生。该对第二源极/漏极区140B的晶体质量可以由于堆垛层错或位错而不高，并且该对第二源极/漏极区140B可以难以用作向第二纳米线120B施加压缩应变的应力源(stressor)。
然而，因为内绝缘间隔物170不形成在第二栅电极130B与该对第二源极/漏极区140B之间，所以该对第二源极/漏极区140B中的堆垛层错或位错的产生可以被抑制，因而该对第二源极/漏极区140B可以具有高的晶体质量。因此，该对第二源极/漏极区140B可以用作向第二纳米线120B施加压缩应变的应力源，因而第二晶体管TR2可以显示出快速的操作速度。具体地，如果第二晶体管TR2是PMOS晶体管，则该PMOS晶体管的性能可以通过该对第二源极/漏极区140B的高晶体质量而被提高。
在根据上述一示例实施方式的半导体器件100中，由于通过内绝缘间隔物170产生的寄生电容的减小，例如NMOS晶体管的第一晶体管TR1可以提供高性能，并且由于该对第二源极/漏极区140B的高晶体质量，例如PMOS晶体管的第二晶体管TR2可以提供高性能。因此，半导体器件100可以具有最佳性能。
图5是根据本公开一示例实施方式的半导体器件100A的剖视图。图5显示了与沿图1的线IIA-IIA'和IIB-IIB'截取的剖面对应的剖面。在图5中，相同的附图标记用于指示与图1至4的元件相同的元件。
参照图5，半导体器件100A还可以包括在衬底110与第一栅电极130A之间的第一沟道分隔区180A以及在衬底110与第二栅电极130B之间的第二沟道分隔区180B。第一沟道分隔区180A可以包括与该对第一源极/漏极区140A中包括的导电类型掺杂剂相反的导电类型掺杂剂，第二沟道分隔区180B可以包括与该对第二源极/漏极区140B中包括的导电类型掺杂剂相反的导电类型掺杂剂。第一沟道分隔区180A和第二沟道分隔区180B可以防止沟道在衬底110的面对第一栅电极130A和第二栅电极130B的底表面的上表面上的形成。例如，沟道路径可以通过第一纳米线120A从该对第一源极/漏极区140A中的一个的下部形成到该对第一源极/漏极区140A中的另一个的下部，因此可以防止短沟道效应。
图6是根据本公开一示例实施方式的半导体器件100B的剖视图。图6显示了与沿图1的线IIA-IIA'和线IIB-IIB'截取的剖面对应的剖面。在图6中，相同的附图标记用于指示与图1至5的元件相同的元件。
参照图6，半导体器件100B还可以包括在衬底110与第一栅电极130A之间的第一缓冲层190A以及在衬底110与第二栅电极130B之间的第二缓冲层190B。
第一缓冲层190A和第二缓冲层190B可以包括具有比用于形成衬底110的材料的晶格常数更大的晶格常数的材料。在一示例实施方式中，衬底110可以包括Si，第一缓冲层190A和第二缓冲层190B可以包括GaAs、InP、InAlAs或这些材料的组合。在一示例实施方式中，第一缓冲层190A和第二缓冲层190B可以是单层或多层。例如，第一缓冲层190A和第二缓冲层190B可以具有一种多层结构，其中包括GaAs的第一层和包括InP或InAlAs的第二层被顺序堆叠在衬底110上。
在一示例实施方式中，该对第一源极/漏极区140A可以包括不同于第一纳米线120A的材料，该对第二源极/漏极区140B可以包括不同于第二纳米线120B的材料。因此，第一纳米线120A和第二纳米线120B可以包括应变沟道。结果，可以增大包括第一纳米线120A和第二纳米线120B的第一晶体管TR1和第二晶体管TR2的载流子迁移率。
例如，在第二晶体管TR2中，第二纳米线120B可以包括Ge，该对第二源极/漏极区140B可以包括掺杂的SiGe。在第一晶体管TR1中，第一纳米线120A可以包括InGaAs，该对第一源极/漏极区140A可以包括掺杂的InGaAs。第一纳米线120A中包括的InGaAs的In和Ga的成分比可以不同于该对第一源极/漏极区140A中包括的InGaAs的In和Ga的成分比。然而，第一纳米线120A和第二纳米线120B以及该对第一源极/漏极区140A和该对第二源极/漏极区140B的材料和成分比不限于此。
图7是根据本公开一示例实施方式的半导体器件200的俯视图。图8是沿图7的线VIIIA-VIIIA'和VIIIB-VIIIB'截取的剖视图。图9是沿图7的线IXA-IXA'和IXB-IXB'截取的剖视图。图10是沿图7的线XA-XA'和XB-XB'截取的剖视图。在图7至10中，相同的附图标记用于指示与图1至6的元件相同的元件。
参照图7至10，半导体器件200可以包括形成在衬底110的第一区I中的第一晶体管TR1以及形成在衬底110的第二区II中的第二晶体管TR2。
第一晶体管TR1可以包括多个第一纳米线120A1、120A2和120A3、第一栅电极230A、第一栅极电介质层232A、一对第一源极/漏极区140A、以及内绝缘间隔物170。第一栅电极230A在Y和Z方向上的平行平面中围绕第一纳米线120A1、120A2和120A3。第一栅极电介质层232A布置在第一栅电极230A与第一纳米线120A1、120A2和120A3之间。内绝缘间隔物170布置在该对第一源极/漏极区140A与第一栅电极230A之间。
第二晶体管TR2可以包括多个第二纳米线120B1、120B2和120B3、第二栅电极230B、第二栅极电介质层232B、以及一对第二源极/漏极区140B。第二栅电极230B在Y和Z方向上的平行平面中围绕第二纳米线120B1、120B2和120B3。第二栅极电介质层232B布置在第二栅电极230B与第二纳米线120B1、120B2和120B3之间。
在第一晶体管TR1中，第一纳米线120A1、120A2和120A3分别位于自衬底110的上表面起的彼此不同的高度上，并且从衬底110的上表面到第一纳米线120A1、120A2和120A3中的每个的距离彼此不同。第一纳米线120A1、120A2和120A3可以分别包括多个第一沟道区(未示出)。第一栅电极230A可以形成为在Y和Z方向上的平行平面中围绕第一纳米线120A1、120A2和120A3中的每个的至少一部分。第一栅电极230A可以包括分别形成在衬底110和第一纳米线120A1、120A2和120A3之间的空间中的第一子栅电极230A1、230A2和230A3。第一栅极电介质层232A可以布置在第一栅电极230A与第一纳米线120A1、120A2和120A3之间。
内绝缘间隔物170可以分别形成在第一子栅电极230A1、230A2和230A3与该对第一源极/漏极区140A之间，在衬底110和第一纳米线120A1、120A2和120A3之间。该对第一源极/漏极区140A可以不接触第一栅极电介质层232A，并且内绝缘间隔物170可以包括与第一栅极电介质层232A不同的材料。
在第二晶体管TR2中，第二纳米线120B1、120B2和120B3分别位于自衬底110的上表面起的彼此不同的高度上，并且从衬底110的上表面到第二纳米线120B1、120B2和120B3中的每个的距离彼此不同。第二纳米线120B1、120B2和120B3可以分别包括多个第二沟道区(未示出)。第二栅电极230B可以形成为在Y和Z方向上的平行平面中围绕第二纳米线120B1、120B2和120B3中的每个的至少一部分。第二栅电极230B可以包括分别形成在衬底110和第二纳米线120B1、120B2和120B3之间的空间中的第二子栅电极230B1、230B2和230B3。第二栅极电介质层232B可以布置在第二栅电极230B与第二纳米线120B1、120B2和120B3之间。第二栅极电介质层232B可以延伸至该对第二源极/漏极区140B与第二子栅电极230B1、230B2和230B3之间的空间。
如图8中所绘，内绝缘间隔物170仅形成在第一子栅电极230A1、230A2和230A3与该对第一源极/漏极区140A之间，并且可以不形成在第二子栅电极230B1、230B2和230B3与该对第二源极/漏极区140B之间。因此，该对第一源极/漏极区140A与第一子栅电极230A1、230A2和230A3之间的分隔距离可以大于该对第二源极/漏极区140B与第二子栅电极230B1、230B2和230B3之间的分隔距离。在一示例实施方式中，当第一晶体管TR1是NMOS晶体管时，因为该对第一源极/漏极区140A与第一子栅电极230A1、230A2和230A3之间的分隔距离相对较大，所以可以减少该对第一源极/漏极区140A和第一子栅电极230A1、230A2和230A3之间的寄生电容的产生。因此，NMOS晶体管可以具有快速的操作速度。
然而，内绝缘间隔物170不形成在第二子栅电极230B1、230B2和230B3与该对第二源极/漏极区140B之间。因此，该对第二源极/漏极区140B可以具有高的晶体质量。如果多个内绝缘间隔物170在用于生长该对第二源极/漏极区140B的工艺中被布置在成对第二源极/漏极凹陷区140RB(参照图15)的暴露表面上，则多个堆垛层错或位错可以由于包括绝缘材料的内绝缘间隔物170而在该对第二源极/漏极区140B中产生。该对第二源极/漏极区140B的晶体质量可以由于堆垛层错或位错而不高，并且对于该对第二源极/漏极区140B而言可以难以用作向第二纳米线120B施加应力的应力源。
然而，内绝缘间隔物170不形成在第二栅电极130B与该对第二源极/漏极区140B之间。该对第二源极/漏极区140B可以使用第一至第三牺牲层240P1、240P2、240P3(参照图16)和第二纳米线120B1、120B2和120B3作为籽晶层而被形成。该对第二源极/漏极区140B中的堆垛层错或位错的产生被抑制，因而该对第二源极/漏极区140B可以具有高的晶体质量。因此，该对第二源极/漏极区140B可以用作向第二纳米线120B1、120B2和120B3施加应力的应力源，因而第二晶体管TR2可以具有高的操作速度。具体地，当第二晶体管TR2是PMOS晶体管时，PMOS晶体管的性能可以通过该对第二源极/漏极区140B的高晶体质量而被提高。
在根据一示例实施方式的半导体器件200中，由于借助于内绝缘间隔物170的寄生电容的减小，第一晶体管TR1即NMOS晶体管可以提供高性能，并且通过该对第二源极/漏极区140B的高晶体质量，第二晶体管TR2即PMOS晶体管可以提供高性能。因此，半导体器件200可以提供高性能。
图11是根据本公开一示例实施方式的半导体器件200A的剖视图。图11显示与沿图7的线VIIIA-VIIIA'和线VIIIB-VIIIB'截取的剖面对应的剖面。在图11中，相同的附图标记用于指示与图1至10的元件相同的元件。
参照图11，内绝缘间隔物170中的每个可以具有在朝向第一子栅电极230A1、230A2和230A3的方向上凸出的侧壁。第一栅极电介质层232A可以形成为在内绝缘间隔物170中的每个的侧壁上具有共形的厚度。第一子栅电极230A1、230A2和230A3可以具有朝其内侧凹入的侧壁，第一子栅电极230A1、230A2和230A3被布置在内绝缘间隔物170的侧壁上，且第一栅极电介质层232A被插置在其间。如图11中所绘，第一子栅电极230A1、230A2和230A3可以分别包括与内绝缘间隔物170的侧壁的形状共形的在其上边缘和下边缘的尾部230AT。
为了说明的方便，内绝缘间隔物170的侧壁的轮廓被减小或夸大，因而内绝缘间隔物170的侧壁的斜度必要时可以改变。
在用于形成内绝缘间隔物170的一示例工艺中，在交替且顺序地形成牺牲层240P(参照图13)和沟道层120P(参照图13)之后，第一源极/漏极凹陷区140RA(参照图17)通过蚀刻部分牺牲层240P和沟道层120P形成。结果，牺牲层240P的侧壁可以被暴露在第一源极/漏极凹陷区140RA的侧壁上。此时，牺牲层240P的暴露的侧壁的部分可以使用其中牺牲层240P相对于沟道层120P具有蚀刻选择性(例如，牺牲层240P的蚀刻速率相对地高于沟道层120P的蚀刻速率)的蚀刻条件而被选择性地去除。牺牲层240P的根据该蚀刻条件被去除的部分在中央区域中可以比在上边缘或下边缘中更大。因此，如图11中所绘，通过在形成绝缘层(未示出)于牺牲层240P被去除的位置上之后执行回蚀刻工艺，每个具有凸出的侧壁的内绝缘间隔物170可以被形成。然而，内绝缘间隔物170和上述的另外的特征不限于以上描述。内绝缘间隔物170可以通过对牺牲层240P的暴露的侧壁执行热氧化工艺来形成。
图12是根据本公开一示例实施方式的半导体器件200B的剖视图。图12显示了与沿图7的线VIIIA-VIIIA'和线VIIIB-VIIIB'截取的剖面对应的剖面。在图12中，相同的附图标记用于指示与图1至11的元件相同的元件。
参照图12，该对第二源极/漏极区140B可以包括面向第二子栅电极230B1、230B2和230B3的多个突出部分140BP，并且第二栅极电介质层232B可以布置在突出部分140BP与第二子栅电极230B1、230B2和230B3之间。
在用于形成该对第二源极/漏极区140B的一示例工艺中，在交替且顺序地形成牺牲层240P(参照图13)和沟道层120P(参照图13)之后，成对的第二源极/漏极凹陷区140RB(参照图15)通过蚀刻牺牲层240P和沟道层120P的部分被形成。结果，牺牲层240P的侧壁可以被暴露在该对第二源极/漏极凹陷区140RB的侧壁上。此时，牺牲层240P的暴露的侧壁的部分可以使用其中牺牲层240P相对于沟道层120P具有蚀刻选择性(例如，牺牲层240P的蚀刻速率相对地高于沟道层120P的蚀刻速率)的蚀刻条件被选择性地去除。牺牲层240P的根据该蚀刻条件被去除的部分可以在中央区域中比在上边缘或下边缘中更大。此后，填充该对第二源极/漏极凹陷区140RB的内侧的该对第二源极/漏极区140B可以使用外延工艺被形成。
在示例实施方式中，在用于形成该对第二源极/漏极凹陷区140RB的蚀刻工艺中，对牺牲层240P的侧壁的损伤可能发生，或者牺牲层240P的晶体质量可能被部分地劣化。然而，牺牲层240P的侧壁的其中晶体质量劣化的部分可以通过选择性去除工艺被去除。此后，具有高晶体质量的该对第二源极/漏极区140B可以使用暴露在该对第二源极/漏极凹陷区140RB的侧壁上的牺牲层240P和沟道层120P作为籽晶层来被形成。
在另一示例实施方式中，该对第二源极/漏极凹陷区140RB的侧壁面积可以通过选择性去除工艺被增大，因此，牺牲层240P和沟道层120P的相对大的面积可以被暴露在该对第二源极/漏极凹陷区140RB的内侧壁上。因此，具有高晶体质量的该对第二源极/漏极区140B可以使用牺牲层240P和沟道层120P的暴露区域作为籽晶层来被形成。然而，该对第二源极/漏极区140B不限于此。
应理解，为了说明的方便，图12中所绘的该对第二源极/漏极区140B和突出部分140BP的侧壁轮廓被简化或夸大了。
在根据上述示例实施方式的半导体器件200中，第一晶体管TR1例如NMOS晶体管可以由于内绝缘间隔物170中的寄生电容的减小而提供高性能，并且第二晶体管TR2例如PMOS晶体管可以通过该对第二源极/漏极区140B的高晶体质量而提供高性能。因此，半导体器件200可以提供高性能。
图13至21是示出根据本公开一示例实施方式的制造半导体器件200的方法的剖视图。在图13至21中，根据制造工艺的顺序描绘了与沿图7的线VIIIA-VIIIA'和线VIIIB-VIIIB'截取的剖面对应的剖面。
参照图13，第一沟道分隔区180A和第二沟道分隔区180B可以通过从衬底110的主表面将掺杂剂离子以高浓度注入到衬底110中来形成。衬底110可以包括第一区I和第二区II。第一区I可以是NMOS晶体管区，第二区II可以是PMOS晶体管区。
然后，牺牲层240P和沟道层120P被交替且顺序地形成在衬底110上。牺牲层240P和沟道层120P可以使用外延工艺形成。牺牲层240P可以包括第一至第三牺牲层240P1、240P2和240P3，沟道层120P可以包括第一至第三沟道层120P1、120P2和120P3。
在示例实施方式中，牺牲层240P和沟道层120P可以包括相对于彼此具有蚀刻选择性的材料。例如，牺牲层240P和沟道层120P可以分别包括IV族半导体、II-IV族化合物半导体或III-V族化合物半导体的单层，并且牺牲层240P和沟道层120P可以包括彼此不同的材料。在一示例实施方式中，牺牲层240P可以包括SiGe，沟道层120P可以包括单晶硅。
在示例实施方式中，外延工艺可以是气相外延(VPE)工艺、诸如超高真空化学气相沉积(UHV-CVD)工艺的化学气相沉积(CVD)工艺、分子束外延工艺、或这些工艺的组合。在外延工艺中，液体或蒸汽前体可以被用作形成牺牲层240P和沟道层120P所需的前体。
参照图14，当在沟道层120P上形成在第一方向(X方向)上以预定长度延伸的掩模图案(未示出)之后，可以通过使用掩模图案作为蚀刻掩模蚀刻第一至第三沟道层120P1、120P2和120P3、第一至第三牺牲层240P1、240P2和240P3、第一沟道分隔区180A和第二沟道分隔区180B、以及衬底110来形成第一沟槽T1。
然后，沟槽T1的内侧用绝缘材料填充，隔离层112可以通过平坦化绝缘材料的上表面来形成。有源区AC可以被隔离层112限定在衬底110上，并且有源区AC可以包括预定类型的掺杂剂离子被注入到其中的阱。
然后，在第一区I和第二区II中，第一虚设栅极结构260A和第二虚设栅极结构260B可以形成在第一至第三牺牲层240P1、240P2和240P3以及第一至第三沟道层120P1、120P2和120P3的堆叠结构上。第一虚设栅极结构260A和第二虚设栅极结构260B可以分别包括第一蚀刻停止层262A和第二蚀刻停止层262B、第一虚设栅电极264A和第二虚设栅电极264B、第一封盖层266A和第二封盖层266B、以及第一外部绝缘间隔物150A和第二外部绝缘间隔物150B。
例如，第一虚设栅极结构260A和第二虚设栅极结构260B可以包括多晶硅，第一封盖层266A和第二封盖层266B可以包括硅氮化物膜。第一蚀刻停止层262A和第二蚀刻停止层262B可以包括相对于第一虚设栅极结构260A和第二虚设栅极结构260B具有蚀刻选择性的材料。例如，第一蚀刻停止层262A和第二蚀刻停止层262B可以包括从热氧化物膜、硅氧化物膜和硅氮化物膜中选择的至少一种膜。第一外部绝缘间隔物150A和第二外部绝缘间隔物150B可以包括硅氧化物、硅氮氧化物或硅氮化物，但不限于此。
参照图15，覆盖第一虚设栅极结构260A和第一至第三沟道层120P1、120P2和120P3的第一保护层272可以在第一区I中形成。在第二区II中，该对第二源极/漏极凹陷区140RB可以通过使用第二虚设栅极结构260B作为蚀刻掩模蚀刻部分第一至第三沟道层120P1、120P2和120P3、第一至第三牺牲层240P1、240P2和240P3、第二沟道分隔区180B、以及衬底110来形成。
在衬底110中，该对第二源极/漏极凹陷区140RB可以具有比第二沟道分隔区180B的深度更大的深度。因为该对第二源极/漏极凹陷区140RB被形成，所以部分第一至第三沟道层120P1、120P2和120P3被去除，并且第二纳米线120B1、120B2和120B3可以由第一至第三沟道层120P1、120P2和120P3的剩余部分被形成。
参照图16，当在该对第二源极/漏极凹陷区140RB中自衬底110、第二纳米线120B1、120B2和120B3以及第一至第三牺牲层240P1、240P2和240P3生长单晶膜之后，填充该对第二源极/漏极凹陷区140RB的该对第二源极/漏极区140B可以被形成。
在用于生长该对第二源极/漏极区140B的外延工艺中，暴露在该对第二源极/漏极凹陷区140RB的侧壁上的衬底110、第二纳米线120B1、120B2和120B3、以及第一至第三牺牲层240P1、240P2和240P3全部可以分别为单晶半导体层。因此，该对第二源极/漏极区140B的生长过程中由于晶格失配的位错或堆垛层错的产生可以被防止，因而该对第二源极/漏极区140B可以提供高的晶体质量。
通常，用于外延工艺的籽晶层或模板可以包括具有不连续界面的单晶半导体层或通过绝缘层被分开布置的多个单晶半导体表面。当这种情况发生时，有在生长于籽晶层或模板上的单晶半导体层中产生位错或堆垛层错的高可能性。包括位错或堆垛层错的单晶半导体层几乎不可以用作向沟道区施加压缩应变或拉伸应力的应力源。
然而，按照根据本公开的制造半导体器件200的方法，暴露在该对第二源极/漏极凹陷区140RB的侧壁上的衬底110、第二纳米线120B1、120B2和120B3、以及第一至第三牺牲层240P1、240P2和240P3全部可以是单晶半导体层。具体地，例如，当与其中绝缘层(或内绝缘间隔物)被暴露在该对第二源极/漏极区140RB的侧壁上的情况相比时，可以防止该对第二源极/漏极凹陷区140RB中生长的该对第二源极/漏极区140B中的位错或堆垛层错的产生，因而该对第二源极/漏极区140B可以提供高的晶体质量。
在示例实施方式中，第二源极/漏极区140B可以包括多个层。例如，第二源极/漏极区140B可以包括：其中含SiGe的第一层和第二层可以被形成但第一层和第二层可以分别具有不同的Si和Ge含量的多层结构；或者其中含SiGe的第一至第三层可以被形成但第一至第三层可以分别具有不同的Si和Ge含量的多层结构。
然后，第一保护层272可以被去除。
参照图17，第二保护层274可以在第二区II中形成。该对第一源极/漏极凹陷区140RA可以通过使用第一区I中的第一虚设栅极结构260A作为蚀刻掩模蚀刻第一至第三沟道层120P1、120P2和120P3、第一至第三牺牲层240P1、240P2和240P3、第一沟道分隔区180A、以及衬底110的在第一虚设栅极结构260A的两侧的部分来形成。
参照图18，牺牲凹陷区240R可以通过横向地蚀刻第一至第三牺牲层240P1、240P2和240P3的由该对第一源极/漏极凹陷区140RA暴露的部分来形成。
在示例实施方式中，可以存在其中第一至第三牺牲层240P1、240P2和240P3相对于第一至第三沟道层120P1、120P2和120P3具有高蚀刻速率的蚀刻条件。牺牲凹陷区240R可以通过基于该蚀刻条件去除暴露在该对第一源极/漏极凹陷区140RA的侧壁上的第一至第三牺牲层240P1、240P2和240P3的预定厚度来形成。如图18中所绘，牺牲凹陷区240R可以具有垂直的侧壁轮廓，与此不同，如图11中所绘，可以具有凹的侧壁轮廓。
参照图19，在通过在该对第一源极/漏极凹陷区140RA的侧壁上形成共形的绝缘层(未示出)来填充牺牲凹陷区240R的内侧之后，利用回蚀刻工艺，内绝缘间隔物170可以仅保留在牺牲凹陷区240R的内侧中。
参照图20，填充该对第一源极/漏极凹陷区140RA的该对第一源极/漏极区140A可以通过自衬底110和第一纳米线120A1、120A2和120A3再生长单晶层来形成在该对第一源极/漏极凹陷区140RA中。
参照图21，第二保护层274(参照图20)可以被去除。
然后，当在隔离层112、第一虚设栅极结构260A和第二虚设栅极结构260B(参照图20)、以及该对第一源极/漏极区140A和第二源极/漏极区140B上形成绝缘层160A和160B之后，绝缘层160A和160B的上部使用回蚀刻工艺的平坦化工艺被去除，结果，第一虚设栅极结构260A和第二虚设栅极结构260B可以被暴露于外部。然后，第一虚设栅极结构260A和第二虚设栅极结构260B被去除，以在该对外部绝缘间隔物150A和150B之间具有第一栅极空隙GSA和第二栅极空隙GSB。第一纳米线120A1、120A2和120A3可以通过第一栅极空隙GSA被暴露，第二纳米线120B1、120B2和120B3可以通过第二栅极空隙GSB被暴露。
然后，第一栅极空隙GSA和第二栅极空隙GSB可以通过选择性地去除第一至第三牺牲层240P1、240P2和240P3的经由第一栅极空隙GSA和第二栅极空隙GSB暴露的部分而延伸至衬底110的上表面。
例如，第一子栅极空隙GSA1、GSA2和GSA3可以在第一区I中在第一至第三牺牲层240P1、240P2和240P3被去除的位置上形成，第二子栅极空隙GSB1、GSB2和GSB3可以在第二区II中在第一至第三牺牲层240P1、240P2和240P3被去除的位置上形成。
参照图21和8，第一栅极电介质层232A和第二栅极电介质层232B分别形成在第一栅极空隙GSA和第二栅极空隙GSB中暴露的表面上。就是说，第一栅极电介质层232A和第二栅极电介质层232B分别在第一纳米线120A1、120A2和120A3、第二纳米线120B1、120B2和120B3、以及第一沟道分隔区180A和第二沟道分隔区180B中的每个的暴露表面、内绝缘间隔物170的暴露表面、以及该对第一外部绝缘间隔物150A和第二外部绝缘间隔物150B的暴露表面上形成。然后，分别填充第一栅极空隙GSA和第二栅极空隙GSB的第一栅电极230A和第二栅电极230B可以形成在第一栅极电介质层232A和第二栅极电介质层232B上。
在按照上述方法制造的半导体器件200中，例如NMOS晶体管的第一晶体管TR1可以提供高性能，因为内绝缘间隔物170中产生的寄生电容被减小；并且第二晶体管TR2可以通过该对第二源极/漏极区140B的高晶体质量提供高性能。
已经参照附图描述了本公开的示例实施方式。在本说明书中，示例实施方式通过使用特定术语被描述。然而，应理解，所述术语用来说明在此描述的构思的技术范围，而不是要限制权利要求中描述的特征、特性和构思的范围。因此，本领域普通技术人员将理解，可以对其进行形式和细节上的各种各样的改变而不背离本公开的精神和范围。因此，本公开的范围不由以上的详细描述限定，而由所附权利要求限定。
本专利申请要求2016年12月16日在韩国知识产权局(KIPO)提交的韩国专利申请第10-2016-0172883号的优先权，其公开通过引用全文合并于此。

Claims (18)

1.一种半导体器件，包括：
在衬底的第一区中的第一晶体管和在所述衬底的第二区中的第二晶体管，
其中所述第一晶体管是n型金属氧化物半导体(NMOS)晶体管，包括：具有第一沟道区的第一纳米线；围绕所述第一纳米线的第一栅电极；在所述第一纳米线与所述第一栅电极之间的第一栅极电介质层；连接到所述第一纳米线的边缘的第一源极/漏极区；以及在所述第一栅极电介质层与所述第一源极/漏极区之间的内绝缘间隔物，以及
所述第二晶体管是p型金属氧化物半导体(PMOS)晶体管，包括：具有第二沟道区的第二纳米线；围绕所述第二纳米线的第二栅电极；在所述第二纳米线与所述第二栅电极之间的第二栅极电介质层；以及连接到所述第二纳米线的边缘的第二源极/漏极区，
其中所述第二栅极电介质层进一步在所述第二栅电极与所述第二源极/漏极区之间延伸，并且与所述第二源极/漏极区接触，以及
其中所述内绝缘间隔物设置在所述第一栅电极与所述第一源极/漏极区之间，且所述第一栅电极与所述第一源极/漏极区之间的距离大于所述第二栅电极与所述第二源极/漏极区之间的距离。
2.根据权利要求1所述的半导体器件，其中所述第一栅极电介质层进一步在所述第一栅电极与所述内绝缘间隔物之间延伸。
3.根据权利要求1所述的半导体器件，其中所述第一源极/漏极区与所述第一栅极电介质层不接触。
4.根据权利要求1所述的半导体器件，其中所述内绝缘间隔物包括具有第一介电常数的第一材料，所述第一栅极电介质层和第二栅极电介质层包括具有比所述第一介电常数大的第二介电常数的第二材料。
5.根据权利要求1所述的半导体器件，还包括：
围绕所述第一纳米线之上的所述第一栅电极的侧面的第一外部绝缘间隔物，
其中，在垂直于所述衬底的方向上，所述第一外部绝缘间隔物和所述内绝缘间隔物重叠并且位于所述衬底之上在彼此不同的高度。
6.根据权利要求5所述的半导体器件，
其中所述第一外部绝缘间隔物和所述内绝缘间隔物包括彼此不同的材料。
7.根据权利要求1所述的半导体器件，还包括：
围绕所述第二纳米线之上的所述第二栅电极的侧面的第二外部绝缘间隔物，
其中，在垂直于所述衬底的方向上，所述第二外部绝缘间隔物和所述第二纳米线之下的所述第二栅电极重叠并且位于所述衬底之上在彼此不同的高度。
8.根据权利要求1所述的半导体器件，
其中所述第二源极/漏极区包括至少一个突出部分，以及所述至少一个突出部分接触所述第二栅极电介质层并且位于所述第二纳米线上方或下方。
9.根据权利要求1所述的半导体器件，还包括沿着所述衬底的主表面延伸方向在所述衬底与所述第一栅电极之间以及在所述衬底与所述第二栅电极之间延伸的缓冲层，其中所述缓冲层包括具有比所述衬底的晶格常数更大的晶格常数的材料。
10.根据权利要求1所述的半导体器件，还包括：
在所述衬底与所述第一栅电极之间并沿着所述衬底的主表面延伸方向延伸的第一沟道分隔区，其中所述第一沟道分隔区包括与所述第一源极/漏极区的导电类型掺杂剂不同的导电类型掺杂剂；以及
在所述衬底与所述第二栅电极之间并沿着所述衬底的所述主表面延伸方向延伸的第二沟道分隔区，其中所述第二沟道分隔区包括与所述第二源极/漏极区的导电类型掺杂剂不同的导电类型掺杂剂。
11.一种半导体器件，包括：
在衬底的第一区中的第一晶体管和在所述衬底的第二区中的第二晶体管，
其中所述第一晶体管是n型金属氧化物半导体(NMOS)晶体管，包括：具有多个第一沟道区的多个第一纳米线；围绕所述多个第一纳米线的第一栅电极；在所述多个第一纳米线与所述第一栅电极之间的第一栅极电介质层；连接到所述多个第一纳米线的边缘的第一源极/漏极区；以及在所述第一栅极电介质层与所述第一源极/漏极区之间的内绝缘间隔物，以及
所述第二晶体管是p型金属氧化物半导体(PMOS)晶体管，包括：具有多个第二沟道区的多个第二纳米线；围绕所述多个第二纳米线的第二栅电极；在所述多个第二纳米线与所述第二栅电极之间的第二栅极电介质层；以及连接到所述多个第二纳米线的边缘的第二源极/漏极区，
其中所述第二栅极电介质层进一步在所述第二栅电极与所述第二源极/漏极区之间延伸，并且与所述第二源极/漏极区接触，以及
其中所述内绝缘间隔物设置在所述第一栅电极与所述第一源极/漏极区之间，且所述第一栅电极与所述第一源极/漏极区之间的距离大于所述第二栅电极与所述第二源极/漏极区之间的距离。
12.根据权利要求11所述的半导体器件，其中所述第一栅极电介质层进一步在所述第一栅电极与所述内绝缘间隔物之间延伸。
13.根据权利要求11所述的半导体器件，其中所述第一源极/漏极区与所述第一栅极电介质层不接触。
14.根据权利要求11所述的半导体器件，还包括：
围绕所述多个第一纳米线之上的所述第一栅电极的侧面的第一外部绝缘间隔物；以及
围绕所述多个第二纳米线之上的所述第二栅电极的侧面的第二外部绝缘间隔物，
其中，在垂直于所述衬底的方向上，所述第一外部绝缘间隔物和所述内绝缘间隔物重叠并且位于所述衬底之上彼此不同的高度，以及
在垂直于所述衬底的方向上，所述第二外部绝缘间隔物和所述第二纳米线之下的所述第二栅电极重叠并且位于所述衬底之上彼此不同的高度。
15.一种半导体器件，包括：
具有第一区和第二区的衬底；
第一晶体管，其在所述衬底的所述第一区中，是n型金属氧化物半导体(NMOS)晶体管，并且包括第一纳米线、围绕所述第一纳米线的第一栅电极、第一栅极电介质层、第一源极区、第一漏极区和内绝缘间隔物；以及
所述衬底的所述第二区中的第二晶体管，其是p型金属氧化物半导体(PMOS)晶体管，包括第二纳米线、围绕所述第二纳米线的第二栅电极、第二栅极电介质层、第二源极区和第二漏极区，
其中所述第一纳米线在所述第一源极区与所述第一漏极区之间输送电子，所述第二纳米线在所述第二源极区与所述第二漏极区之间输送电子，
其中所述第一栅极电介质层被提供在所述第一纳米线与所述第一栅电极之间以及在所述内绝缘间隔物与所述第一栅电极之间，
其中所述内绝缘间隔物保持所述第一栅极电介质层与所述第一源极区和所述第一漏极区之间的间隔，
其中所述第二栅极电介质层被提供在所述第二纳米线与所述第二栅电极之间、所述第二源极区与所述第二栅电极之间、以及所述第二漏极区与所述第二栅电极之间，
其中所述第二栅极电介质层与所述第二源极区和所述第二漏极区接触，以及
其中所述内绝缘间隔物设置在所述第一栅电极与所述第一源极区和所述第一漏极区之间，且所述第一栅电极与所述第一源极区和所述第一漏极区之间的距离大于所述第二栅电极与所述第二源极区和所述第二漏极区之间的距离。
16.根据权利要求15所述的半导体器件，
其中所述第一源极区和所述第一漏极区与所述第一栅极电介质层不接触。
17.根据权利要求15所述的半导体器件，还包括：
第一外部绝缘间隔物，其在所述第一纳米线的与所述内绝缘间隔物以及与所述衬底相反的侧，在侧面围绕所述第一栅电极，以及
第二外部绝缘间隔物，其在所述第二纳米线的与所述衬底相反的侧，在侧面围绕所述第二栅电极。
18.根据权利要求15所述的半导体器件，
其中所述第一晶体管包括在所述第一源极区与所述第一漏极区之间输送电子并被所述第一栅电极围绕的至少一个第三纳米线，
其中所述第一栅极电介质层被提供在所述第一纳米线和所述至少一个第三纳米线中的每一个与所述第一栅电极之间，
其中所述内绝缘间隔物在垂直于所述衬底的方向上被提供在所述第一纳米线和所述至少一个第三纳米线中的相邻两个之间，
其中所述第二晶体管包括在所述第二源极区与所述第二漏极区之间输送电子并被所述第二栅电极围绕的至少一个第四纳米线，以及
其中所述第二栅极电介质层被提供在所述第二纳米线和所述至少一个第四纳米线中的每个与所述第二栅电极之间。
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