CN105993064B - 用于环绕栅极架构的选择性蚀刻 - Google Patents
用于环绕栅极架构的选择性蚀刻 Download PDFInfo
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- CN105993064B CN105993064B CN201380081248.9A CN201380081248A CN105993064B CN 105993064 B CN105993064 B CN 105993064B CN 201380081248 A CN201380081248 A CN 201380081248A CN 105993064 B CN105993064 B CN 105993064B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
本公开内容涉及一种对牺牲材料进行蚀刻的方法。该方法包括:在反应室中供应半导体衬底,其中衬底包括被布置在衬底上的沟道以及被布置在沟道的至少一部分上的牺牲层。该方法还包括:向反应室供应卤间化合物蒸汽;利用卤间化合物蒸汽来对牺牲层的至少一部分进行蚀刻;以及从牺牲层下方暴露出所述沟道的至少一部分。
Description
技术领域
本公开内容涉及借助于卤间化合物或卤素-稀有元素化合物利用气相蚀刻技术对环绕栅极架构进行选择性蚀刻。
背景技术
随着半导体器件缩小,三维拓扑结构的使用有所增加。在晶体管设计中实现了用于形成沟道的一部分的环绕栅极(gate all around)架构(包括纳米线)。在形成这种设计中使用替代金属栅极方法的情况下,在各个步骤中使用牺牲材料来提供用于形成器件中的其它特征的支架。例如,在牺牲栅极的两侧上沉积牺牲栅极材料并且形成侧壁间隔件。在之后的工艺中,然后移除牺牲材料以便给要部署在晶体管中的实际栅极电极让路。类似地,在纳米线之间形成牺牲层,以便在制造期间支撑纳米线。
然而,例如在纳米线之间的牺牲层材料往往在组分上与纳米线材料不会有太大区别。湿法蚀刻掉牺牲材料具有潜在的挑战,例如沟道塌陷、蚀刻选择性问题、以及蚀刻剂不能够到达要蚀刻的所有表面。认为使用等离子体蚀刻的各向同性蚀刻改善了蚀刻剂对要蚀刻的表面的可达性,然而,来自等离子体的损失以及蚀刻选择性仍然有待改善。因此,在提供其中蚀刻选择性相对高的蚀刻工艺中仍然有改善的空间,在蚀刻材料对特征几何形状的可达性中仍有改善的空间,并且在使用替代栅极方法来形成三维拓扑结构中材料损失被最小化。
附图说明
通过参考结合附图对本文所述实施例所作的以下说明,本公开内容的上述特征和其它特征以及实现它们的方式将变得更为显而易见,并且可以更好地加以理解,在附图中:
图1示出了从半导体器件的沟道层之间对牺牲材料进行蚀刻的流程图;
图2a和图2b示出了形成环绕栅极器件的方法的实施例的流程图。流程图在图2a开始并且在图2b结束;
图3a示出了在半导体衬底上形成的鳍状件的实施例,其中该鳍状件包括沟道材料和牺牲材料的交替层的堆叠体,该堆叠体被覆盖有硬掩模,还示出了浅沟槽隔离区;
图3b示出了鳍状堆叠体的实施例,该鳍状堆叠体具有在鳍状堆叠体上方形成的牺牲栅极电极;
图3c示出了在鳍状堆叠体上方的牺牲电极的两侧上形成的侧壁间隔件的实施例;
图3d示出了沿着线3d-3d截取的图3c的剖面视图;
图3e示出了其中移除了鳍状堆叠体以便给源极和漏极材料生长让路的半导体器件;
图3f示出了包括在侧壁间隔件的两侧上生长的源极和漏极的半导体器件的剖面;
图3g示出了半导体器件的实施例的透视图,该半导体器件包括沉积在源极区和漏极区上方的层间电介质;以及
图3h示出了其中移除了牺牲栅极的半导体器件的实施例的剖面;
图3i示出了沿着线3i-3i截取的图3h的剖面视图;
图3j示出了其中移除了硬掩模和牺牲材料层的半导体器件的实施例;
图3k示出了半导体器件的实施例,在该半导体器件中电介质层形成在沟道材料上方并且栅极电极围绕沟道材料而形成。
具体实施方式
如上面提到的,随着晶体管持续缩放,针对三维拓扑结构的需求变得相对地必不可少。环绕栅极架构(包括纳米线)连同三栅极(或鳍式场效应晶体管)架构已经在金属氧化物半导体或者互补金属氧化物半导体晶体管设计中实现。在使用替代金属栅极或消减(subtractive)金属栅极工艺来形成三维晶体管中,在各个步骤中使用牺牲材料并且然后在形成晶体管期间移除牺牲材料。例如,在纳米线层之间使用牺牲层,以便给后续在流工艺中形成栅极电极让路。然而,牺牲材料往往在组分上类似于形成纳米线的沟道材料。湿法蚀刻掉牺牲材料具有潜在的挑战,例如沟道塌陷、蚀刻选择性、以及蚀刻剂到达要蚀刻的所有表面的能力。认为使用等离子体蚀刻的各向同性蚀刻改善了蚀刻剂对要蚀刻的表面的可达性,然而,发生来自等离子体的损失并且蚀刻选择性仍然有待改善。
在本文所描述的工艺中,在气相中使用卤间化合物和卤素-稀有元素化合物,以从沟道材料周围对牺牲材料进行蚀刻,以便形成提供晶体管中的沟道的至少一部分的纳米线。在移除纳米线之间的牺牲层时,蚀刻工艺不需要掩模,这是因为蚀刻剂对其它材料(例如,层间电介质、浅沟槽材料、栅极间隔件、以及源极和漏极材料)呈现选择性。此外,工艺能够改善蚀刻剂对器件的特征的可达性。
在实施例中,本公开内容涉及一种对用于形成半导体器件的牺牲材料进行蚀刻的方法。如图1的实施例中所示出的,工艺100通常包括:在反应室中供应半导体衬底102。半导体衬底例如包括沟道材料,其中沟道材料可以布置在衬底上或者由半导体衬底的一部分形成。本文中沟道被理解为在半导体中源极与漏极之间的材料区,其中取决于场效应晶体管的类型(即,NMOS或PMOS),该材料区流动有电子或空穴。此外,半导体衬底还包括牺牲材料,其中牺牲材料布置在沟道材料的至少一部分上,包括在沟道材料上方,在沟道材料下方,或者在一侧以上围绕沟道材料。牺牲材料被理解为如下材料:最初被沉积以提供临时支架,支撑形成的晶体管的环绕栅极结构,并且然后被移除。在形成纳米线的情况下,在制造的大部分过程中由牺牲层来支持沟道层。例如,在采用纳米线来形成沟道的环绕栅极器件的情况下,利用栅极电介质和栅极电极来替代纳米线之间的沟道区中的牺牲层。
在实施例中,由单晶材料(例如,硅、锗、硅锗、或者III-V族化合物半导体材料)来形成半导体衬底。在其它实施例中,由绝缘体上硅衬底来形成衬底,其中上部绝缘体层由被布置在单晶材料上的材料(包括,但不限于,二氧化硅、氮化硅或者氮氧化硅)组成。沟道材料可以从以下材料中的一种或多种材料中选择:硅(Si)、锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)、铟锡(InSb)、磷化镓(GaP)、锑化镓(GaSb)、砷化铟铝(InAlAs)、砷化铟镓(InGaAs)、磷化镓锑(GaSbP)、镓砷锑(GaAsSb)、磷化铟(InP)、以及石墨烯。牺牲材料包括包含III族、IV族或V族元素的半导体,其中在实施例中,III族、IV族或V族元素选自由以下各项组成的组:碳、氮、镓、硅、锗、锡及其组合。在一个实施例中,沟道材料和牺牲材料两者都包括硅。在优选的实施例中,沟道材料包括硅,牺牲材料包括硅锗。
然后在反应室中靠近牺牲材料提供卤间化合物或卤素-稀有元素蒸汽104。卤间化合物被理解为包括至少两种不同的卤素原子的化合物。用于本文的卤间化合物例如包括氯、氟、溴和碘的组合。组分可以是双原子的、三原子的或四原子的,并且包括诸如一氯化碘(ICl)、一溴化碘(IBr)、三氟化氯(ClF3)、三氟化溴(BrF3)、以及四氯化碘(ICl4)之类的化合物。卤素-稀有元素蒸汽包括卤素原子和稀有元素原子二者,包括诸如二氟化氙(XeF2)、四氟化氙(XeF4)、六氟化氙(XeF6)或二溴化氙(XeBr2)之类的材料。
在实施例中,卤间化合物或卤素-稀有元素在-100℃至600℃范围内(包括其中的所有值和范围)的温度下可用作为蒸汽,优选地在20℃至30℃范围内(包括其中的所有值和范围)的温度下。此外,卤间化合物或卤素-稀有元素化合物可以具有在100:1至1000:1的范围内(包括其中的所有比率)的牺牲材料比沟道层的蚀刻选择性。卤间化合物或卤素-稀有元素化合物可以以1sccm至1000sccm范围内(包括其中的所有值和范围)的流率被供应给反应室,并且优选地在10sccm至200sccm的范围内。
可以与卤间化合物或卤素-稀有元素化合物一起供应运载气体,包括Ar、He或N2,并且优选地供应Ar。运载气体与蚀刻剂气体按体积的比率在100:1至1:100的范围内(包括其中的所有值和范围),并且优选地从10:1至1:10。运载气体的流率可以在1sccm至1,000sccm的范围内(包括其中的所有值和范围),并且优选地在10sccm至200sccm的范围内。
在处理期间,反应室中的压强可以维持在1毫托至100毫托的范围内(包括其中的所有值和范围),例如10毫托。在某种程度上,可以使用耦合到反应室的单级或双级真空泵系统以及通过进入反应室的气体流速,来维持反应室中的压强。
然后利用蒸汽来对牺牲材料的至少一部分进行蚀刻106。在蚀刻期间可以在-100℃至600℃范围内的温度下对半导体衬底进行加热,并且优选地在20℃至30℃范围内的温度下进行加热。对牺牲层的蚀刻可以在1秒至600秒范围内(包括其中的所有值和范围)的时间段内发生。然后暴露出牺牲材料下方的沟道材料的至少一部分108。
在上面的实施例中,牺牲材料被沉积为半导体衬底上的层并且沟道材料被沉积为牺牲材料上的层,以使得牺牲材料将沟道层与衬底间隔开,在环绕栅极器件的实施例中是这种情况。在特定的实施例中,在堆叠体中形成牺牲材料和沟道材料的交替层,如本文将参考图2和图3a至图3h将进一步描述的。从沟道层之间移除牺牲层而形成纳米线。纳米线不仅呈现如所示出的正方形剖面,还可以呈现圆形、矩形(纳米带)、六边形、八边形或三角形剖面。本文中提及的纳米线包括上面所描述的各种几何形状。
图2示出了形成包括环绕栅极架构的半导体器件的实施例的流程图。在该实施例中,栅极包括与半导体衬底的表面间隔开的多个纳米线。图3a至图3h示出了在形成工艺中的各个点处半导体中的变化。要注意的是,以数字“2”开始的附图标记指代图2,并且以数字“3”开始的附图标记指代图3a至图3h。
方法200以在半导体衬底上形成牺牲材料和沟道材料的交替层的堆叠体202开始。在特定的实施例中,由硅锗层来形成牺牲材料层,并且由硅来形成沟道材料层。在实施例中,取决于层的成分,经由化学气相沉积、原子层沉积、分子束外延、金属有机化学气相沉积、等离子体增强化学气相沉积、物理气相沉积、或者等离子体增强物理气相沉积来形成层。以在衬底上形成牺牲层开始,按照交替的方式来形成层。可以形成2至20个(包括其中的所有值和范围)交替层,尽管示出了三个牺牲层和三个沟道材料层。
然后在交替的牺牲层和沟道材料层的堆叠体上方沉积可选的硬掩模204。硬掩模材料例如可以包括硅、多孔硅、非晶硅、氮化硅、氮氧化硅、氧化硅、二氧化硅、碳氮化硅、碳化硅、氧化铝、氧化铪、氧化锆、硅酸钽、氧化镧、聚合物材料等等。再次,可以通过化学气相沉积、原子层沉积、等离子体增强化学气相沉积、物理气相沉积、或者等离子体增强物理气相沉积来形成硬掩模材料,这再次取决于层的组分以及期望的属性。
然后对牺牲材料和沟道材料的交替层的堆叠体以及可选的硬掩模进行图案化和蚀刻,以将堆叠体形成为从衬底的表面延伸的鳍状件206。图3a示出了在衬底302上方形成的交替的牺牲层306和沟道材料层308的鳍状堆叠体304。在所示出的示例中,可选的硬掩模312被示出为沉积在堆叠体304的顶部上。牺牲层可以具有在1至100nm范围内(包括其中的所有值和范围)的厚度。沟道材料可以具有在1nm至100nm范围内(包括其中的所有值和范围)的厚度。此外,硬掩模可以具有在1至100nm范围内(包括其中的所有值和范围)的厚度。鳍状堆叠体的宽度可以在1nm至150nm的范围内(包括其中的所有值和范围)。
再次参考图2,在鳍状件的两侧上形成浅沟槽隔离区208。在实施例中,沟槽区可以被蚀刻到衬底表面,并且可以将电介质(例如,氧化硅、氮化硅、氮氧化硅及其组合)沉积到沟槽中,以形成隔离区。还可以使用化学气相沉积、旋转涂覆、或者物理气相沉积技术来形成浅沟槽隔离区。浅沟槽隔离区在图3a中被示出为物件314。浅沟槽隔离区可以具有在1至200nm范围内(包括其中的所有值和范围)的厚度。
再次参考图2,然后使用图案化和化学气相沉积技术在堆叠体的顶部和侧壁上方形成牺牲栅极210。牺牲栅极的示例包括多晶硅。图3b示出了围绕鳍状件304形成的牺牲栅极322。
再次参考图2,然后经由化学气相沉积或原子层沉积,由氧化硅、氮化硅、氮氧化硅或这其组合,在牺牲栅极电极的两侧上形成侧壁间隔件212,其中使用各向异性蚀刻来移除多余的间隔件材料。侧壁间隔件可以呈现在至宽的范围内的厚度。图3c和图3d示出了牺牲栅极材料324以及在牺牲栅极324的两侧上并且围绕鳍状件304的每一侧(即,围绕侧壁和顶面)形成的侧壁间隔件326。如所示出的,在鳍状件304的所有侧(再次,围绕侧壁和顶面)上方形成电极。
然后可以形成纳米线的源极区和漏极区(如图2,214中可以看到的)。移除侧壁间隔件的任一侧上的沟道材料和牺牲材料层,以便为源极区和漏极区的生长让路。取决于沟道材料,例如可以通过硅、掺杂的硅、锗、硅锗、或者其它IIIV元素的外延生长来形成源极区和漏极区,并且耦合到间隔件之间的鳍状堆叠体的部分。在NMOS器件中,源极结构、漏极结构或二者可以是n掺杂的硅。在PMOS器件中,源极结构、漏极结构或二者可以是n掺杂的硅。在生长工艺期间可以通过等离子体掺杂、通过固态源掺杂(solid source doping)等来引入对结构的掺杂。在其它实施例中,牺牲栅极的任一侧(仅示出了一侧)上的栅极堆叠体304的暴露的部分可以通过掺杂沟道材料来提供源极区和漏极区。图3e示出了在移除鳍状件204的源极区和漏极区之后的鳍状堆叠体304,并且图3f示出了在形成源极区332和漏极区334之后的鳍状堆叠体304。
然后在浅沟槽隔离区和源极区以及漏极区上方沉积层间电介质216。可以使用化学气相沉积来沉积层间电介质,并且层间电介质可以包括诸如未掺杂的氧化硅、掺杂的氧化硅(例如,BPSG、PSG)、氮化硅以及氮氧化硅之类的材料。对层间电介质进行抛光以暴露出鳍状堆叠体304。层间电介质328在图3g中被示出为位于侧壁间隔件326的任一侧上,覆盖源极区和漏极区332(334未示出)以及浅沟槽隔离区314。
然后从鳍状堆叠体移除牺牲栅极电极218。可以通过利用适当的蚀刻剂进行蚀刻,来移除牺牲栅极电极。图3h示出了在移除了牺牲栅极电极的情况下的器件,并且图3i示出了沿着线3i-3i截取的图3h的剖面。使用如上面所讨论的卤间化合物或卤素-稀有元素蒸汽,从鳍状件中的沟道层之间移除牺牲层220,从而在沟道区中形成纳米线。再次,不需要提供用于保护剩余暴露的材料的掩模。然后移除可选的硬掩模222。图3j示出了在从沟道层308之间移除了牺牲层306以形成纳米线的情况下的半导体器件300。
然后可以围绕纳米线使用化学气相沉积来沉积栅极电介质层224。形成栅极电介质的材料可以是具有大于3.9的介电常数的高k电介质材料、氧化铪、氮氧化铪、硅化铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌及其组合。栅极电介质可以呈现在至范围内的厚度。
此外,可以在栅极电介质层上方沉积栅极电极材料226,从而填充纳米线之间的区域。栅极材料的示例例如包括金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、钴、镍、钨以及导电金属氧化物。图3k示出了半导体器件300,其中半导体器件300包括被沉积在纳米线308的表面上方的栅极电介质336,以及在纳米线308的沟道区的任一侧上的剩余牺牲层306。图3k还示出了经沉积的栅极电极338,其中栅极电极338对纳米线308的沟道区之间以及其周围的间隔进行填充。
在实施例中,本公开内容还涉及通过上面所描述的卤间化合物或卤素-稀有元素蒸汽蚀刻工艺来形成的半导体器件。例如,所述方法可以用于形成平面晶体管、非平面晶体管、用于平面晶体管和非平面晶体管两者的接触件、以及平面器件和非平面器件中的其它部件或线路互连沟槽。半导体器件例如包括集成电路,该集成电路包括各种部件,例如晶体管、二极管、电源、电阻器、电容器、电感器、传感器、接收器、收发器、天线等等,以及用于形成这些部件的特征,例如互连件、栅极、插头等等。与集成电路相关联的部件可以安装在集成电路上或者连接到集成电路。集成电路是模拟的或数字的,并且可以用于多种应用,例如微处理器、光电设备、逻辑块、音频放大器等等,这取决于与集成电路相关联的部件。集成电路然后可以用作为用于执行计算设备(例如,计算机、手持设备或便携式设备)中的一个或多个相关功能的芯片组的部分。
本公开内容的一个方面涉及一种对牺牲材料进行蚀刻以形成晶体管的方法。所述方法包括:在反应室中供应半导体衬底,其中,所述衬底包括沟道材料和牺牲材料,所述牺牲材料被布置在所述沟道材料的至少一部分上。所述方法还包括:在所述反应室中提供蒸汽,所述蒸汽包括卤间化合物或卤素-稀有元素化合物;利用所述蒸汽来对所述牺牲材料的至少一部分进行蚀刻;以及从所述牺牲材料下方暴露出所述沟道材料的至少一部分。
在上述实施例中,所述沟道材料包括硅,并且所述牺牲材料包括硅锗。另外,在上述实施例中的任何实施例中,所述卤间化合物选自由以下各项构成的组:一氯化碘(ICl)、一溴化碘(IBr)、三氟化氯(ClF3)、三氟化溴(BrF3)、以及四氯化碘(ICl4)。并且在特定的实施例中,所述卤间化合物是三氟化溴。此外,在上述实施例中的任何实施例中,所述卤素-稀有元素化合物选自由以下各项构成的组:二氟化氙(XeF2)、四氟化氙(XeF4)、六氟化氙(XeF6)、或者二溴化氙(XeBr2)。
在上述实施例中的任何实施例中,在-100℃至600℃范围内的温度下对所述半导体衬底进行加热,并且优选地,在20℃至30℃范围内的温度下对所述半导体衬底进行加热。此外,在上述实施例中的任何实施例中,所述蒸汽以1sccm至1000sccm范围内的流率被供应给所述反应室,并且优选地,所述蒸汽以10sccm至200sccm范围内的流率被供应给所述反应室。另外,在上述实施例中的任何实施例中,所述反应室在蚀刻期间维持在1毫托至100毫托范围内的压强下。此外,在上述实施例中的任何实施例中,对所述牺牲层进行蚀刻在1秒至600秒范围内的时间段内发生。
在上述实施例中的任何实施例中,所述方法还包括供应选自以下各项中的一项或多项的运载气体:Ar、He或者N2。另外,在特定的实施例中,所述运载气体以1sccm至1,000sccm的范围内的流率被供应给所述反应室。替代地或者除了上述实施例以外,以100:1至1:100范围内的运载气体与蚀刻剂气体的比率来供应所述运载气体,包括100:1至1:100中的所有值和范围。
在上述实施例中的任何实施例中,所述半导体衬底具有衬底表面,所述牺牲层被布置在所述半导体衬底表面上;所述沟道层被布置在所述牺牲层上,牺牲栅极电极被布置在所述牺牲层和所述沟道层上方,并且栅极间隔件被布置在所述牺牲层和所述沟道层上方的所述牺牲栅极电极的两侧上,其中,利用所述蒸汽对所述牺牲层进行的蚀刻从所述半导体衬底与所述沟道层之间移除牺牲层,从而形成纳米线。
此外,在上述实施例中,在所述半导体衬底表面上提供被交替地设置在堆叠体中的多个牺牲层和多个沟道层。另外,在上述实施例中,在所述纳米线上方沉积高k电介质层。此外,在上述实施例中,在所述高k电介质层上方沉积栅极电介质层。
在本公开内容的另一方面中,提供了一种根据上面所阐述的方法来形成的晶体管。并且在本公开内容的另一方面中,多个所述晶体管包括在集成电路中。
在本公开内容的另一方面中,涉及一种对牺牲材料进行蚀刻以形成支撑在衬底的表面上方的沟道的方法。所述方法包括:在反应室中供应半导体衬底,其中,所述半导体衬底具有:衬底表面;牺牲层,所述牺牲层被布置在所述半导体衬底表面上;沟道层,所述沟道层被布置在所述牺牲层上;牺牲栅极电极,所述牺牲栅极电极被布置在所述牺牲层和所述沟道层上方;栅极间隔件,所述栅极间隔件被布置在所述牺牲层和所述沟道层上方的所述牺牲栅极电极的两侧上。所述方法还包括:对所述牺牲栅极电极进行蚀刻,从而暴露出所述沟道层和所述牺牲层的一部分。所述方法还包括:在所述反应室中提供蒸汽,所述蒸汽包括卤间化合物或卤素-稀有元素化合物;以及利用所述蒸汽来对所述牺牲层进行蚀刻,并且从所述半导体衬底与所述沟道层之间移除所述牺牲层,从而形成纳米线。
在实施例中,所述方法还包括提供多个牺牲层和多个沟道层,其中所述多个牺牲层和所述多个沟道层被交替地设置在所述半导体衬底表面上的堆叠体中。在上述实施例中,所述沟道层包括硅,并且所述牺牲层包括硅锗。此外,在上述实施例中,所述卤间化合物是三氟化溴。
在上述实施例中的任何实施例中,在-100℃至600℃范围内的温度下对所述半导体衬底进行加热。此外,在上述实施例中的任何实施例中,所述蒸汽以1sccm至1000sccm范围内的流率被供应给所述反应室。另外,在上述实施例中的任何实施例中,所述反应室在蚀刻期间维持在1毫托至100毫托范围内的压强下。此外,在上述实施例中的任何实施例中,对所述牺牲层进行蚀刻在1秒至600秒范围内的时间段内发生。
在上述实施例中的任何实施例中,所述方法还包括供应选自以下各项中的一项或多项的运载气体:Ar、He或者N2。另外,在上述实施例中的任何实施例中,所述方法包括:在所述纳米线上方沉积高k电介质层。此外,在上述实施例中的任何实施例中,所述方法还包括:在所述高k电介质层上方沉积栅极电介质层。
在另一方面中,本公开内容涉及一种对牺牲材料进行蚀刻的方法,所述牺牲材料来自环绕栅极器件中的纳米线栅极。所述方法包括:在反应室中供应半导体衬底,其中,所述半导体衬底具有衬底表面、多个硅锗牺牲层和硅沟道层,所述多个硅锗牺牲层和硅沟道层交替地堆叠在所述半导体衬底表面上。所述方法还包括:在20℃至30℃范围内的温度下对所述衬底进行加热。所述方法还包括:以在10sccm至200sccm范围内的流率向所述反应室供应三氟化溴,并且使得所述反应室维持在1毫托至100毫托范围内的压强下。另外,所述方法包括:在1秒至600秒范围内的时间段内利用所述三氟化溴蒸汽对所述牺牲层进行蚀刻,并且移除所述硅锗牺牲层,从而由所述硅沟道层形成纳米线。
在另一实施例中,本公开内容涉及一种晶体管,所述晶体管根据上面阐述的方法中的任何方法形成。在实施例中,多个所述晶体管包括在集成电路中。
出于说明的目的给出了对若干方法和实施例的前述描述。本公开内容并非旨在是详尽的或者将权利要求限制为所公开的精确步骤和/或形式,并且显而易见的是,根据上述教导,许多修改和变型是可能的。旨在由所附权利要求来限定本发明的范围。
Claims (26)
1.一种对牺牲材料进行蚀刻以形成晶体管的方法,包括:
在反应室中供应半导体衬底,其中,所述衬底包括沟道材料和牺牲材料,所述牺牲材料被布置在所述沟道材料的至少一部分上,其中所述衬底还包括布置在所述牺牲材料和所述沟道材料上方的牺牲栅极电极;
蚀刻所述牺牲栅极电极从而暴露所述沟道材料和所述牺牲材料的一部分;
在所述反应室中提供蒸汽,所述蒸汽包括卤间化合物或卤素-稀有元素化合物;
利用所述蒸汽对所述牺牲材料的至少一部分进行蚀刻;以及
从所述牺牲材料下方暴露出所述沟道材料的至少一部分。
2.根据权利要求1所述的方法,其中,所述沟道材料包括硅,并且所述牺牲材料包括硅锗。
3.根据权利要求1所述的方法,其中,所述卤间化合物选自由以下各项构成的组:一氯化碘(ICl)、一溴化碘(IBr)、三氟化氯(ClF3)、三氟化溴(BrF3)以及四氯化碘(ICl4)。
4.根据权利要求1所述的方法,其中,所述卤间化合物是三氟化溴。
5.根据权利要求1所述的方法,其中,所述卤素-稀有元素化合物选自由以下各项构成的组:二氟化氙(XeF2)、四氟化氙(XeF4)、六氟化氙(XeF6)、或者二溴化氙(XeBr2)。
6.根据权利要求1所述的方法,其中,在-100℃至600℃范围内的温度下对所述半导体衬底进行加热。
7.根据权利要求1所述的方法,其中,在20℃至30℃范围内的温度下对所述半导体衬底进行加热。
8.根据权利要求1所述的方法,其中,以在1sccm至1000sccm范围内的流率为所述反应室供应所述蒸汽。
9.根据权利要求1所述的方法,其中,以在10sccm至200sccm范围内的流率为所述反应室供应所述蒸汽。
10.根据权利要求1所述的方法,其中,在蚀刻期间使所述反应室维持在1毫托至100毫托范围内的压强下。
11.根据权利要求1所述的方法,其中,在1秒至600秒范围内的时间段内对所述牺牲层进行蚀刻。
12.根据权利要求1所述的方法,还包括供应选自以下各项中的一项或多项的运载气体:Ar、He或者N2。
13.根据权利要求12所述的方法,其中,以在1sccm至1,000sccm范围内的流率向所述反应室供应所述运载气体。
14.根据权利要求12所述的方法,其中,以在100:1至1:100范围内的运载气体与蚀刻剂气体的比率来供应所述运载气体,所述运载气体与蚀刻剂气体的比率包括在100:1至1:100的范围中的所有值和范围。
15.一种对牺牲材料进行蚀刻以形成被支撑在衬底的表面上方的沟道的方法,包括:
在反应室中供应半导体衬底,其中,所述半导体衬底具有:衬底表面;牺牲层,所述牺牲层被布置在所述半导体衬底表面上;沟道层,所述沟道层被布置在所述牺牲层上;牺牲栅极电极,所述牺牲栅极电极被布置在所述牺牲层和所述沟道层上方;栅极间隔件,所述栅极间隔件被布置在所述牺牲层和所述沟道层上方的所述牺牲栅极电极的两侧上;
对所述牺牲栅极电极进行蚀刻,从而暴露出所述沟道层和所述牺牲层的一部分;
在所述反应室中提供蒸汽,所述蒸汽包括卤间化合物或卤素-稀有元素化合物;以及
利用所述蒸汽对所述牺牲层进行蚀刻,并且从所述半导体衬底与所述沟道层之间移除所述牺牲层,从而形成纳米线。
16.根据权利要求15所述的方法,还包括多个牺牲层和多个沟道层,其中所述多个牺牲层和所述多个沟道层被交替地设置在所述半导体衬底表面上的堆叠体中。
17.根据权利要求15所述的方法,其中,所述沟道层包括硅,并且所述牺牲层包括硅锗。
18.根据权利要求15所述的方法,其中,所述卤间化合物是三氟化溴。
19.根据权利要求15所述的方法,其中,在-100℃至600℃范围内的温度下对所述半导体衬底进行加热。
20.根据权利要求15所述的方法,其中,以在1sccm至1000sccm范围内的流率为所述反应室供应所述蒸汽。
21.根据权利要求15所述的方法,其中,在蚀刻期间使所述反应室维持在1毫托至100毫托范围内的压强下。
22.根据权利要求15所述的方法,其中,在1秒至600秒范围内的时间段内对所述牺牲层进行蚀刻。
23.根据权利要求15所述的方法,还包括供应选自以下各项中的一项或多项的运载气体:Ar、He或者N2。
24.根据权利要求15所述的方法,还包括在所述纳米线上方沉积高k电介质层。
25.根据权利要求24所述的方法,还包括在所述高k电介质层上方沉积栅极电极材料。
26.一种对牺牲材料进行蚀刻的方法,所述牺牲材料来自环绕栅极器件中的纳米线栅极,所述方法包括:
在反应室中供应半导体衬底,其中,所述半导体衬底具有衬底表面、多个硅锗牺牲层和硅沟道层,所述多个硅锗牺牲层和硅沟道层被交替地堆叠在所述半导体衬底表面上,其中所述半导体衬底还包括布置在所述硅锗牺牲层和所述硅沟道层上方的牺牲栅极电极;
蚀刻所述牺牲栅极电极从而暴露至少一个硅锗牺牲层的一部分和至少一个硅沟道层的一部分;
在20℃至30℃范围内的温度下对所述衬底进行加热;
以在10sccm至200sccm范围内的流率向所述反应室供应三氟化溴,并且使所述反应室维持在1毫托至100毫托范围内的压强下;以及
在1秒至600秒范围内的时间段内利用三氟化溴蒸汽对所述牺牲层进行蚀刻,并且移除所述硅锗牺牲层,从而由所述硅沟道层形成纳米线。
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