CN109860170A - 集成半导体装置 - Google Patents

集成半导体装置 Download PDF

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Publication number
CN109860170A
CN109860170A CN201811295405.7A CN201811295405A CN109860170A CN 109860170 A CN109860170 A CN 109860170A CN 201811295405 A CN201811295405 A CN 201811295405A CN 109860170 A CN109860170 A CN 109860170A
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China
Prior art keywords
layer
dielectric layer
semiconductor device
nitride
interlayer dielectric
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CN201811295405.7A
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English (en)
Inventor
彭成毅
吕俊颉
萧孟轩
叶凌彦
卡罗司·迪亚兹
李东颖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109860170A publication Critical patent/CN109860170A/zh
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Abstract

集成半导体装置包含第一半导体装置、层间介电层以及第二半导体装置。第一半导体装置具有第一晶体管结构。层间介电层是在第一半导体装置上。层间介电层的厚度实质为10nm至100nm。第二半导体装置是在层间介电层上且具有作为第二晶体管结构的通道层的二维材料层。

Description

集成半导体装置
技术领域
本揭露是关于一种集成半导体装置，特别是关于一种具有二维材料层的集成半导体装置。
背景技术
电子产业已经历日益增长的电子装置小型化及高速化需求。电子装置的小型化及高速化可同时支持大量更复杂且精密的功能。因此，在半导体产业中，制作低成本、高效能和低功耗集成电路(Integrated Circuit，IC)的趋势持续存在。这些目标大部分是通过缩小半导体集成电路尺寸(例如：最小特征尺寸)而达成，从而提高生产效率及降低相关成本。然而，集成电路在二维空间中可达成的密度存在物理限制。
半导体装置的三维堆叠是用以解决上述问题，以进一步增加密度。构成三维堆叠集成电路或晶片的技术包含三维封装、平行三维整合(parallel 3D integrateion)及单体三维集成电路(monolithic 3D IC)技术。在这些技术中，单体三维集成电路技术具有成本效益、小面积及高异相整合能力的优点。然而，单体三维集成电路技术的关键问题在于，在形成上层装置的制程中的高热预算(thermal budget)需求可能有害于下层装置。
发明内容
本揭露的一态样提供一种集成半导体装置，其是包含第一半导体装置、层间介电层以及第二半导体装置。第一半导体装置具有第一晶体管结构。层间介电层是在第一半导体装置上。层间介电层的厚度实质为10nm至100nm。第二半导体装置具有第二晶体管结构，且具有形成在层间介电层上的二维材料层，其是做为第二晶体管结构的通道层。
附图说明
根据以下详细说明并配合附图阅读，使本揭露的态样获致较佳的理解。需注意的是，如同业界的标准作法，许多特征并不是按照比例绘示的。事实上，为了进行清楚讨论，许多特征的尺寸可以经过任意缩放。
图1是绘示根据本揭露一些实施例的集成半导体装置的结构示意图；
图2A是绘示根据本揭露一些实施例的集成半导体装置的立体视图；
图2B是绘示图2A的集成半导体装置沿着B1-B1’线的剖面视图；
图2C是绘示图2A的集成半导体装置沿着C1-C1’线的剖面视图；
图2D至图2I是绘示根据本揭露一些实施例的形成图2A的集成半导体装置的各中间阶段中沿着B1-B1’线的剖面视图；
图2J至图2N是绘示根据本揭露一些实施例的形成图2A的下部半导体装置的各中间阶段中沿着B1-B1’线的剖面视图；
图3A是绘示根据本揭露一些实施例的集成半导体装置的立体视图；
图3B是绘示图3A的集成半导体装置沿着B2-B2’线的剖面视图；
图3C是绘示图3A的集成半导体装置沿着C2-C2’线的剖面视图；
图3D是绘示图3A的集成半导体装置的等效电路图；
图3E至图3J是绘示根据本揭露一些实施例形成图3A的另一集成半导体装置的各中间阶段中沿着B2-B2’线的剖面视图。
具体实施方式
以下揭露提供许多不同实施例或例示，以实施发明的不同特征。以下叙述的成份和排列方式的特定例示是为了简化本揭露。这些当然仅是做为例示，其目的不在构成限制。举例而言，第一特征形成在第二特征之上或上方的描述包含第一特征和第二特征有直接接触的实施例，也包含有其他特征形成在第一特征和第二特征之间，以致第一特征和第二特征没有直接接触的实施例。
以下使用的用语仅是用于描述特定实施例，而非用以限制附加的申请专利范围。举例而言，除非另外限制，单位形式的用语“一(a)”、“一(an)”、“一个(one)”或“该(the)”也可代表复数形式。除此之外，本揭露在各种例示中会重复元件符号及/或字母。此重复的目的是为了简化和明确，并不表示所讨论的各种实施例及/或配置之间有任何关系。
再者，空间相对性用语，例如“上方(over)”、“在…之上(on)”、“高于(upper)”、“低于(lower)”、“顶部(top)”、“底部(bottom)”及其延伸用语(例如：“水平地(horizontally)”、“侧向地(laterally)”、“下方(underlying)”)等，是为了易于描述附图中所绘示的元素或特征和其他元素或特征的关系。空间相对性用语除了附图中所描绘的方向外，还包含元件在使用或操作时的不同方向。装置可以其他方式定向(旋转90度或在其他方向)，而本文所用的空间相对性描述也可以如此解读。
除非有其他描述，电子通讯及其相关用语，例如“耦合(coupled)”及“电性耦合(electrically coupled)”或“电性连接(electrically connected)”，是代表节点与其他者直接或非直接穿过介于中间的结构通讯的关系。
本揭露的实施例是针对具有半导体装置或结构堆叠的集成半导体装置。通过导入二维(two dimensional，2D)材料层至集成半导体装置中以作为一或多个利用低热预算制程的半导体装置或结构的通道层，集成半导体装置可通过利用低热预算(thermal budget)制程而制得，而不须牺牲效能或降级半导体装置或结构。三维(three dimensional，3D)半导体装置，例如鳍式场效晶体管(fin field effect transistor，FinFET)、环绕式栅极(gate-all-around，GAA)晶体管等，可作为集成半导体装置的部分，故可实现整合三维半导体装置的集成半导体装置。再者，二维材料的高迁移率特性有利于提高集成半导体装置的晶体管速度及功率效率。
图1是绘示根据本揭露一些实施例的集成半导体装置100的简易剖视视图。如图1所示，集成半导体装置100为三维堆叠半导体装置，且在集成半导体装置100中，呈现基材102，在其上的半导体装置104、层间介电(interlayer dielectric，ILD)层106及半导体装置108是依序地堆叠。
基材102可为半导体基材，例如主体半导体基材、绝缘体上覆半导体(semiconductor-on-insulator，SOI)基材、多层或梯度基材，或前述相似物。基材102可包含半导体材料，例如元素半导体材料(包含硅或镓)、化合物或合金半导体(包含碳化硅、硅锗、砷化镓、磷化镓、磷化铟、锑化铟、砷磷化镓、砷化铝铟、砷化铝镓、砷化铟镓、砷化铟、磷化铟镓、砷磷化铟镓、或前述的组合，或其他合适的半导体材料。在一些具体例中，基材102包含结晶硅基材，例如硅晶圆。
半导体装置104可具有晶体管结构，例如平面场效晶体管(field effecttransistor，FET)结构、鳍式场效晶体管结构、环绕式栅极晶体管结构或任何其他合适的结构，其是可通过采取栅极优先(gate first)制造流程或后栅极(gate last)制造流程。
层间介电层106是插入在半导体装置104及半导体装置108之间。层间介电层106可包含一或多个介电材料层，其是可包含一或多个介电材料，例如氧化硅、氮化硅、氮氧化硅、四乙氧基硅烷(Tetra Ethyl Ortho Silicate，TEOS)、磷硅玻璃(Phospho-SilicateGlass，PSG)、硼掺杂磷硅玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃(fluorine-doped silicate glass，FSG)、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯(Parylene)、苯并环丁烯(benzocyclobutene，BCB)或聚酰亚胺。考量到制程耐受度，例如为了避免后续在形成层间介电层106上的元件(例如半导体装置108)的过程中破坏下层半导体装置104，层间介电层106的厚度可约为10nm至100nm。
半导体装置108可具有晶体管结构，例如平面场效晶体管结构、薄膜晶体管(thinfilm transistor，TFT)结构或任何其他合适的前栅极型(front gate)或后栅极型(backgate)结构，其是可通过采取栅极优先制造流程或后栅极制造流程所制造。除此之外，半导体装置108包含二维材料层110。二维材料层可为单层，其是可包含例如石墨烯、铋、六方氮化硼(h-BN)、硫化钼、硒化钼、硫化钨、硒化钨、硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓、硒化铟及/或其类似物。在另一些实施例中，二维材料层110包含三元二维材料，例如WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4(其中x是介于0与1之间)、混合二维材料，例如氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物。在本揭露中，单层可为单分子厚度层、双分子厚度层、三分子厚度层或类似者，其是取决于其中的材料。在另一些实施例中，二维材料层110包含多个单层，其是可包含上述的材料。在半导体装置108具有晶体管结构的例示中，二维材料层110可为晶体管结构的一部分(即通道层)，其是具有高迁移率特性，且因而有利于提高高速晶体管及功率效率。为了提供晶体管结构的通道层优良的静电控制，二维材料层110的厚度可约为10埃至50埃。
以下对集成半导体装置100的一些具体例做更详细的描述。
请参阅图2A至图2C，图2A是绘示根据本揭露一些实施例的集成半导体装置200的立体视图，而图2B及图2C是分别为图2A的集成半导体装置200沿着B1-B1’线及C1-C1’线的剖面视图。
集成半导体装置200包含下部半导体装置200A及上部半导体装置200B。在一些实施例中，如图2A至图2C所示，下部半导体装置200A可包含鳍式场效晶体管结构。在各种实施例中，下部半导体装置200A可包含平面场效晶体管、环绕式栅极晶体管结构及/或任何其他合适的结构。
层间介电层202是插入在下部半导体装置200A及上部半导体装置200B之间。层间介电层202可包含一或多个介电材料层，其是可包含一或多种介电材料，例如氧化硅、氮化硅、四乙氧基硅烷、磷硅玻璃、硼掺杂磷硅玻璃、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。考量到制程耐受度，例如为了避免在后续构成上部半导体装置200B的制程中因后续元件的改变而破坏下部半导体装置200A，层间介电层202的厚度可约为10nm至100nm。
在一些实施例中，如图2A及图2B所示，上部半导体装置200B包含平面场效晶体管结构。在一些实施例中，上部半导体装置200B可包含薄膜晶体管(thin film transistor，TFT)结构或任何其他合适的前栅极型、后栅极型或合并的结构。
上部半导体装置200B可具有多个晶体管结构204，其中每一个晶体管结构204的二维材料层206是在下部半导体装置200A之上的层间介电层202上方，并做为晶体管结构204的通道层。为了简洁目的，以下仅以一个晶体管结构204进行描述。在一些实施例中，二维材料层206为单层，其是由例如石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨、硒化钨、硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓、硒化铟及/或其类似物所形成。在另一些实施例中，二维材料层206是由三元二维材料，例如WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4(其中x是介于0与1之间)、混合二维材料，例如氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物所形成。为了提供晶体管结构204通道层优良的静电控制，二维材料层206的厚度T206可约为10埃至50埃。在另一些实施例中，多个具有相同或不同二维材料的二维材料层206是形成在层间介电层202上。
晶体管结构204的源极电极208及漏极电极210是设置在二维材料层206的相对两端。源极电极208及漏极电极210可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成。
栅极介电层212是设置在层间介电层202、二维材料层206、源极电极208及漏极电极210上。栅极介电层212是由介电材料所形成，其中介电材料包含但不限于氧化硅、氮化硅、氮氧化硅、氧化铪、氧化钽、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、硅化锆、铝化锆、氧化锡、氧化锆、氧化钛、氧化铝、高介电常数材料、前述的组合及/或其他合适的材料，且栅极介电层212的厚度可约为1nm至5nm。
栅极电极214是设置在栅极介电层212及二维材料层206上，并侧向地介于源极电极208及漏极电极210之间。栅极电极214可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成，且栅极电极214的厚度可约为10nm至20nm。在一些实施例中，栅极电极214、源极电极208及漏极电极210是由相同或相似材料所形成。
图2D至图2I是绘示根据本揭露一些实施例的形成图2A的集成半导体装置200的各中间阶段中沿着B1-B1’线的剖面视图。
如图2D所示，层间介电层202是形成在下部半导体装置200A上。在一些实施例中，下部半导体装置200A可包含鳍式场效晶体管结构，其将在之后配合图2J至图2N进行描述。在各种实施例中，下部半导体装置200A可包含平面场效晶体管、环绕式栅极晶体管结构及/或任何其他合适的结构。层间介电层202可由一或多种介电材料所形成，例如氧化硅、氮化硅、四乙氧基硅烷(TEOS)、磷硅玻璃(PSG)、硼掺杂磷硅玻璃(BPSG)、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。层间介电层202的厚度T202可约为10nm至100nm，且可通过进行例如化学气相沉积(Chemical Vapor Depostion，CVD)、物理气相沉积法(physical vapor deposition，PVD)、原子层沉积法(atomic layer deposition，ALD)、旋转涂布(spin-on coating)或其他合适的制程而形成。进一步地，可进行平坦化制程，例如化学机械研磨(chemical mechanical polishing，CMP)，以平坦化层间介电层202。
如图2E所示，二维材料层206是形成在层间介电层202上。在一些实施例中，二维材料层206为单层，其是由例如石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨、硒化钨、硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓、硒化铟及/或其类似物所形成。在另一些实施例中，二维材料层206是由三元二维材料，例如WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4(其中x是介于0与1之间)、混合二维材料，例如氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物所形成。二维材料层206的厚度T206可约为10埃至50埃，且可通过进行制程所形成，例如化学气相沉积、原子层沉积法、低热蒸镀(low thermal evaporation)、注射、晶圆尺度转印(wafer scale transfer)，或其他适于在温度低于400℃下操作的制程，其是取决于选择用于二维材料层206的材料。在另一些实施例中，具有相同或不同二维材料的多个二维材料层206是形成在层间介电层202上。
请参阅图2F，二维材料层206是被图案化以形成每一个晶体管结构204的通道层在下部半导体装置200A上。在一些实施例中，举例而言，光阻层(图未绘示)是设置在二维材料层206上，接着通过光微影技术被图案化，以形成光阻罩幕。在形成光阻罩幕之后，可进行一或多个蚀刻制程(例如非等向性干式蚀刻制程或相似者)，以移除二维材料层206的不需要的部分。接着，可通过进行例如灰化制程及/或湿式蚀刻制程以移除光阻罩幕。为了简洁目的，以下仅以一个晶体管结构204进行描述，而其他晶体管结构204可通过相同制程而形成。
请参阅图2G，源极电极208及漏极电极210是设置在二维材料层206的相对两端。源极电极208及漏极电极210可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成。源极电极208及漏极电极210可通过进行一或多种制程而形成，例如物理气相沉积法、原子层沉积法、电化学电镀法(electro-chemical plating)、无电式电镀法(electroless plating)、前述的组合或其他合适的制程。
请参阅图2H，栅极介电层212是设置在层间介电层202、二维材料层206、源极电极208及漏极电极210上。栅极介电层212是由介电材料所形成，其中介电材料包含但不限于氧化硅、氮化硅、氮氧化硅、氧化铪、氧化钽、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、硅化锆、铝化锆、氧化锡、氧化锆、氧化钛、氧化铝、高介电常数材料、前述的组合及/或其他合适的材料。栅极介电层212的厚度可约为1nm至5nm，且可通过进行制程所形成，例如化学气相沉积、电浆辅助化学气相沉积法(plasma-enhanced chemical vapordeposition，PECVD)、高密度电浆化学气相沉积(high density plasma chemical vapordeposition，HDPCVD)、原子层沉积法、旋转涂布、溅镀(sputtering)、前述的组合或其他合适的制程。
请参阅图2I，栅极电极214是设置在栅极介电层212及二维材料层206上，并侧向地介于源极电极208及漏极电极210之间。栅极电极214可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成，且栅极电极214的厚度可约为10nm至20nm。栅极电极214可通过进行制程而形成，例如物理气相沉积法、原子层沉积法、电化学电镀法、无电式电镀法、前述的组合或其他合适的制程。在一些实施例中，栅极电极214、源极电极208及漏极电极210是由相同或相似材料所形成。
为了如图2E至图2I所示的集成半导体装置200的形成，在上部半导体装置200B内的每一个晶体管结构202的二维材料层206可通过进行低热预算制程而形成，集成半导体装置200可在不牺牲上部半导体装置200B(包含晶体管结构204)的效能或降级下部半导体装置200A下而制作。
图2J至图2N是绘示根据本揭露一些实施例的形成如图2A所示集成半导体装置200的下部半导体装置200A的各中间阶段中沿着的B1-B1’线的各种剖面视图。
请参阅图2J，提供基材216，且后续元件是形成在基材216内或基材216上，在以下段落中再进行详述。基材216可为半导体基材，例如主体半导体基材、绝缘体上覆半导体基材、多层或梯度基材，或前述相似物。基材216可包含半导体材料，例如元素半导体材料(包含硅或镓)、化合物或合金半导体(包含碳化硅、硅锗、砷化镓、磷化镓、磷化铟、锑化铟、砷磷化镓、砷化铝铟、砷化铝镓、砷化铟镓、砷化铟、磷化铟镓、砷磷化铟镓、或前述的组合，或其他合适的半导体材料。在一些具体例中，基材216包含结晶硅基材，例如硅晶圆。
基材216可被掺杂或未掺杂，其是取决于设计需求。在一些实施例中，基材216包含一或多个掺杂区域，其可被p型杂质(例如硼或氟化硼)或n型杂质(例如磷或砷)所掺杂，且掺杂区域的掺质浓度可为例如约1017个原子/立方厘米至约1018个原子/立方厘米。进一步地，可在掺杂区域上进行退火制程，以活化掺杂区域内的p型杂质或n型杂质。
同样如图2J所示，磊晶层结构218是形成在基材216上，且包含用以形成鳍片的交替的第一磊晶层218A及第二磊晶层218B。第一磊晶层218A及第二磊晶层218B的每一者可由IV族材料(例如：硅、锗、硅锗、硅锗锡或类似物)、III-V族化合物材料(例如：砷化镓、磷化镓、砷化铟、磷化铟、锑化铟、砷磷化镓、砷化铝铟、砷化铝镓、砷化铟镓、磷化铟镓、砷磷化铟镓或类似物)或其他合适的材料。第一磊晶层218A及第二磊晶层218B可分别由硅锗及硅所形成。另外，第一磊晶层218A及第二磊晶层218B可分别由硅及硅锗所形成。第一磊晶层218A及第二磊晶层218B可被磊晶成长，其是通过例如有机金属化学气相沉积(metal organicchemical vapor deposition，MOCVD)、分子束磊晶(molecular beam epitaxy，MBE)、液相磊晶(liquid phase epitaxy，LPE)、气相磊晶(vapor phase epitaxy，VPE)、超高真空化学气相沉积(ultra high vacuum chemical vapor deposition，UHVCVD)、前述的组合或其他合适的技术。磊晶层结构218的厚度可约为40nm至90nm，且第一磊晶层218A及第二磊晶层218B的每一者的厚度可约为3nm至20nm。
如图2J所绘示，磊晶层结构218包含五个第一磊晶层218A及五个第二磊晶层218B。在各种实施例中，磊晶层结构218可包含任何数量的第一磊晶层218A及任何数量的第二磊晶层218B。
在形成磊晶层结构218之后，可在磊晶层结构218及基材216上进行蚀刻制程，以形成鳍片，其是包含磊晶层结构的剩余部分及下方的基材216。每一个鳍片的通道高度可约为40nm至90nm，且两相邻鳍片的节距可约为10nm至60nm。在磊晶层结构218及基材216上进行的蚀刻制程可为例如非等向性蚀刻制程(例如：干式蚀刻)、反应性离子蚀刻(reactive ionetching，RIE)、中性粒子束蚀刻(neutral beam etching，NBE)、前述的组合或其他任何合适的制程。
请参阅图2K，虚拟栅极介电层228是形成在磊晶层结构218上，然后，虚拟栅极电极层230是形成在虚拟栅极介电层228上。
虚拟栅极介电层228可由氧化硅、氮化硅、氮氧化硅、例如碳掺杂氧化物的低介电常数介电质、例如孔洞碳掺杂二氧化硅的极低介电常数介电质、例如聚酰亚胺的聚合物、例如氮化硅、氮氧化硅、氧化铪、氧化锆铪、氧化硅铪、氧化钛铪、氧化铝铪的高介电质或其他合适的材料，且可通过进行制程而形成，例如热氧化、化学气相沉积、电浆辅助化学气相沉积、次大气压化学气相沉积(sub-atmospheric CVD，SACVD)、物理气相沉积法、溅镀或其他本领域习知的合适制程。
虚拟栅极电极层230为导电材料，且可由非晶相硅、多晶硅、多晶硅锗、金属、金属氮化物、金属硅化物、金属氧化物或类似物。虚拟栅极电极层230可通过物理气相沉积法、化学气相沉积、原子层沉积法、溅镀或其他本领域习知的合适制程而沉积。在另一些实施例中，非导电材料可用以形成虚拟栅极电极层230。
在形成虚拟栅极介电层228及虚拟栅极电极层230之后，硬罩幕层232是形成在虚拟栅极电极层230上。硬罩幕层232可由氧化物材料(例如：氧化硅、氧化铪)、氧化物材料(例如：氮化硅、碳氮化硅、氮化钛)、前述的组合或其他合适的材料所形成。硬罩幕层232可通过进行制程而形成，例如：热氧化、低压化学气相沉积(low pressure CVD，LPCVD)、电浆辅助化学气相沉积、物理气相沉积、化学气相沉积、原子层沉积法、前述的组合或其他合适的制程，且可通过利用光微影技术而被图案化。
接着，在硬罩幕层232的辅助下进行蚀刻制程，以图案化虚拟栅极介电层228及虚拟栅极电极层230，借以形成分别包含虚拟栅极介电层228及虚拟栅极电极层230的剩余部分的虚拟栅极堆叠234。在蚀刻制程过程中，虚拟栅极介电层238是做为蚀刻中止层，以保护在虚拟栅极介电层228之下的鳍片。对虚拟栅极介电层228及虚拟栅极电极层230的蚀刻制程可包含合适的非等向性蚀刻制程，例如反应性离子蚀刻、中性粒子束蚀刻、前述的组合或其他合适的蚀刻制程。然后，在虚拟栅极介电层228及虚拟栅极电极层230被蚀刻之后，硬罩幕层232是被移除。
在一些实施例中，每一个鳍片的第一磊晶层218A可选择性地被蚀刻，且每一个鳍片的剩余第二磊晶层218B形成纳米线。为了说明，在第一磊晶层218A是由硅锗所形成且第二磊晶层218B是由硅所形成的实施例中，第一磊晶层218A是利用蚀刻剂被移除，其中前述蚀刻剂蚀刻硅锗具有比蚀刻硅更高的速率，例如NH4OH：H2O2：H2O(氢氧化氨、双氧水混合物)、H2SO4+H2O2(硫酸、双氧水混合物)或类似物，且第二磊晶层218B是被保留以形成纳米线。另外，在第一磊晶层218A是由硅所形成且第二磊晶层218B是由硅锗所形成的实施例中，第二磊晶层218B是被移除，且第一磊晶层218A是被保留以形成纳米线。
在图2L中，间隙壁层236是沿着虚拟栅极堆叠234的相对两侧壁形成。间隙壁层236可由介电材料所形成，例如氧化硅、氮化硅、氮氧化硅、碳化硅、前述的组合或其他合适的材料，且间隙壁层236可通过一或多种制程所形成，制程包含但不限于沉积制程、微影制程、蚀刻制程及/或前述的组合。在另一些实施例中，间隙壁层236可为包含多层的复合材料结构。
然后，根据一些实施例，源极/漏极区域238是分别沿着虚拟栅极堆叠234的相对两侧在鳍片的暴露部分(例如：未被间隙壁层236及虚拟栅极堆叠234覆盖)上形成。除了交替的第一磊晶层218A及第二磊晶层218B所造成的压力之外，在源极/漏极区域238中磊晶成长材料的使用使得源极/漏极区域238施加压力在通道区域内。用于源极/漏极区域238的材料可变化为鳍式场效晶体管的各种型式(例如n型及p型)，使一种型式的材料是用于n型鳍式场效晶体管，以施加抗拉应力在通道区域内，而另一种型式的材料是用于p型鳍式场效晶体管，以施加抗压应力在通道区域内。为了说明，一些源极/漏极区域238可包含例如磷化硅、碳化硅、砷掺杂硅、磷掺杂硅或磷掺杂硅锗，或其类似物，以形成n型鳍式场效晶体管，而另一些源极/漏极区域238可包含例如硅、锗、或以硼或镓或锡掺杂的硅锗，或其类似物，以形成p型鳍式场效晶体管。
在不用材料被用于n型装置及p型装置的实施例中，可掩蔽一者(例如n型鳍片)而形成磊晶材料在另一者(例如p型鳍片)上，并对另一者重复制程。源极/漏极区域238可被掺杂，其是透过布植制程以植入适当的掺质，或在材料被成长时原位掺杂。在一些实施例中，一些源极/漏极区域238是由以磷化硅或以磷掺杂的碳化硅所形成，以形成n型鳍式场效晶体管，而另一些源极/漏极区域238是由以硅锗或以硼掺杂的锗所形成，以形成p型鳍式场效晶体管。源极/漏极区域238可分别以p型及n型掺质布植。源极/漏极区域238可具有杂质浓度为约1019个原子/立方厘米至约1021个原子/立方厘米。
在形成源极/漏极区域238之后，层间介电层240是形成在源极/漏极区域238及基材216上。层间介电层240可由一或多个介电材料所形成，例如氧化硅、氮化硅、氮氧化硅、四乙氧基硅烷、磷硅玻璃、硼掺杂磷硅玻璃、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。层间介电层240可通过进行一或多种制程而形成，例如化学气相沉积、物理气相沉积法、原子层沉积法、旋转涂布或其他合适的制程。如图2L所示，在一些实施例中，层间介电层240为双层结构，其是包含二个次层240A及次层240B。在各种实施例中，层间介电层240可为单层或多层。进一步地，可进行平坦化制程，例如化学机械研磨，以平坦化层间介电层240。
请参阅图2M，在层间介电层240形成之后，虚拟栅极堆叠234被移除，借以形成凹陷242在层间介电层240内。虚拟栅极堆叠234是通过进行一或多个蚀刻制程而被移除。举例而言，虚拟栅极堆叠234可通过进行干式蚀刻制程而被移除，然后虚拟栅极介电层228可通过进行湿式蚀刻制程而被移除。然而，其他合适的蚀刻制程可用以移除虚拟栅极堆叠234。
然后，栅极244是分别地形成以填充凹陷242。详细而言，栅极244是分别地包含栅极介电质246及栅极电极248。栅极介电质246是分别地形成为与凹陷242共形，而栅极电极248是分别地形成在凹陷242内的栅极介电质246上。
栅极介电质246可由介电材料所形成，例如但不限于氧化硅、氮化硅、氮氧化硅、氧化铪、氧化钽、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、硅化锆、铝化锆、氧化锡、氧化锆、氧化钛、氧化铝、高介电常数材料、前述的组合及/或其他合适的材料。在一些实施例中，栅极介电质246包含多层结构，例如具有高介电常数材料的氧化硅或氮氧化硅。栅极介电质246可通过进行一或多个制程而形成，制程包含但不限于化学气相沉积、电浆辅助化学气相沉积法、高密度电浆化学气相沉积、原子层沉积法、旋转涂布、溅镀、前述的组合或其他合适的制程。
栅极电极248可通过一或多个制程而形成，制程包含但不限于物理气相沉积法、化学气相沉积、低压化学气相沉积、原子层沉积法、旋转沉积、电镀及/或前述的组合。栅极电极248可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成。
请参阅图2N，蚀刻中止层250及层间介电层252是依序地形成在如图2M所示的结构上。蚀刻中止层250可由氮化硅、氮化钛、氮化铝及/或其他蚀刻剂选择性材料。在各种实施例中，蚀刻中止层250可为单层或多层，且其厚度可约为5nm。蚀刻中止层250可通过进行一或多个制程而形成，例如化学气相沉积、电浆辅助化学气相沉积法、有机金属化学气相沉积、原子层沉积、溅镀及/或其他合适的制程。
层间介电层252可由一或多个介电材料所形成，例如氧化硅、氮化硅、氮氧化硅、四乙氧基硅烷、磷硅玻璃、硼掺杂磷硅玻璃、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。层间介电层252的厚度可约为15nm至85nm，且可通过进行一或多种制程而形成，例如化学气相沉积、物理气相沉积法、原子层沉积法、旋转涂布或其他合适的制程。进一步地，可进行平坦化制程，例如化学机械研磨，以平坦化层间介电层252。
然后，在层间介电层252、蚀刻中止层250及层间介电层240上进行一或多个蚀刻制程，以形成凹陷，然后导电插塞254是分别地通过填充凹陷而形成。在一些实施例中，举例而言，光阻层(图未绘示)是沉积在层间介电层252上，接着通过光微影技术而被图案化以形成光阻罩幕。在形成光阻罩幕之后，一或多个蚀刻制程，例如非等向性干式蚀刻制程或类似者，可被进行以蚀刻层间介电层252、蚀刻中止层250及层间介电层240的垂直地未被光阻罩幕覆盖的部分。当凹陷的深度达到预设值时，蚀刻制程可被停止。在一些实施例中，凹陷的底部是垂直地高于层间介电层240的顶表面。接着，光阻罩幕可通过进行例如灰化制程及/或湿式蚀刻制程而被移除。
导电插塞254包含衬层256，且各自地包含接触窗258。衬层256是与形成为与凹陷共形，然后接触窗258是形成在衬层256上，并各自地填充凹陷。衬层256可包含钛、氮化钛、钽、氮化钽或类似物，且可通过进行例如原子层沉积、化学气相沉积或相似制程而形成。接触窗258可由金、银、铜、钨、铝、镍、前述的组合、金属合金或类似物，且可通过进行例如原子层沉积、化学气相沉积、物理气相沉积或相似制程而形成。进一步地，可进行平坦化制程，例如化学机械研磨，以移除接触窗258及衬层256在层间介电层252的顶表面上的多余部分。然后，形成半导体装置200A(例如：实施例中的鳍式场效晶体管结构)，其中导电插塞254是形成为穿过层间介电层252、蚀刻中止层250及层间介电层240至各种元件，例如源极/漏极238及/或其他未绘示于图中的元件。在一些其他实施例中，导电插塞254各自包含接触窗258但不具有衬层256。
在各种实施例中，整合在三维叠半导体装置中的下部半导体装置及上部半导体装置可共同地形成电子电路结构。举例而言，图3A是绘示根据本揭露一些实施例的集成半导体装置300的透视示意图，而图3B及图3C是分别绘示图3A所示的集成半导体装置300沿着B2-B2’线及C2-C2’线(其是与B2-B2’线垂直)的剖面视图。
集成半导体装置300包含下部半导体装置300A及上部半导体装置300B。在一些实施例中，如图3A至图3C所示，下部半导体装置300A可包含鳍式场效晶体管装置结构，且下部半导体装置300A是类似于如图2A至图2C所示的下部半导体装置200A，而下部半导体装置300A形成的中间阶段是类似于如图2J至图2N所示，因此下部半导体装置300A的细节便不在此重复描述。在各种实施例中，下部半导体装置300A可包含平面场效晶体管、环绕式栅极晶体管结构及/或其他合适的结构。
层间介电层302是插入在下部半导体装置300A及上部半导体装置300B之间。层间介电层302可包含一或多个介电材料层，其是可包含一或多种介电材料，例如氧化硅、氮化硅、四乙氧基硅烷、磷硅玻璃、硼掺杂磷硅玻璃、低介电常数材料及/或其他合适的材料。低介电常数材料的具体例包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。考量到制程耐受度，例如为了避免在后续形成层间介电层302上的元件(包含上部半导体装置300B的元件)的过程中破坏下部半导体装置300A，层间介电层302的厚度可约为10nm至100nm。
在上部半导体装置300B中，导电插塞304、306及308从层间介电层302的上表面向下延伸。导电插塞304及导电插塞306穿透层间介电层302，以分别接触在下部半导体装置300A内的导电插塞310及导电插塞312，而导电插塞308穿透层间介电层302，且下部半导体装置300A的层间介电层314及蚀刻中止层316接触下部半导体装置300A的栅极318。导电插塞304、306及308可由金、银、铜、钨、铝、镍、前述的组合、金属合金或类似物所形成。
栅极堆叠320是在层间介电层302上。每一个栅极堆叠320包含金属层322及介电层324，其是依序堆叠在层间介电层302上。换言之，如图3B所示，每一个栅极堆叠320为堆叠结构，其中金属层322是形成在层间介电层302上，且介电层324是形成在金属层322上。金属层322的厚度可约为10nm至20nm，且金属层322可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成。介电层324的厚度可约为1nm至5nm，且介电层324可由介电材料所形成，例如但不限于氧化硅、氮化硅、氮氧化硅、氧化铪、氧化钽、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、硅化锆、铝化锆、氧化锡、氧化锆、氧化钛、氧化铝、高介电常数材料、前述的组合及/或其他合适的材料。如图3B所示，栅极堆叠320其中的一者接触导电插塞308。
二维材料层326是形成在栅极堆叠320、层间介电层302及导电插塞304、306及308上。在一些实施例中，二维材料层326为单层，且是由例如石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨、硒化钨、硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓、硒化铟及/或其类似物所形成。在另一些实施例中，二维材料层326是由三元二维材料，例如WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4(其中x是介于0与1之间)、混合二维材料，例如氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物所形成。二维材料层326的厚度可约为10埃至50埃。在一些实施例中，具有相同或不同二维材料的多个二维材料层是形成在栅极堆叠320、层间介电层302及导电插塞304、306、308上。
金属间介电(inter-metal dielectric，IMD)层328是形成在二维材料层326上。在一些实施例中，金属间介电层328是由介电材料所形成，例如氧化硅或其他合适的低介电常数材料。做为金属间介电层328的低介电常数材料的具体例可包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。如图3A至图3C所示，金属间介电层328也包含导电介层窗330、332，其是穿透以接触二维材料层326。导电介层窗330、332可由金、银、铜、钨、铝、镍、前述的组合、金属合金或类似物所形成。
图3D是如图3A所示的集成半导体装置300的等效电路图。在图3D中，反向器的电路是被绘示，其中上拉晶体管T1及下拉晶体管T2是连续地耦合在电源(其是可提供电源电压VDD)、互补电源(其是可提供接地电压VGND)、输入节点(其是配置以接收输入电压VIN)及输出节点(其是配置以提供输出电压VOUT)之间。上拉晶体管T1及下拉晶体管T2可分别为p型场效晶体管及n型场效晶体管。上拉晶体管T1及下拉晶体管T2的源极是分别对应至图3A所示的集成半导体装置的上部半导体装置300B及下部半导体装置300A。申言之，上拉晶体管T1的源极、漏极及栅极是分别对应至导电介层窗332、导电插塞306及其中一个栅极堆叠320，而下拉晶体管T2的源极、漏极及栅极是分别对应至下部半导体装置300A的源极/漏极区域334、336以及栅极318，且输入节点及输出节点是分别地对应至导电插塞308、312。
图3E至图3J是绘示根据本揭露一些实施例的形成图3A的集成半导体装置300的各中间阶段中沿着B2-B2’线的剖面视图。
请参阅图3E，开口302A、302B、302C是形成在下部半导体装置300A之上的层间介电层302内。在一些实施例中，如图3E所示，下部半导体装置300A可包含鳍式场效晶体管结构，且是类似于图2A所示的下部半导体装置200A，且下部半导体装置300A的形成的中间阶段是相似于图2J至图2N所示者，因此，下部半导体装置300A的细节便不在此重复描述。在各种实施例中，下部半导体装置300A可包含平面场效晶体管、环绕式栅极晶体管结构及/或其他合适的结构。
如图3E所示，开口302A、302B是形成为穿透层间介电层302，以分别暴露出在下部半导体装置300A内的导电插塞310、312，而开口302C是形成为穿透下部半导体装置300A的层间介电层302、层间介电层314及蚀刻中止层316，以暴露出下部半导体装置300A的栅极318。在一些实施例中，举例而言，光阻层(图未绘示)是沉积在层间介电层302上，接着光阻层通过光微影技术被图案化，以形成光阻罩幕。在形成光阻罩幕之后，可进行蚀刻制程(例如非等向性干式蚀刻制程或相似者)，以蚀刻层间介电层302垂直地未被光阻罩幕所覆盖的部分，借以形成开口302A、302B。然后，可进一步地进行一或多个蚀刻制程(例如非等向性干式蚀刻制程或相似者)，以蚀刻层间介电层314及蚀刻中止层316垂直地未被光阻罩幕所覆盖的部分，借以形成开口302C。接着，可通过进行例如灰化制程及/或湿式蚀刻制程，以移除光阻罩幕。
请参阅图3F，导电插塞304、306、308是形成为分别填充开口302A、302B、302C，以分别接触导电插塞310、312及栅极318。导电插塞304、306、308可由金、银、铜、钨、铝、镍、前述的组合、金属合金或类似物所形成，且可通过进行例如原子层沉积、化学气相沉积、物理气相沉积或类似的制程而形成。进一步地，可进行平坦化制程，例如化学机械研磨，以移除导电插塞304、306、308在层间介电层302的顶表面之上的部分。在一些实施例中，导电插塞304、306、308还包含衬层(图未绘示)，其是形成为与开口的底部及侧壁共形，且是类似于图2N所示的衬层256，故衬层的细节不在此做赘述。
请参阅图3G，金属层322是形成在层间介电层302及导电插塞304、306、308上，接着介电层324是形成在金属层322上。金属层322的厚度可约为10nm至20nm，且可由金属材料(例如：钛、钽、钨、铝、钼、铂及铪)、金属硅化物材料(例如：硅化钛、硅化钽、硅化钨、硅化钼、硅化镍及硅化钴)、金属氮化物材料(例如：氮化钛、氮化钽、氮化钨、氮化钼、氮化镍及氮化钴)、硅化金属氮化物(例如：氮化钛硅、氮化钽硅及氮化钨硅)、耐火金属、多晶硅、前述的组合及/或其他合适的材料所形成。金属层322可通过进行制程而形成，例如物理气相沉积法、原子层沉积法、电化学电镀法、无电式电镀法、前述的组合或其他合适的制程。
介电层324可由介电材料所形成，例如但不限于氧化硅、氮化硅、氮氧化硅、氧化铪、氧化钽、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、硅化锆、铝化锆、氧化锡、氧化锆、氧化钛、氧化铝、高介电常数材料、前述的组合及/或其他合适的材料。介电层324的厚度可约为1nm至5nm，且可通过进行制程而形成，例如化学气相沉积、电浆辅助化学气相沉积法、高密度电浆化学气相沉积、原子层沉积法、旋转涂布、溅镀、前述的组合或其他合适的制程。
请参阅图3H，金属层322及介电层324是被图案化，以形成栅极堆叠320。在一些实施例中，光阻层(图未绘示)是沉积在介电层324上，接着光阻层通过光微影技术被图案化，以形成光阻罩幕。栅极堆叠320可通过进行一或多个蚀刻制程而被形成。举例而言，介电层324可通过进行湿式蚀刻制程而被蚀刻，然后金属层322可通过进行干式蚀刻制程而被蚀刻。然而，其他合适的蚀刻制程可被用以蚀刻金属层322及/或介电层324。接着，可通过进行例如灰化制程及/或湿式蚀刻制程，以移除光阻罩幕。在此例示中，如图3H所示，在光阻罩幕被移除之后，导电插塞304及导电插塞306的顶表面是被暴露，而导电插塞308是被其中一个栅极堆叠320所覆盖。
请参阅图3I，二维材料层326是形成在栅极堆叠320、层间介电层302及导电插塞304、306、308上。在一些实施例中，二维材料层326为单层，且是由例如石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨、硒化钨、硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓、硒化铟及/或其类似物所形成。在另一些实施例中，二维材料层206是由三元二维材料，例如WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4(其中x是介于0与1之间)、混合二维材料，例如氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物所形成。二维材料层326的厚度可约为10埃至50埃，且可通过进行制程所形成，例如化学气相沉积、原子层沉积法、低热蒸镀、注射、晶圆尺度转印，或其他适于在温度低于400℃下操作的制程，其是取决于选择用于二维材料层326的材料。在一些实施例中，具有相同或不同二维材料的多个二维材料层是形成在栅极堆叠320、层间介电层302及导电插塞304、306、308上。
请参阅图3J，金属间介电层328是形成在二维材料层326上。在一些实施例中，金属间介电层328是由介电材料所形成，例如氧化硅或其他合适的低介电常数材料。做为金属间介电层328的低介电常数材料的具体例可包含但不限于氟掺杂硅玻璃、碳掺杂氧化硅、非晶相氟化碳、聚对二甲苯、苯并环丁烯或聚酰亚胺。金属间介电层328可通过进行例如化学气相沉积、物理气相沉积法、原子层沉积法、旋转涂布或其他合适的制程而形成。进一步地，可进行平坦化制程，例如化学机械研磨，以平坦化金属间介电层328。
如图3J所示，金属间介电层328也包含导电介层窗330、导电介层窗332，其是穿透以接触二维材料层326。在一些实施例中，举例而言，光阻层(图未绘示)是沉积在金属间介电层328上，接着光阻层通过光微影技术被图案化，以形成光阻罩幕。在形成光阻罩幕之后，可进行一或多个蚀刻制程(例如非等向性干式蚀刻制程或相似者)，以蚀刻金属间介电层328垂直地未被光阻罩幕所覆盖的部分，借以形成开口在金属间介电层328内。接着，可通过进行例如灰化制程及/或湿式蚀刻制程，以移除光阻罩幕。
导电介层窗330、332是形成为分别填充金属间介电层328内的开口。导电介层窗330、332可由金、银、铜、钨、铝、镍、前述的组合、金属合金或类似物所形成，且可通过进行例如原子层沉积、化学气相沉积、物理气相沉积或类似的制程而形成。进一步地，可进行平坦化制程，例如化学机械研磨，以移除导电介层窗330、332在金属间介电层328的顶表面之上的部分。
根据一些实施例，集成半导体装置包含第一半导体装置、层间介电层以及第二半导体装置。第一半导体装置具有第一晶体管结构。层间介电层是在第一半导体装置上。层间介电层的厚度实质为10nm至100nm。第二半导体装置具有第二晶体管结构，且具有形成在层间介电层上的二维材料层，其是做为第二晶体管结构的通道层。
在一些实施例中，二维材料层包含石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨或硒化钨。
在一些实施例中，二维材料层包含硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓或硒化铟。
在一些实施例中，二维材料层包含三元二维材料及混合二维材料的至少一者。
在一些实施例中，三元二维材料包含WSe2(1-x)Te2x、Ta2NiS5或ZnIn2S4，其中x是介于0与1之间。
在一些实施例中，混合二维材料层包含氮化硼及石墨烯的组成物或硫化钼及红荧烯的组成物。
在一些实施例中，二维材料层的厚度实质为10埃至50埃。
在一些实施例中，第二晶体管结构还包含源极电极、漏极电极、栅极介电层及栅极电极。源极电极及漏极电极是分别在二维材料层的相对两端。栅极介电层是在二维材料层、源极电极及漏极电极上。栅极电极是在栅极介电层上，并侧向地介于源极电极及漏极电极之间。
在一些实施例中，第二半导体装置还包含栅极堆叠、第一导电插塞、第二导电插塞及导电介层窗。栅极堆叠是在层间介电层上，且是被二维材料层所环绕。第一导电插塞是穿过层间介电层，并接触二维材料层及第一晶体管结构的栅极。第二导电插塞是穿过层间介电层，并接触二维材料层及第一晶体管结构的漏极。导电介层窗接触二维材料层。第二导电插塞及导电介层窗是分别侧向地在栅极堆叠的相对两侧。
在一些实施例中，第一晶体管结构为鳍式场效晶体管结构、环绕式栅极场效晶体管结构或平面场效晶体管结构。
根据特定实施例，一种集成半导体装置的制造方法包含以下步骤。提供具有第一晶体管结构的半导体装置。在半导体装置上形成层间介电层。层间介电层的厚度是实质为10nm至100nm。在层间介电层上形成二维材料层。图案化二维材料层，以形成第二晶体管结构的通道层。在被图案化的二维材料层的相对两端分别形成第二晶体管结构的源极电极及漏极电极。在被图案化的二维材料层、源极电极及漏极电极上形成第二晶体管结构的栅极介电层。在栅极介电层上形成第二晶体管结构的栅极电极，且第二晶体管结构的栅极电极是侧向地介于源极电极及漏极电极之间。
在一些实施例中，二维材料层是由石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨或硒化钨所形成。
在一些实施例中，二维材料层是由硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓或硒化铟所形成。
在一些实施例中，二维材料层是由三元二维材料及混合二维材料的至少一者所形成。
在一些实施例中，二维材料层是形成为具有实质为10埃至50埃的厚度。
根据一些实施例，一种集成半导体装置的制造方法包含以下步骤。提供具有第一晶体管结构的半导体装置。在半导体装置上形成层间介电层。层间介电层的厚度是实质为10nm至100nm。形成第一导电插塞穿过层间介电层，并接触第一晶体管结构的栅极。形成第二导电插塞穿过层间介电层，并接触第一晶体管结构的漏极。在层间介电层上形成栅极堆叠，并接触第一导电插塞。在栅极堆叠及层间介电层上形成二维材料层，并接触第二导电插塞，且二维材料层是做为第二晶体管结构的通道层。形成导电介层窗，并接触二维材料层。第二导电插塞及导电介层窗是分别侧向地在相对于栅极堆叠的相对两侧。
在一些实施例中，二维材料层是由石墨烯、铋、六方氮化硼、硫化钼、硒化钼、硫化钨或硒化钨所形成。
在一些实施例中，二维材料层是由硒化锡、硫化铂、硒化铂、硫化镉、硒化镉、硒化钯、硫化铼、硒化钛、碲化钼、碲化钨、碘化铅、磷化硼、硒化镓或硒化铟所形成。
在一些实施例中，二维材料层是由三元二维材料及混合二维材料的至少一者所形成。
在一些实施例中，二维材料层是形成为具有实质为10埃至50埃的厚度。
上述摘要许多实施例的特征，因此本领域具有通常知识者可更了解本揭露的态样。本领域具有通常知识者应理解利用本揭露为基础可以设计或修饰其他制程和结构以实现和所述实施例相同的目的及/或达成相同优势。本领域具有通常知识者也应了解与此同等的架构并没有偏离本揭露的精神和范围，且可以在不偏离本揭露的精神和范围下做出各种变化、交换和取代。

Claims (1)

1.一种集成半导体装置，其特征在于，包含：
一第一半导体装置，具有一第一晶体管结构；
一层间介电层，在该第一半导体装置上，其中该层间介电层的一厚度实质为10nm至100nm；以及
一第二半导体装置，具有一第二晶体管结构，其中该第二半导体装置具有一二维材料层，且该二维材料层是形成在该层间介电层上并作为该第二晶体管结构的一通道层。
CN201811295405.7A 2017-11-30 2018-11-01 集成半导体装置 Pending CN109860170A (zh)

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