CN108022841A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN108022841A
CN108022841A CN201610925896.3A CN201610925896A CN108022841A CN 108022841 A CN108022841 A CN 108022841A CN 201610925896 A CN201610925896 A CN 201610925896A CN 108022841 A CN108022841 A CN 108022841A
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semiconductor fin
isolated area
substrate
method described
ion implanting
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CN108022841B (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to EP17198882.7A priority patent/EP3319128A1/en
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Abstract

本发明公开了一种半导体装置的制造方法，涉及半导体技术领域。所述方法包括：提供衬底结构，所述衬底结构包括：衬底、在所述衬底上的半导体鳍片、以及在所述半导体鳍片两侧的隔离区，其中，所述半导体鳍片的顶表面与所述隔离区的顶表面基本齐平；执行沟道停止离子注入，以在所述半导体鳍片和所述隔离区中形成杂质区；对所述隔离区进行回刻，以露出所述半导体鳍片的一部分；执行退火工艺，以激活所述杂质区中的杂质。本发明中，由于在对隔离区进行回刻后才进行退火，从而可以使得一部分杂质扩散到隔离区和半导体鳍片的外部，从而减少了扩散到沟道中的杂质，改善了器件性能。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置的制造方法。
背景技术
随着金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor FieldEffect Transistor，MOSFET)关键尺寸的缩小，短沟道效应(Short Channel Effect，SCE)成为影响器件性能一个至关重要的因素。鳍式场效应晶体管(Fin Field EffectTransistor，FinFET)具有良好的栅控能力，能够有效地抑制短沟道效应。因此，在更小尺寸的半导体元件设计中通常采用FinFET器件。
但是，随着器件尺寸的减小，更容易出现穿通效应(punch through effect)。为了抑制穿通效应，可以在鳍片的底部进行沟道停止离子注入(channel stop IMP)。然而，发明人发现，在进行沟道停止离子注入后的退火工艺后，通过沟道停止离子注入掺入的杂质很容易扩散到上面的沟道中，从而影响器件的性能。
发明内容
本公开的一个目的在于减少扩散到沟道中的通过沟道停止离子注入所掺入的杂质。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括：衬底、在所述衬底上的半导体鳍片、以及在所述半导体鳍片两侧的隔离区，其中，所述半导体鳍片的顶表面与所述隔离区的顶表面基本齐平；执行沟道停止离子注入，以在所述半导体鳍片和所述隔离区中形成杂质区；对所述隔离区进行回刻，以露出所述半导体鳍片的一部分；执行退火工艺，以激活所述杂质区中的杂质。
在一个实施例中，所述提供衬底结构的步骤包括：提供初始衬底；在所述初始衬底上形成图案化的硬掩模；以所述硬掩模为掩膜对所述初始衬底进行刻蚀，从而形成所述衬底、所述半导体鳍片和在所述半导体鳍片两侧的凹陷；沉积隔离材料以填充所述凹陷并覆盖所述硬掩模；对所述隔离材料进行平坦化，以使得剩余的隔离材料的顶表面与所述硬掩模的顶表面基本齐平；对剩余的隔离材料进行回刻蚀，以露出所述硬掩膜；去除所述硬掩模，从而形成所述衬底结构。
在一个实施例中，在沉积隔离材料之前，还包括：在所述衬底和所述半导体鳍片的表面形成衬垫层。
在一个实施例中，所述对所述隔离区进行回刻包括：去除所述隔离区的一部分；去除露出的衬垫层，以露出所述半导体鳍片的一部分。
在一个实施例中，对所述隔离区进行回刻后剩余的隔离区的上表面高于所述杂质区的上表面。
在一个实施例中，在执行沟道停止离子注入之前，还包括：在所述衬底结构上沉积硅的氧化物层。
在一个实施例中，所述衬底结构包括在所述衬底上的多个半导体鳍片。
在一个实施例中，所述执行沟道停止离子注入包括：对所述半导体鳍片和所述隔离区进行P型离子注入。
在一个实施例中，所述P型离子注入所注入的离子包括硼离子或二氟化硼离子。
在一个实施例中，所述执行沟道停止离子注入包括：对所述半导体鳍片和所述隔离区进行N型离子注入。
在一个实施例中，所述N型离子注入所注入的离子包括砷离子或磷离子。
在一个实施例中，所述衬底包括阱区，所述阱区与所述杂质区具有相同的导电类型，所述阱区的掺杂浓度小于所述杂质区的掺杂浓度。
本公开提供的半导体装置的制造方法中，由于在对隔离区进行回刻后才进行退火，从而可以使得一部分杂质扩散到隔离区和半导体鳍片的外部，从而减少了扩散到沟道中的杂质，改善了器件性能。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的流程图；
图2示出了根据本公开一个实施例的衬底结构的示意截面图；
图3A-图3F示出了根据本公开一个实施例的形成图2的衬底结构的各个阶段的示意截面图；
图4示出了根据本公开的一个实施例的半导体装置的制造方法的一个阶段的示意截面图；
图5示出了根据本公开的一个实施例的半导体装置的制造方法的一个阶段的示意截面图；
图6示出了根据本公开的一个实施例的半导体装置的制造方法的一个阶段的示意截面图；
图7示出了现有技术中退火后杂质的扩散情况的示意图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是根据本公开一个实施例的半导体装置的制造方法的流程图。如图1所示，在步骤102，提供衬底结构。
图2示出了根据本公开一个实施例的衬底结构的示意截面图。如图2所示，该衬底结构包括衬底201、在衬底201上的一个或多个半导体鳍片202、以及在半导体鳍片202两侧的隔离区203。半导体鳍片202的顶表面与隔离区203的顶表面基本齐平。
需要说明的是，在本文中，“基本齐平”是指在半导体工艺偏差范围内的齐平。
图3A-图3F示出了根据本公开一个实施例的形成图2的衬底结构的各个阶段的示意截面图。
如图3A所示，提供初始衬底301，在初始衬底301上形成图案化的硬掩模302。这里，初始衬底301例如可以是硅(Si)、锗(Ge)或其他元素半导体，或者也可以是砷化镓(GaAs)等化合物半导体。硬掩模302例如可以是硅的氮化物、硅的氧化物、硅的氮氧化物等等。然而，本公开并不限于此。
如图3B所示，以硬掩模302为掩模对初始衬底301进行刻蚀，例如干法刻蚀，以形成衬底201、位于衬底201上的半导体鳍片202和在半导体鳍片两侧的凹陷203。应理解，虽然图3B以实线区分开了衬底201和半导体鳍片202，但是衬底201和半导体鳍片202均由初始衬底301形成而来。在其他的实施例中，也可以通过其他的方式来形成衬底201和在衬底201上的半导体鳍片202。
如图3C所示，沉积隔离材料304以填充凹陷203并覆盖硬掩模302。例如，可以通过诸如流式化学气相沉积(Flowable Chemical Vapour Deposition,FCVD)的化学气相沉积(CVD)技术等沉积隔离材料304(例如电介质材料层)以填充凹陷203并覆盖各个半导体鳍片202和硬掩模302。可选地，在沉积隔离材料304之前，还可以在衬底201和半导体鳍片202的表面形成衬垫层(例如，通过热氧化形成氧化硅层，图中未示出)，衬垫层可以修复在刻蚀初始衬底301时对半导体鳍片202造成的表面损伤。这里，半导体鳍片202的表面的衬垫层的一部分可能会在随后对隔离材料进行的回刻工艺中被去除。
如图3D所示，对隔离材料304进行平坦化，例如化学机械抛光(CMP)，以使得剩余的隔离材料304的顶表面与硬掩模302的顶表面基本齐平。
如图3E所示，对剩余的隔离材料304进行回刻蚀，以露出硬掩膜302。
如图3F所示，去除硬掩模302，例如可以通过干法刻蚀去除硬掩模302，从而形成衬底结构。这里，剩余的隔离材料304即为隔离区203。
应理解，也可以根据其他方式来形成上述衬底结构，在此不再赘述。
回到图1，在步骤104，执行沟道停止离子注入，以在半导体鳍片202和隔离区203中形成杂质区401，如图4所示。优选地，在执行沟道停止离子注入之前，还可以在图2所示的衬底结构上沉积硅的氧化物层(未示出)，以减小沟道停止离子注入对半导体鳍片202的损伤。
在一个实施例中，在执行沟道停止离子注入时可以对半导体鳍片202和隔离区203进行离子注入，在隔离区203中所注入的杂质的一部分通过横向扩散可以扩散到半导体鳍片202中，半导体鳍片202中的杂质区401可以作为沟道停止层。对于N沟道金属氧化物半导体(Negative Channel Metal Oxide Semiconductor，NMOS)器件来说，可以对半导体鳍片202和隔离区203进行P型离子注入，以在半导体鳍片202和隔离区203中形成第一杂质区。示例性地，P型离子注入所注入的离子可以包括硼离子或二氟化硼离子等。对于P沟道金属氧化物半导体(Positive Channel Metal Oxide Semiconductor，PMOS)器件来说，可以对半导体鳍片202和隔离区203进行N型离子注入，以在半导体鳍片202和隔离区203中形成第二杂质区。示例性地，N型离子注入所注入的离子可以包括砷离子或磷离子等。另外，在半导体装置同时包括NMOS器件和PMOS器件的情况下，可以对NMOS器件中的半导体鳍片202和隔离区203进行P型离子注入，对PMOS器件中的半导体鳍片202和隔离区203进行N型离子注入。
另外，在某些实施例中，衬底201可以包括阱区，阱区与杂质区401具有相同的导电类型，并且优选地，阱区的掺杂浓度小于杂质区401的掺杂浓度。例如，阱区可以是P阱，P阱的掺杂浓度优选小于第一杂质区的掺杂浓度。
之后，在步骤106，对隔离区203进行回刻，以露出半导体鳍片202的一部分，如图5所示。在一个实施例中，对隔离区203进行回刻后剩余的隔离区203的上表面高于杂质区401的上表面。在半导体鳍片202的表面具有衬垫层的情况下，对隔离区203进行回刻的步骤可以包括：首先去除隔离区203的一部分，以露出一部分衬垫层；然后去除露出的衬垫层，以露出半导体鳍片202的一部分。
之后，在步骤108，执行退火工艺，以激活杂质区301中的杂质，如图6所示。
图7示出了现有技术中在退火后通过沟道停止离子注入掺入的杂质的扩散情况的示意图。如图7所示，杂质区401中的杂质会扩散到上面的沟道中，从而影响器件的性能。
本公开提供的制造方法由于在对隔离区203进行回刻后才进行退火，从而可以使得一部分杂质扩散到隔离区203和半导体鳍片202的外部，如图6所示，从而减少了扩散到沟道中的杂质，改善了器件性能。
之后，可以进行后续的工艺，例如形成栅极、源极和漏极等。由于后续工艺并非本公开的重点，因此，在此不再做详细介绍。
至此，已经详细描述了根据本公开实施例的半导体装置的制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (12)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括：衬底、在所述衬底上的半导体鳍片、以及在所述半导体鳍片两侧的隔离区，其中，所述半导体鳍片的顶表面与所述隔离区的顶表面基本齐平；
执行沟道停止离子注入，以在所述半导体鳍片和所述隔离区中形成杂质区；
对所述隔离区进行回刻，以露出所述半导体鳍片的一部分；
执行退火工艺，以激活所述杂质区中的杂质。
2.根据权利要求1所述的方法，其特征在于，所述提供衬底结构的步骤包括：
提供初始衬底；
在所述初始衬底上形成图案化的硬掩模；
以所述硬掩模为掩膜对所述初始衬底进行刻蚀，从而形成所述衬底、所述半导体鳍片和在所述半导体鳍片两侧的凹陷；
沉积隔离材料以填充所述凹陷并覆盖所述硬掩模；
对所述隔离材料进行平坦化，以使得剩余的隔离材料的顶表面与所述硬掩模的顶表面基本齐平；
对剩余的隔离材料进行回刻蚀，以露出所述硬掩膜；
去除所述硬掩模，从而形成所述衬底结构。
3.根据权利要求2所述的方法，其特征在于，在沉积隔离材料之前，还包括：
在所述衬底和所述半导体鳍片的表面形成衬垫层。
4.根据权利要求3所述的方法，其特征在于，所述对所述隔离区进行回刻包括：
去除所述隔离区的一部分；
去除露出的衬垫层，以露出所述半导体鳍片的一部分。
5.根据权利要求1所述的方法，其特征在于，对所述隔离区进行回刻后剩余的隔离区的上表面高于所述杂质区的上表面。
6.根据权利要求1所述的方法，其特征在于，在执行沟道停止离子注入之前，还包括：
在所述衬底结构上沉积硅的氧化物层。
7.根据权利要求1所述的方法，其特征在于，所述衬底结构包括在所述衬底上的多个半导体鳍片。
8.根据权利要求1所述的方法，其特征在于，所述执行沟道停止离子注入包括：
对所述半导体鳍片和所述隔离区进行P型离子注入。
9.根据权利要求8所述的方法，其特征在于，
所述P型离子注入所注入的离子包括硼离子或二氟化硼离子。
10.根据权利要求1所述的方法，其特征在于，所述执行沟道停止离子注入包括：
对所述半导体鳍片和所述隔离区进行N型离子注入。
11.根据权利要求10所述的方法，其特征在于，
所述N型离子注入所注入的离子包括砷离子或磷离子。
12.根据权利要求1所述的方法，其特征在于，所述衬底包括阱区，所述阱区与所述杂质区具有相同的导电类型，所述阱区的掺杂浓度小于所述杂质区的掺杂浓度。
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