CN105304494B - 一种形成nmos晶体管装置的锗通道层、nmos晶体管装置和cmos装置的方法 - Google Patents

一种形成nmos晶体管装置的锗通道层、nmos晶体管装置和cmos装置的方法 Download PDF

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CN105304494B
CN105304494B CN201510435539.4A CN201510435539A CN105304494B CN 105304494 B CN105304494 B CN 105304494B CN 201510435539 A CN201510435539 A CN 201510435539A CN 105304494 B CN105304494 B CN 105304494B
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groove
layer
seed layer
side wall
relaxed buffer
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CN105304494A (zh
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J·米塔德
R·鲁
L·维特斯
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

一种形成用于NMOS晶体管装置的锗通道层的方法，该方法包括：a.提供具有侧壁的沟槽，所述侧壁由介电材料结构限定并邻接硅基材的表面；b.在所述表面上的所述沟槽中种植晶种层，所述晶种层具有前表面，所述前表面包含具有(111)取向的分面；c.在所述沟槽中的所述晶种层上种植应变弛豫缓冲层，所述应变弛豫缓冲层包含硅锗；d.在所述应变弛豫缓冲层上种植包含锗(Ge)的通道层；以及相关NMOS晶体管装置和CMOS装置。

Description

一种形成NMOS晶体管装置的锗通道层、NMOS晶体管装置和 CMOS装置的方法
技术领域
本发明涉及制造晶体管装置(优选NMOS晶体管装置)的锗通道层和相关装置的方法。
背景技术
在CMOS生产中，通常需要使单一基材上具有各NOMS和PMOS晶体管装置的拉伸应变/无应变的和压缩应变的通道结构的组合。
现有技术方案是针对拉伸和压缩应变的通道结构(通道层)提供不同的通道材料。
使用诸如Ge基或III-V基的通道材料带来了特定问题。在先进技术节点上，迫切地需要与常规应变和无应变Si通道参照装置相比具有较高迁移率的通道材料，旨在进一步加强装置性能。
因此，锗基通道材料的营业用被认为是现有技术水平。
在Yang,Appl.Phys.Lett.91,102103(2007),(111)中，Ge表面性质被报道为：与侧壁(110)或顶部(100)Ge表面相比，在任何通道应变条件下都具有改进的电子传递。
需要允许制造在基材上使用相同通道材料(例如锗基通道材料)的拉伸应变和压缩应变的通道结构的方法。
其中，一大挑战是生产Ge n-通道装置。实际上，需要内在电子迁移率高的低缺陷弛豫Ge翅片(low defective relaxed Ge fins)。在常规平面Ge nFET(例如具有(100)-Ge作为主要载体传送平面)中，已广泛报道了使用标准栅叠的迁移率较差。作为最近期的示例，C.H.Lee等在VLSI 2014，technology symposium，第144页(技术研讨会(technologysymposium))中报道了300cm2/V.s的迁移率值，而在(111)-取向表面(平面)上迁移率可超过400cm2/V.s。
发明内容
本发明的目的是提供制造NMOS晶体管装置或NMOS晶体管装置的锗通道层的方法，通过该方法生产了低缺陷(低于1E8/cm3)弛豫Ge翅片结构，其还具有高载体迁移率(对于孔，高于50cm2/V.s，且对于电子，高于100cm2/V.s)。
根据本发明，使用显示第一独立权利要求的技术特性的方法实现该目的。
根据本发明的第一方面，公开了形成NMOS晶体管装置的锗通道层的方法，该方法包括：
a.提供具有侧壁的沟槽(第一沟槽)，该侧壁由介电材料结构限定并邻接硅基材的表面，该沟槽优选具有(001)取向；
b.在表面上的沟槽中种植晶种层，所述晶种层具有前表面，该前表面包含具有(111)取向的分面(facet)；
c.在沟槽中的晶种层上种植应变弛豫缓冲层，该应变弛豫缓冲层包含硅锗；
d.在应变弛豫缓冲层上种植包含锗(Ge)的通道层。
一个优势在于：晶种层在随后的应变弛豫缓冲层沉积期间促进形成具有(111)分面的前表面。优选地，基材是包含STI(浅沟槽隔离)的基材，且介电材料结构包含STI结构，后者例如包含二氧化硅。然后，在包含STI的基材中提供沟槽可包括对位于各相邻STI结构对之间的相应硅突出物开槽。
根据优选的实施方式，晶种层的顶表面不是仅由(111)-分面组成。晶种层的特定分面取决于沟槽宽度。晶种层的厚度(优选在5-60nm的范围内)也可确定晶种层的最终分面性质。对于窄沟槽(宽度小于100nm，优选小于50nm，更优选小于30nm)，仅(111)分面可在晶种层的前表面上形成。对于窄和宽沟槽(后者的宽度大于100nm)，顶表面的边缘会成为(111)-分面化，而在沟槽的两个纵向侧壁之间的中心位置或中心部分附近，该表面可具有另一种取向，例如仍具有(001)取向，尤其是对于宽沟槽而言。
应理解，(111)分面形成的驱动力是介电材料和SiGe或Ge半导体层之间的高界面能。可通过例如提高晶种层中的Ge含量或通过使用100％Ge晶种层(其导致种植的原子的表面扩散性提高)来促进(111)分面形成。或者，可通过提供足够的动能来促进(111)分面形成，所述动能也允许表面原子从介电层离开。这可以通过在充分高温(例如350-900℃的范围内)下种植晶种层，或者通过在晶种层和SiGe SRB之间施加种植阻断来实现，后者可与其他分面形成刺激方法联用。分面形成开始的关键温度随着Ge含量的增加而降低，并且如果种植被阻断，则更低。该关键温度还可取决于介电(沟槽侧壁)材料。
根据优选的实施方式，该方法还包括在种植应变弛豫缓冲层之前施用温度步骤，优选在惰性气体气氛中。例如在N2环境中，该温度优选高于或等于350℃，更优选高于或等于400℃。例如在H2环境中，该温度优选高于或等于400℃，更优选高于或等于450℃。
根据优选的实施方式，该晶种层是锗基晶种层。其可包含SiGe或由SiGe组成，更优选地其可包含Ge或由Ge组成。
根据优选的实施方式，该应变弛豫缓冲层是SiGe基的。其上(前)表面将包含具有(111)取向的分面。其前表面主要具有(111)取向的表面。至少SRB层的前表面的边缘区域具有(111)取向。该SRB层的锗含量优选在50-90％，更优选为70-80％。优选地，该SRB是完全应变弛豫的。
根据优选的实施方式，该方法还包括
a.提供具有侧壁的第二沟槽，该侧壁由介电材料结构限定，并邻接限定该第二沟槽的底表面的硅基材表面；
b.在第一沟槽和第二沟槽中种植应变弛豫缓冲层，优选同时种植(此时，SRB模板(对于nFinFET是(111)且对于pFinFET是矩形)可供使用以种植p和nFinFET的通道沉积物)；
c.在第一沟槽和第二沟槽中的应变弛豫缓冲层上种植包含锗的通道层，优选同时种植。
根据优选的实施方式，该方法还包括提供封盖层，从而盖住晶种层，例如通过诸如沉积Si基层的原位工艺，之后提供第二沟槽(在STI结构之间蚀刻第二硅突起物)。该封盖层可用作针对CMOS装置的进一步加工期间所使用的化学处理的保护。
该方法提供了同时形成单一SRB层和NOMS与PMOS装置共有的通道层的机会。
根据优选的实施方式，使硅沟槽(例如NMOS和PMOS沟槽)凹陷从而控制各翅片结构(包含Ge晶种、SRB层和通道层)的最终厚度。
根据优选的实施方式，该方法包括提供沟槽且第二沟槽包括STI基材上硅突起物的凹陷蚀刻，且在表面的沟槽(第一沟槽)中种植晶种层之后提供第二沟槽。
根据本发明的第二方面，公开了一种NMOS晶体管装置，其包括：
-具有侧壁的沟槽，该侧壁由介电材料结构限定并邻接硅基材的表面；
-表面上沟槽中的晶种层，该晶种层具有前表面，该前表面包含具有(111)取向的分面；
-晶种层上沟槽中的应变弛豫缓冲层，该应变弛豫缓冲层包含硅锗；
-应变弛豫缓冲层上包含锗(Ge)的通道层，所述通道层在所述沟槽中具有(111)取向。
根据优选的实施方式，该晶种层是SiGe或锗晶种层。
根据本发明的第三方面，公开了一种CMOS装置，其包含第二方面的实施方式中任一项所述的NMOS晶体管装置，且还包含PMOS装置，该PMOS装置包含
-具有侧壁的第二沟槽，该侧壁由介电材料结构限定并邻接限定第二沟槽底表面的硅基材的表面；
-第二沟槽中的应变弛豫缓冲层；
-第二沟槽中应变弛豫缓冲层上的包含锗的通道层，该通道层具有(110)侧壁取向和(001)顶表面取向。
本发明的各方面提供了若干优势。在外延种植中，一个优势在于，在翅片加工终末，使用常规和现有的CMOSFET平台生产(111)分面化的Ge通道。此外，在使用Ge晶种层概念时，优选对于nFinFET，例如可以保持pFinFET的翅片形状(例如对于pFinFET，主要是(110)的侧壁)。pFINFET和nFINFET的最终通道材料的形状可以是不同的并可被有利地使用以使装置性质最大化(例如增加迁移率)。
出于本发明的目的，每当限定范围时，其旨在公开封闭、开放和两个半开放形式的这些范围。即使术语“之间”被用于限定这类范围的上下文中时，也意味着公开了所有这些选项。
本领域技术人员应理解，针对本发明的一个方面所述的特征和优势加上必要的变更也可适用于本发明的其他方面且反之亦然，因此其也被认为是已公开的。
附图说明
通过以下说明书和附图进一步描述本发明。
图1显示现有技术水平的FINFET型晶体管装置的装置设计。
图2显示现有技术水平的图1所示装置的制作方案。
图3显示本发明的一个优选实施方式。
图4表示根据本发明的实施方式的晶体管结构的组件的TEM图像。
图5显示可能的利用晶种层概念的CMOS兼容工艺流程。分开限定nFINFET或pFINFET。
图6显示可能的利用晶种层概念的CMOS兼容工艺流程。nFINFET或pFINFET具有共同的SRB和Ge层。
优选实施方式的详述
将就具体实施方式并参照某些附图对本发明进行描述，但本发明并不受此限制，仅由权利要求书限定。描述的附图仅是说明性的且是非限制性的。在附图中，一些元素的尺寸可能被夸大且未按尺度绘画以用于说明目的。各尺寸和相对尺寸不必然对应于实践本发明的实际简化。
另外，在说明书以及权利要求书中，术语“第一”、“第二”和“第三”等仅仅是用来区别类似的元件，而不是用来描述次序或时间顺序。在适当的情况下，这些术语可互换，且本发明的实施方式可以如本文所述和所示以外的其它顺序操作。
此外，在说明书和权利要求书中，术语顶、底、之上、之下等用于描述目的，而不一定用于描述相对位置。如此使用的术语在适当条件下是可互换的且本发明的实施方式可以不同于本文所描述或显示的取向进行。
此外，虽然被称为“优选的”，但应将多个实施方式理解为可以实施本发明的示例性方式，而不应理解为限制本发明的范围。
图1显示现有技术水平的FINFET型晶体管装置100的装置设计。应变Ge pFinFET结构包含应变(应力)锗(sGe)通道4，其外延种植于Si1-xGex应变弛豫缓冲层(SRB)3的顶部上，在源/漏区域上具有Si1-yGey(或Ge1-zSnz)应力源(stressor)5。在通道4的垂直上方提供包含栅叠60且由间隔结构61侧向限定的栅结构6。应力源5通过这些间隔结构61与栅叠60分离。Si1-xGex应变弛豫缓冲层3和通道层4种植于硅基材上基材表面上的浅沟槽隔离(STI)结构之间的凹陷的沟槽10内(在另一个视图中，在介电层的沟槽内)。该STI结构通常通过在硅圆片(wafer)或基材的主要表面中蚀刻沟槽来形成，且之后使用氧化物填充这些沟槽。通常，随后进行平整步骤以在氧化物填充的沟槽(STI结构)之间暴露硅突起物。随后使硅突起物在STI结构之间凹陷，并在所得沟槽内种植FIN结构。
图2显示图1所示的一个MOS晶体管(当宽度小于100nm时在本文中称作FinFET)的制作方案，其类似于本发明的实施方式中使用的方案。20-30nm高的sGe翅片4下方的Si0.25Ge0.75SRB层3一方面获得了应变增强的迁移率与量子-阱限制之间的良好平衡，另一方面使通道应变弛豫具有有限的风险。从300mm体Si FinFET(100)圆片(图2(a))开始，可使用翅片替换工艺来制作目标装置。通过湿HF处理和常规的磊晶前焙烤(pre-epi bake)(通常800℃下2分钟)除去天然氧化物后，可通过原位HCl蒸汽蚀刻使Si凹陷(图2(b))，生成邻接硅表面的且例如不在STI结构下(或不在STI结构/介电层的下表面下)延伸的沟槽10。可在凹陷的Si表面顶部选择性种植Si1-xGex SRB层3和sGe通道4(图2(c))。磊晶前焙烤、Si凹陷和SiGe/Ge通道再种植依次进行。或者，可使用湿化学蚀刻方法非原位进行Si凹陷。常规氧化物凹陷后出现应变Ge FIN结构(图2(d))，例如通过在基于HF的溶液中使用常规湿化学处理。
本发明的实施方式靶向类似的方法和结构。通过提供在沟槽中硅基材1表面上种植的晶种层7来设置NMOS区域中的锗通道层4的取向和相关特性，之后使(例如NMOS和PMOS共有的)SRB层3和通道层4外延生长。
在图3中，显示了本发明的优选实施方式。其中，使(111)-分面化的Ge通道(111)生长用于nFINFET(NMOS装置)，与pFINFET(PMOS装置)的应变Ge通道互补，优选同时生长。公开的方法可在NMOS和PMOS区域中的典型的rSiGe(SRB)层/应变Ge层生长(其通常用于pFET结构)前使用Ge作为NMOS区域中的晶种层。
图3显示本发明的实施方式所述的硅基材1上的CMOS装置的部份，其包括本发明的实施方式所述的NMOS装置。该CMOS装置包含含有硅基材的NMOS装置和PMOS装置。
该NMOS晶体管装置包含：
a.具有侧壁的沟槽10，该侧壁由介电材料结构2限定并邻接硅基材的表面；
b.所述表面上所述沟槽10中的晶种层7，所述晶种层7具有前表面，该前表面包含具有(111)取向的分面；
c.所述晶种层7上所述沟槽10中的应变弛豫缓冲层3，所述应变弛豫缓冲层3包含硅锗；
d.所述应变弛豫缓冲层3上包含锗的通道层4，所述通道层4在所述沟槽10中具有(111)取向。
该PMOS晶体管装置包含：
-具有侧壁的第二沟槽10，该侧壁由介电材料结构2限定并邻接限定第二沟槽10的底表面的硅基材表面；
-第二沟槽10中的应变弛豫缓冲层3；
-第二沟槽中应变弛豫缓冲层上的包含锗的通道层4，该通道层具有(110)侧壁取向和(001)顶表面取向。
优选的，该共有的通道层4在NMOS区域中包含拉伸应变或者是无应变的，且在PMOS区域中包含压缩应变。
图4是对类似样品摄取的高角度环形暗场成像扫描投射电子显微镜(HAADF-STEM)图像，其显示Si0.25Ge0.75SRB在组成中具有轻微不均匀性，这反映为靠近沟槽边缘对比沟槽中心的不同对比度。该轻微Ge不均匀性(由EDS(能量色散X射线光谱)确认为±3％)被解释为Si0.25Ge0.75选择性外延种植期间的分面形成。Ge掺入与种植的表面的表面取向以函数关系变化且在(111)表面上高于在(001)表面上。在Si0.25Ge0.75SRB之下，层7代表分面化的晶种层，其在该实施例中是纯Ge。顶层4是(111)分面化通道(此时是Ge)，其中发生载体传递。
图5描述限定翅片的工艺流程，其旨在制作CMOS晶体管。在选择性凹陷Si材料(优选在nFinFET侧面上)后，我们从种植正确分面化的(例如(111)-取向的)晶种层开始。如之前的实施方式中所述，在该阶段可进行额外的热处理。随后种植优先原位掺杂的SRB，随后种植通道层。通过例如氧化物层被覆nFinFET后，可进行其他装置的加工(例如该实施例中的pFinFET)。进行类似的加工顺序(Si凹陷、SRB和Ge种植)但此时不种植晶种层。在翅片加工的终末和在STI氧化物凹陷以暴露翅片后，制作(111)-Ge通道，同时该配套装置的形状是标准的(例如，优先顶部上(100)-Ge，侧壁上(111)-Ge)。
图6描述了限定CMOSFET兼容翅片的相对图5所述方法的替代性方法。其基于使用共有的SRB和通道层。在选择性凹陷Si材料(优选在nFinFET侧面上)后，我们从种植正确分面化的(例如(111)-取向的)晶种层开始。随后种植旨在保护晶种层对抗化学攻击的封盖层(优选在晶种层步骤后种植该封盖层以避免晶种层的表面污染)。随后，进行配套装置(该实施例中的pFinFET)的Si凹陷。完成种植无掺杂的SRB。可使用成熟建立的技术对n或pFINFET进行这些SRB层的选择性掺杂。在适当清洁SRB表面后，可在n和pFINFET中无掺杂种植通道层。

Claims (15)

1.一种形成晶体管装置的方法，所述方法包括：
提供具有侧壁的沟槽，所述侧壁由介电材料结构限定并邻接硅基材的表面；
在所述表面上的沟槽中种植晶种层，所述晶种层具有前表面，所述前表面包含具有(111)取向的分面；
在所述晶种层上且所述沟槽中种植应变弛豫缓冲(SRB)层，所述应变弛豫缓冲层包含硅锗(SiGe)；和
在所述应变弛豫缓冲层上种植应变锗通道层。
2.如权利要求1所述的方法，其还包括：在种植所述应变弛豫缓冲层之前施用温度步骤。
3.如权利要求1所述的方法，其中，所述晶种层是锗基晶种层。
4.如权利要求1所述的方法，其还包括：
提供具有侧壁的第二沟槽，所述侧壁由第二介电材料结构限定，并邻接限定所述第二沟槽的底表面的所述硅基材的表面；
在所述第二沟槽中种植第二应变弛豫缓冲层；和
在所述第二沟槽中的所述第二应变弛豫缓冲层上种植压缩应变的锗通道层。
5.如权利要求4所述的方法，其中，所述应变弛豫缓冲层和所述第二应变弛豫缓冲层在种植所述晶种层之后同时形成，并且由相同材料形成。
6.如权利要求4所述的方法，其中，所述应变锗通道层和所述压缩应变的锗通道层同时形成，并且由相同材料形成。
7.如权利要求6所述的方法，其中，所述晶种层是Ge层或SiGe层。
8.如权利要求4所述的方法，其中，提供所述沟槽和所述第二沟槽包括：对位于所述硅基材中形成的浅沟槽隔离(STI)结构之间的硅突起物开槽，并且其中，在种植所述晶种层之后进行开槽，以形成所述第二沟槽。
9.如权利要求4所述的方法，其中，形成所述应变锗通道层包括：形成具有(111)取向的分面，和
其中，形成所述压缩应变的锗通道层包括：形成具有(110)取向的侧壁和具有(001)取向的顶表面。
10.一种半导体晶体管装置，其包含：
具有侧壁的沟槽，所述侧壁由介电材料结构限定并邻接硅基材的表面；
在所述表面上的沟槽中形成的晶种层，所述晶种层具有前表面，所述前表面包含具有(111)取向的分面；
在所述晶种层上所述沟槽中形成的应变弛豫缓冲(SRB)层，所述应变弛豫缓冲层包含硅锗；和
在所述应变弛豫缓冲层上形成的应变锗通道层，所述应变锗通道层在所述沟槽中具有(111)取向。
11.如权利要求10所述的装置，其中，所述晶种层是锗晶种层或SiGe晶种层。
12.如权利要求10所述的装置，其还包含：
具有侧壁的第二沟槽，所述侧壁由介电材料结构限定，并邻接限定所述第二沟槽的底表面的硅基材的表面；
在所述第二沟槽中进一步形成的应变弛豫缓冲(SRB)层；和
在所述第二沟槽中所述应变弛豫缓冲层上形成的压缩应变的锗通道层。
13.如权利要求12所述的装置，其中，所述应变锗通道层和所述压缩应变的锗通道层各自是无掺杂的。
14.如权利要求10所述的装置，其中，所述沟槽具有底表面，所述底表面具有的取向使具有(111)取向的应变锗通道层的表面和所述沟槽的底表面在交叉平面中形成。
15.一种半导体晶体管装置，其包含：
n-通道金属氧化物硅(NMOS)晶体管装置，包含：
具有侧壁的沟槽，所述侧壁由介电材料结构限定并邻接硅基材的表面，
在所述表面上的沟槽中形成的晶种层，所述晶种层具有前表面，所述前表面包含具有(111)取向的分面，
在所述晶种层上所述沟槽中形成的应变弛豫缓冲(SRB)层，所述应变弛豫缓冲层包含硅锗，和
在所述应变弛豫缓冲层上形成的包含锗的通道层，所述通道层在所述沟槽中具有(111)取向；和
p-通道金属氧化物硅(PMOS)晶体管装置，包含：
具有侧壁的第二沟槽，所述侧壁由介电材料结构限定，并邻接限定所述第二沟槽的底表面的所述硅基材的表面；
在所述第二沟槽中进一步形成的应变弛豫缓冲(SRB)层；和
在所述第二沟槽中所述应变弛豫缓冲层上进一步形成的通道层，该进一步形成的通道层具有(110)侧壁取向和(001)顶表面取向。
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