CN107888179B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN107888179B
CN107888179B CN201710824613.0A CN201710824613A CN107888179B CN 107888179 B CN107888179 B CN 107888179B CN 201710824613 A CN201710824613 A CN 201710824613A CN 107888179 B CN107888179 B CN 107888179B
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CN
China
Prior art keywords
voltage
switch
substrate
node
mosfet
Prior art date
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Application number
CN201710824613.0A
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English (en)
Chinese (zh)
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CN107888179A (zh
Inventor
田边昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
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Publication of CN107888179A publication Critical patent/CN107888179A/zh
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electromagnetism (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
CN201710824613.0A 2016-09-29 2017-09-14 半导体装置 Active CN107888179B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-191234 2016-09-29
JP2016191234A JP6767225B2 (ja) 2016-09-29 2016-09-29 半導体装置

Publications (2)

Publication Number Publication Date
CN107888179A CN107888179A (zh) 2018-04-06
CN107888179B true CN107888179B (zh) 2023-07-25

Family

ID=61687317

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710824613.0A Active CN107888179B (zh) 2016-09-29 2017-09-14 半导体装置

Country Status (5)

Country Link
US (2) US10340905B2 (https=)
JP (1) JP6767225B2 (https=)
KR (1) KR20180035696A (https=)
CN (1) CN107888179B (https=)
TW (1) TWI728184B (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016092536A (ja) * 2014-10-31 2016-05-23 ルネサスエレクトロニクス株式会社 半導体装置
US10921839B2 (en) 2017-08-30 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Switchable power supply
JP7195133B2 (ja) * 2018-12-19 2022-12-23 ルネサスエレクトロニクス株式会社 半導体装置
CN112130614B (zh) * 2019-06-24 2021-11-02 华邦电子股份有限公司 反向偏压调整器
JP7256102B2 (ja) * 2019-10-21 2023-04-11 ルネサスエレクトロニクス株式会社 電子システム装置、及び電子システム装置の起動方法
CN112825263B (zh) * 2019-11-20 2024-08-13 合肥格易集成电路有限公司 Nand Flash的电压控制方法及非易失性存储器
CN116487380A (zh) 2022-03-11 2023-07-25 台湾积体电路制造股份有限公司 具有不同电压域的公共深n阱的半导体器件及其形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101207120A (zh) * 2006-12-18 2008-06-25 株式会社瑞萨科技 半导体集成电路及其制造方法
JP2012234593A (ja) * 2011-04-28 2012-11-29 Renesas Electronics Corp 半導体装置

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JP3705842B2 (ja) * 1994-08-04 2005-10-12 株式会社ルネサステクノロジ 半導体装置
KR0172555B1 (ko) * 1995-12-29 1999-03-30 김주용 고속 감지 증폭기
JP3732914B2 (ja) * 1997-02-28 2006-01-11 株式会社ルネサステクノロジ 半導体装置
JP4253052B2 (ja) * 1997-04-08 2009-04-08 株式会社東芝 半導体装置
US6411156B1 (en) * 1997-06-20 2002-06-25 Intel Corporation Employing transistor body bias in controlling chip parameters
JPH11214526A (ja) * 1998-01-21 1999-08-06 Mitsubishi Electric Corp 半導体回路装置
JP2002093195A (ja) 2000-09-18 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置のテスト方法
US6807109B2 (en) * 2001-12-05 2004-10-19 Renesas Technology Corp. Semiconductor device suitable for system in package
JP2004031411A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体装置
JP4473669B2 (ja) * 2004-07-28 2010-06-02 株式会社リコー 定電圧回路、その定電圧回路を使用した定電流源、増幅器及び電源回路
EP1662660A3 (en) * 2004-11-29 2007-12-12 STMicroelectronics Pvt. Ltd Method and apparatus for providing compensation against temperature, process and supply voltage variation
JP5008367B2 (ja) * 2005-09-29 2012-08-22 エスケーハイニックス株式会社 電圧発生装置
JP2007201236A (ja) * 2006-01-27 2007-08-09 Renesas Technology Corp 半導体集積回路
US7911855B2 (en) * 2006-02-24 2011-03-22 Renesas Technology Corp. Semiconductor device with voltage interconnections
US7355437B2 (en) * 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
JP2008148008A (ja) * 2006-12-11 2008-06-26 Renesas Technology Corp 基板制御回路、半導体集積回路及び基板制御方法
US7978001B2 (en) * 2008-09-25 2011-07-12 Via Technologies, Inc. Microprocessor with selective substrate biasing for clock-gated functional blocks
JP2010104195A (ja) * 2008-10-27 2010-05-06 Seiko Epson Corp 電気負荷駆動回路
US7800179B2 (en) * 2009-02-04 2010-09-21 Fairchild Semiconductor Corporation High speed, low power consumption, isolated analog CMOS unit
JP5488361B2 (ja) * 2010-09-15 2014-05-14 富士通株式会社 半導体集積回路
US8373497B2 (en) * 2011-01-11 2013-02-12 Infineon Technologies Ag System and method for preventing bipolar parasitic activation in a semiconductor circuit
US8743647B2 (en) * 2012-02-21 2014-06-03 Synopsys, Inc. Static read only memory device which consumes low stand-by leakage current
KR101926604B1 (ko) * 2012-02-27 2018-12-07 삼성전자 주식회사 스탠바이 모드 바디 바이어스 제어 방법 및 이를 이용한 반도체 장치
US9472948B2 (en) * 2013-09-30 2016-10-18 Infineon Technologies Ag On chip reverse polarity protection compliant with ISO and ESD requirements

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101207120A (zh) * 2006-12-18 2008-06-25 株式会社瑞萨科技 半导体集成电路及其制造方法
JP2012234593A (ja) * 2011-04-28 2012-11-29 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
US20180091130A1 (en) 2018-03-29
US20190273486A1 (en) 2019-09-05
US10447257B2 (en) 2019-10-15
JP2018055747A (ja) 2018-04-05
TW201824749A (zh) 2018-07-01
US10340905B2 (en) 2019-07-02
KR20180035696A (ko) 2018-04-06
TWI728184B (zh) 2021-05-21
JP6767225B2 (ja) 2020-10-14
CN107888179A (zh) 2018-04-06

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