CN107845628B - 集成电路器件及其组装方法 - Google Patents

集成电路器件及其组装方法 Download PDF

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CN107845628B
CN107845628B CN201710856201.5A CN201710856201A CN107845628B CN 107845628 B CN107845628 B CN 107845628B CN 201710856201 A CN201710856201 A CN 201710856201A CN 107845628 B CN107845628 B CN 107845628B
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connection
substrate
integrated circuit
die
circuit device
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CN107845628A (zh
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A.V.高达
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General Electric Co
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General Electric Co
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Memories (AREA)

Abstract

描述了一种集成电路(IC)器件。IC器件包括衬底。包括通过其中的腔的连接部件附接到衬底。存储器晶片位于连接部件的腔中并且电连接到衬底。逻辑晶片在存储器晶片和连接部件的至少一部分上延伸，并且电连接到连接部件和存储器晶片。连接部件形成为没有硅通孔并且通过引线接合电连接到衬底。

Description

集成电路器件及其组装方法
技术领域
本文公开的主题一般涉及集成电路器件。
背景技术
在常规的三维(3D)堆叠集成电路(IC)封装中，半导体器件竖直地堆叠并且彼此互连，使得能够实现更小的IC封装尺寸并且促进增加的电性能(例如，增加的带宽，减小的功耗等)。由于需要连接到外部电路的逻辑器件的互连数量的增加，至少一些已知的3D堆叠IC器件包括放置在逻辑器件的顶部上的存储器件或存储器堆栈。然而，典型地，与存储器件相比，逻辑器件具有增加的功率耗散，并且因此增加了工作温度。因此，使用至少一些3D堆叠的IC器件，将逻辑器件定位在存储器件和3D堆叠IC器件的衬底之间并不是热有利的布置。
另外，至少一些已知的3D堆叠IC器件包括在逻辑器件中形成的硅通孔(TSV)以便于将存储器件电连接到外部电路，这增加了逻辑器件制造的复杂性和成本。在至少一些已知的3D堆叠IC器件中，逻辑器件和存储器和外部电路之间的互连数量将需要存储器件中的硅通孔数量的增加，由此减小存储器件不动产的有效使用和成本效益。
发明内容
在一方面，提供了一种集成电路(IC)器件。IC器件包括衬底。IC器件还包括连接部件，连接部件包括通过其中限定的腔。连接部件连接到衬底。另外，IC器件包括位于腔中的至少一个存储器晶片。至少一个存储器晶片电连接到衬底。而且，IC器件包括在至少一个存储器晶片和连接部件的至少一部分上延伸的逻辑晶片。至少一个逻辑晶片电连接到连接部件和至少一个存储器晶片。连接部件没有硅通孔，并且通过至少一个引线接合电连接到衬底。
优选的，连接部件包括再分布引线层，再分布引线层包括至少一个引线接合垫，连接部件通过至少一个引线接合电连接到衬底。
优选的，至少一个存储器晶片包括有源表面，有源表面面对衬底并且背离逻辑晶片。
优选的，至少一个存储器晶片包括有源表面，有源表面面对逻辑晶片并且背离衬底。
优选的，连接部件是无源连接部件。
优选的，无源连接部件包括嵌入其中的至少一个无源部件。
优选的，无源部件包括以下的一个或多个：电阻器，电容器，和电感器。
优选的，连接部件是有源连接部件。
优选的，有源连接部件包括嵌入其中的至少一个有源电气部件。
优选的，有源电气部件包括以下的一个或多个：晶体管，信号放大器，和信号滤波器。
在另一方面，提供了另一集成电路(IC)器件。IC器件包括具有第一有源表面的衬底。第一有源表面包括多个衬底接合垫。IC器件也包括连接到衬底的第一有源表面的多个连接部件。多个连接部件布置成限定位于多个连接部件之间的腔。多个连接部件的每个连接部件包括与衬底的第一有源表面相对的第二有源表面。每个第二有源表面包括至少一个连接部件接合垫。而且，IC器件包括位于腔内并且电连接到衬底的第一有源表面的至少一个存储器晶片。另外，IC器件包括连接到每个第二有源表面和至少一个存储器晶片的逻辑晶片。多个连接部件没有硅通孔。此外，至少一个连接部件接合垫的每一个电连接到多个衬底接合垫中的一个衬底接合垫。
优选的，多个连接部件中的至少一个连接部件是无源连接部件。
优选的，至少一个无源连接部件包括嵌入其中的至少一个无源部件。
优选的，至少一个无源部件包括以下的一个或多个：电阻器，电容器，和电感器。
优选的，多个连接部件中的至少一个连接部件是有源连接部件。
优选的，有源连接部件包括嵌入其中的至少一个有源电气部件。
优选的，有源电气部件包括以下的一个或多个：晶体管，信号放大器，和信号滤波器。
在又一方面，提供了一种形成具有3D封装结构的IC器件的方法。方法包括形成没有硅通孔的连接部件。连接部件包括通过其中限定的腔；和再分布引线层，再分布引线层包括连接部件接合垫。方法还包括将连接部件连接到衬底。衬底包括衬底接合垫。而且，方法包括将至少一个存储器晶片连接到衬底使得存储器晶片位于腔内。此外，方法包括在存储器晶片和连接部件的至少一部分上延伸逻辑晶片，并且将逻辑晶片电连接到存储器晶片和连接部件的至少一部分。另外，方法包括将连接部件接合垫电连接到衬底接合垫。
优选的，形成连接部件包括独立地形成多个连接部件，多个连接部件的每个连接部件包括连接部件接合垫，并且其中将连接部件连接到衬底包括：将多个连接部件定位在衬底上以限定在位于多个连接部件之间的腔；以及将多个连接部件连接到衬底。
优选的，将至少一个存储器晶片连接到衬底包括：将存储器晶片的第一表面电连接到衬底；以及通过形成于存储器晶片中的多个硅通孔将存储器晶片的第二表面电连接到衬底，第二表面与第一表面相对。
附图说明
当参考附图阅读以下详细描述时，将更好地理解本公开的这些和其它特征、方面和优点，其中相同的附图标记在所有附图中表示相同的部件，其中：
图1是在单个三维(3D)封装结构中形成的现有技术集成电路(IC)器件的示意性前视图；
图2是在单个2.5维(2.5D)封装结构中形成的现有技术IC器件的示意性前视图；
图3是在单个3D封装结构中形成的示例性IC器件的截面图；
图4是图3中所示的IC器件的示意性平面图；
图5是在单个3D封装结构中形成的替代IC器件的示意性平面图；
图6是在单个3D封装结构中形成的另一替代IC器件的示意性平面图；以及
图7是形成具有单个3D封装结构的IC器件(例如图3中所示的示例性IC器件)的示例性方法的流程图。
除非另外说明，本文中提供的附图旨在示出本公开的实施例的特征。这些特征被认为可应用于包括本公开的一个或多个实施例的多种多样的系统中。因而，附图并不意味着包括本领域普通技术人员已知的实施本文中公开的实施例所需的所有常规特征。
具体实施方式
在下面的说明书和权利要求中，将提及许多术语，其应当被定义为具有以下含义。
单数形式“一”和“所述”包括复数指代物，除非上下文另外明确规定。
“可选的”或“可选地”表示随后描述的事件或情况可能发生或不发生，并且该描述包括事件发生的情况以及事件不发生的情况。
当在本文中在说明书和权利要求中各处使用时，近似语言可以应用于修饰可以允许改变的任何定量表示，而不导致与其相关的基本功能的变化。因此，由诸如“约”、“近似”和“大致”的一个或多个术语修饰的值不限于指定的精确值。在至少一些情况下，近似语言可以对应于用于测量该值的仪器的精度。在这里和整个说明书和权利要求中，范围限制可以组合和/或互换；这样的范围被识别并且包括其中包含的所有子范围，除非上下文或语言另外说明。
本文中描述的装置和方法通过将无源连接部件配置成围绕连接到并定位在逻辑晶片和封装衬底之间的存储器晶片促进增加集成电路器件的效率。逻辑晶片和存储器晶片经由焊接微凸点彼此连接并且直接通信。逻辑晶片经由焊接微凸点经由围绕存储器晶片定位的无源连接部件电连接到封装衬底。存储器晶片设有硅通孔(TSV)以使能够进行逻辑晶片和封装衬底之间的通信。另外，存储器晶片经由焊接微凸点直接连接到衬底封装。因而，本文中所述的实施例通过将逻辑晶片(较高功率耗散部件)远离封装衬底定位在存储器晶片(较低功率耗散部件)上方提供逻辑晶片的增加散热或效率。这促进增加热管理和逻辑晶片的增加性能。另外，所述的实施例减小在逻辑晶片中提供硅通孔的需要以使存储器晶片能够直接连接到封装衬底。这便于通过减小逻辑晶片的尺寸和复杂性减小逻辑晶片的制造成本。
图1是在单个三维(3D)封装结构中形成的现有技术集成电路(IC)器件100的示意性前视图。典型的3D封装结构包括安装在另一晶片的顶部上至少一个晶片，下部晶片具有硅通孔以允许上部晶片与下部晶片和封装衬底通信。例如，如图1中所示，IC器件100被制造为包括逻辑晶片102和至少一个存储器晶片104的单个3D封装。逻辑晶片102和存储器晶片104经由焊接微凸点110彼此直接连接并且竖直地集成，即，存储器晶片104位于逻辑晶片102的顶部上，大致覆盖逻辑晶片102。逻辑晶片102经由多个焊接微凸点112连接到封装衬底108。逻辑晶片102包括多个硅通孔106，其使存储器晶片104的至少一些连接能够经由焊接微凸点112连接到封装衬底108。尽管硅通孔106的长度与典型地在堆叠式封装结构中发现的引线接合相比减小，如本文中所述，但是硅通孔106增加逻辑晶片102的尺寸和复杂性。这导致与逻辑晶片102关联的增加制造成本。另外，IC器件100的热效率减小，原因是由逻辑晶片102生成的热传递到存储器晶片104。而且，热不能容易地从逻辑晶片102直接去除。
图2是在单个2.5维(2.5D)封装结构中形成的现有技术IC器件200的示意性前视图。典型的2.5D封装结构包括在单个平面中接着另一晶片安装的至少一个晶片，中介层放置在封装衬底和两个晶片之间，其中中介层具有连接其上表面和下表面上的金属化层的硅通孔。例如，如图2中所示，IC器件200被制造为包括逻辑晶片202、至少一个存储器晶片204和中介层(interposer)206的单个2.5D封装。逻辑晶片202和存储器晶片204以并排布置相应地经由焊接微凸点208和210直接连接到中介层206。中介层206包括使得能够进行逻辑晶片202和存储器晶片204之间的直接通信的电路(未示出)。中介层206典型地由硅制造，但是也使用其它材料，如玻璃、陶瓷和/或有机材料。中介层206包括多个硅通孔212，其使逻辑晶片202和存储器晶片204的至少一些连接能够经由焊接微凸点216连接到封装衬底214。然而，并排2.5D封装结构导致IC器件200的尺寸增加。另外，与图1中所示的3D封装结构相比，逻辑晶片202和存储器晶片204之间的连接路径的长度增加，这导致IC器件200的附加低效率。另外，中介层206包括用于逻辑晶片202和存储器晶片204的硅通孔212和连接电路，这导致与IC器件200关联的增加制造成本。
图3是在单个3D封装结构中形成的示例性IC器件300的截面图。图4是图3中所示的IC器件300的示意性平面图。参考图3和4，IC器件300被制造为单个3D封装并且包括封装衬底302，中介层部件或连接部件304，至少一个逻辑晶片308，和至少一个存储器晶片312。连接部件304经由多个焊接微凸点306连接到封装衬底302。至少一个逻辑晶片308位于连接部件304上，与封装衬底302相对。逻辑晶片308经由多个焊接微凸点310直接连接到连接部件304。在一些实施例中，逻辑晶片308是单个芯片，并且在其它实施例中，逻辑晶片308是多芯片(例如，并排芯片布置)封装。逻辑晶片308包括例如但不限于处理器，处理器件，或控制器，如通用中央处理单元(CPU)，图形处理单元(GPU)，加速处理单元(APU)，微控制器，精简指令集计算机(RISC)处理器，专用集成电路(ASIC)，可编程逻辑电路(PLC)，可编程逻辑单元(PLU)，现场可编程门阵列(FPGA)，门阵列，数字信号处理(DSP)器件，和/或使IC器件300能够如本文中所述起作用的任何其它逻辑电路或处理器件。
在示例性实施例中，连接部件304形成为围绕逻辑晶片308的周边延伸并具有限定的腔324的单个部件。经由从连接部件304的大体中心部分去除材料在其中形成腔324。如图4中所示，连接部件304大体为矩形并且限定大体矩形的腔32。尽管连接部件304被示出为具有大体矩形的形状，但是替代地，连接部件304具有使连接部件304能够如本文中所述起作用的任何形状。另外，腔324可以在连接部件304中的任何位置形成并且不需要大体居中定位。
而且，在示例性实施例中，连接部件304由硅制造并且包括一个或多个再分布引线层334。替代地，连接部件304由使连接部件304能够如本文中所述起作用的任何材料制造，例如但不限于玻璃，陶瓷，有机材料，锗，砷化镓，磷化铟，和碳化硅。再分布引线层334便于逻辑晶片308的电连接点或引脚(未示出)，例如对应于焊接微凸点310的位置，可用于连接部件304上的其它位置。因此，再分布引线层334便于将逻辑晶片308的电连接点或引脚引导到连接部件304上的有利位置，以便于使能够从逻辑晶片308上的不同位置接合到连接部件304上的类似和/或相邻位置，由此简化IC器件300的组装。
此外，在示例性实施例中，连接部件304是无源中介层。例如但不限于，在一些实施例中，连接部件304不包括附加电气部件，仅包括一个或多个再分布引线层334。在其它实施例中，连接部件304包括嵌入和/或形成于其上的一个或多个集成无源器件(IPD)，例如但不限于电阻器，电容器，电感器，或使连接部件304能够如本文中所述起作用的任何其它无源电器件。因此，在示例性实施例中，连接部件304不包括有源电气部件，例如但不限于晶体管，信号放大器，信号滤波器，或任何其它有源电气部件。替代地，在一些实施例中，连接部件304是有源中介层，并且包括嵌入和/或形成于其上的一个或多个有源电气部件。
参考图3和4，在示例性实施例中，存储器晶片312表示堆叠或多芯片布置。替代地，存储器晶片312可以是单芯片和/或未堆叠芯片布置。在示例性实施例中，逻辑晶片308和存储器晶片312经由焊接微凸点314彼此直接连接并且被竖直地集成，即，存储器晶片312相对于逻辑晶片308竖直地定位。在替代实施例中，逻辑晶片308和存储器晶片312使用使IC器件300能够如本文中所述起作用的任何连接方法彼此直接连接，例如但不限于经由扩散接合、共晶键合、热压接合、和导电聚合物的使用。在示例性实施例中，存储器晶片312位于逻辑晶片308下方。更具体地，存储器晶片312竖直地位于逻辑晶片308和封装衬底302之间使得逻辑晶片308覆盖存储器晶片312。存储器晶片312位于连接部件304的腔324中，并且逻辑晶片308与存储器晶片312完全重叠。在替代实施例中，逻辑晶片308仅仅与存储器晶片312部分地重叠。
在示例性实施例中，如图3中所示，存储器晶片312的有源表面316朝着逻辑晶片308的有源表面318并且远离衬底302定向，即，逻辑晶片308和存储器晶片312以面对面布置定向。存储器晶片312包括形成于其中的多个硅通孔(TSV)320以使能够直接电连接到封装衬底302。硅通孔320经由多个焊接微凸点322直接连接到衬底302。在替代实施例中，硅通孔320使用使IC器件300能够如本文中所述起作用的任何连接方法直接连接到衬底302，例如但不限于经由扩散接合，共晶键合，热压接合，和导电聚合物的使用。在一些实施例中，硅通孔320使用任何已知的制造技术形成于存储器晶片312中，如激光钻孔，机械钻孔，和/或蚀刻工艺。硅通孔320和焊接微凸点322使存储器晶片312的至少一个电连接能够连接到衬底302上的其它电路(未示出)而不通过逻辑晶片308。这便于增加IC器件300的效率以及减少与IC器件300的制造关联的制造成本。
在替代实施例中，存储器晶片312可以定向成使得存储器晶片312的有源表面316远离逻辑晶片308的有源表面318并朝着衬底302定向。在这样的实施例中，存储器晶片312的硅通孔320便于直接电连接到逻辑晶片308。而且，在这样的实施例中，硅通孔320经由焊接微凸点(如焊接微凸点314)直接连接到逻辑晶片308。因而，硅通孔320和焊接微凸点314使存储器晶片312的至少一个电连接能够直接连接到逻辑晶片308而不通过衬底302。在替代实施例中，逻辑晶片308和硅通孔320使用使IC器件300能够如本文中所述起作用的任何连接方法彼此直接连接，例如但不限于经由扩散接合，共晶键合，热压接合，和导电聚合物的使用。
在示例性实施例中，如图3和4中所示并且如本文中所述，逻辑晶片308经由多个焊接微凸点310直接连接到连接部件304。连接部件304包括形成于再分布引线层334上的一个或多个引线接合垫326。接合垫326经由形成于再分布引线层334上的电路(未示出)和/或形成于连接部件304的一个或多个内建层(未示出)内的内部电路328电连接到至少一个焊接微凸点310。因此，电信号(未示出)从逻辑晶片308传输到一个或多个引线接合垫326。而且，衬底302包括一个或多个引线接合垫330，其经由形成于衬底302的有源表面331之上/之中的电路和/或内部电路(未示出)连接到其它电路(未示出)。应当注意，与至少一些已知的中介层相反，连接部件304没有硅通孔，由此便于减小制造连接部件304的复杂性和制造成本。
在示例性实施例中，连接部件接合垫326和衬底接合垫330经由引线332电连接在一起。这便于将逻辑晶片308直接连接到衬底302。引线332例如但不限于由金、铝、铜及其合金制造。经由引线332将逻辑晶片308连接到衬底302促进用于将IC器件300连接到其它电器件和/或电路(未示出)的成本效益高和灵活的技术。
图5是在单个3D封装结构中形成的IC器件500的示意性平面图。参考图3和5，在示例性实施例中，IC器件500大致类似于IC器件300被制造，如本文中所述。IC器件500包括封装衬底302，至少一个逻辑晶片308，和至少一个存储器晶片312。然而，与本文中关于IC器件300所述的单一连接部件304相反，IC器件500包括一个或多个连接部件，例如连接部件502、504、506和508，如图5中所示。连接部件502、504、506和508经由多个焊接微凸点306连接到封装衬底302。逻辑晶片308与封装衬底302相对地定位在连接部件502、504、506和508上并与连接部件502、504、506和508连接。逻辑晶片308经由多个焊接微凸点310直接连接到连接部件502、504、506和508。在一些实施例中，逻辑晶片308是单个芯片，并且在其它实施例中，逻辑晶片308是多芯片(例如，并排芯片布置)封装。如本文中所述，逻辑晶片308包括例如但不限于处理器，处理器件，或控制器，如通用中央处理单元(CPU)，图形处理单元(GPU)，加速处理单元(APU)，微控制器，精简指令集计算机(RISC)处理器，专用集成电路(ASIC)，可编程逻辑电路(PLC)，可编程逻辑单元(PLU)，现场可编程门阵列(FPGA)，门阵列，数字信号处理(DSP)器件，和/或使IC器件500能够如本文中所述起作用的任何其它逻辑电路或处理器件。
在示例性实施例中，连接部件502、504、506和508是邻近逻辑晶片308的周边定位的分立部件，在其间限定用于接收存储器晶片312的腔524。如图5中所示，连接部件502、504、506和508是定位成限定大体矩形腔524的大体矩形部件。然而，应当注意尽管连接部件502、504、506和508被示出为具有大体矩形形状，但是可以预料连接部件502、504、506和508可以具有使连接部件502、504、506和508能够如本文中所述起作用的任何形状。
在示例性实施例中，连接部件502、504、506和508的每一个仅仅由逻辑器件308部分地覆盖。在这样的实施例中，连接部件502、504、506和508中的一个或多个可以是有源连接部件。例如，在一个实施例中，连接部件502、504、506和508中的一个或多个包括嵌入和/或形成于其上的有源电气部件，例如但不限于晶体管，信号放大器，信号滤波器，以及使一个或多个连接部件502、504、506和508能够如本文中所述起作用的任何其它有源电气部件。这样的有源电气部件放置在不由逻辑器件308覆盖的连接部件502、504、506和508的部分上。
在替代实施例中，连接部件502、504、506和508中的一个或多个是无源中介层。例如但不限于在一些这样的替代实施例中，一个或多个连接部件502、504、506和508不包括附加的电气部件。在其它这样的实施例中，一个或多个连接部件502、504、506和508包括嵌入和/或形成于其上的一个或多个集成无源器件(IPD)，例如但不限于电阻器，电容器，电感器，以及使连接部件502、504、506和508能够如本文中所述起作用的任何其它无源电气部件。
此外，在示例性实施例中，连接部件502、504、506和508由硅制造并且包括一个或多个再分布引线层334(即，和有源表面)。替代地，连接部件502、504、506和508由使连接部件502、504、506和508能够如本文中所述起作用的任何材料制造，例如但不限于玻璃，陶瓷，有机材料，锗，砷化镓，磷化铟，和碳化硅。再分布引线层334便于逻辑晶片308的电连接点或引脚(未示出)，例如对应于焊接微凸点310的位置，可用于连接部件502、504、506和508上的其它位置。因此，再分布引线层334便于将逻辑晶片308的电连接点或引脚引导到连接部件502、504、506和508上的有利位置，以便于使能够从逻辑晶片308上的不同位置接合到连接部件502、504、506和508上的类似和/或相邻位置，由此简化IC器件500的组装。
参考图3和5，逻辑晶片308和存储器晶片312经由焊接微凸点314彼此直接连接并且竖直地集成，即，存储器晶片312竖直地定位在逻辑晶片308下方。更具体地，存储器晶片312竖直地定位在逻辑晶片308和封装衬底302之间，使得逻辑晶片308覆盖存储器晶片312。在这样的实施例中，存储器晶片312定位在由连接部件502、504、506和508限定的腔524中，并且逻辑晶片308与存储器晶片312完全重叠。替代地，逻辑晶片308仅仅与存储器晶片312部分地重叠。
在示例性实施例中，逻辑晶片308经由多个焊接微凸点310直接连接到连接部件502、504、506和508。连接部件502、504、506和508包括形成于再分布引线层534上的一个或多个引线接合垫526。接合垫526经由形成于再分布引线层534上的电路(未示出)和/或形成于连接部件502、504、506和508的一个或多个内建层(未示出)内的内部电路328电连接到至少一个焊接微凸点310。因此，电信号(未示出)从逻辑晶片308传输到一个或多个引线接合垫526。应当注意，与至少一些已知的中介层相反，连接部件502、504、506和508没有硅通孔，由此便于减小制造连接部件502、504、506和508的复杂性和制造成本。
在示例性实施例中，连接部件接合垫526和衬底接合垫330经由引线332电连接在一起。这便于将逻辑晶片308直接连接到衬底302。如本文中所述，引线332例如但不限于由金、铝、铜及其合金制造。经由引线332将逻辑晶片308连接到衬底302促进用于将IC器件500连接到其它电器件和/或电路(未示出)的成本效益高和灵活的技术。
图6是在单个3D封装结构中形成的IC器件600的示意性平面图。参考图3和6，在示例性实施例中，IC器件600大致类似于IC器件300和500被制造，如本文中所述。例如，IC器件600包括封装衬底302，至少一个逻辑晶片308，和至少一个存储器晶片312。然而，与在本文中相应地关于IC器件300和500所述的单一连接部件304或大致矩形连接部件502、504、506和508相反，IC器件600包括一个或多个“L形”连接部件，例如连接部件602和604，如图6中所示。连接部件602和604经由多个焊接微凸点306连接到封装衬底302。逻辑晶片308与封装衬底302相对地定位在连接部件602和604上并与连接部件602和604连接。逻辑晶片308经由多个焊接微凸点310直接连接到连接部件602和604。
在示例性实施例中，连接部件602和604是围绕逻辑晶片308的周边定位的分立部件，在其间限定用于接收存储器晶片312的腔624。如图6中所示，连接部件602和604定位成限定大体矩形的腔624。逻辑晶片308和存储器晶片312彼此直接连接，使得存储器晶片312竖直地定位在逻辑晶片308和封装衬底302之间。在这样的实施例中，存储器晶片312定位在由连接部件602和604限定的腔624中，并且逻辑晶片308与存储器晶片312完全重叠。替代地，逻辑晶片308仅仅与存储器晶片312部分地重叠。
在示例性实施例中，如图3和6中所示，逻辑晶片308经由多个焊接微凸点310直接连接到连接部件602和604。连接部件602和604包括形成于再分布引线层634上的一个或多个引线接合垫626。接合垫626经由形成于再分布引线层634上的电路(未示出)和/或形成于连接部件602和604的一个或多个内建层(未示出)内的内部电路328电连接到至少一个焊接微凸点310。因此，电信号(未示出)从逻辑晶片308传输到一个或多个引线接合垫626。应当注意，与至少一些已知的中介层相反，连接部件602和604没有硅通孔，由此便于减小制造连接部件602和604的复杂性和制造成本。
而且，在示例性实施例中，连接部件接合垫626和衬底垫330经由引线332电连接在一起。这便于将逻辑晶片308直接连接到衬底302。如本文中所述，引线332例如但不限于由金、铝、铜及其合金制造。经由引线332将逻辑晶片308连接到衬底302促进用于将IC器件600连接到其它电器件和/或电路(未示出)的成本效益高和灵活的技术。
此外，在示例性实施例中，连接部件602和604以与连接部件304和/或连接部件502、504、506和508大致相同的方式形成。例如，连接部件602和604由硅制造并且包括一个或多个再分布引线层634。替代地，连接部件602和604由使连接部件602和604能够如本文中所述起作用的任何材料制造，例如但不限于玻璃，陶瓷，有机材料，锗，砷化镓，磷化铟，和碳化硅。另外，在一些实施例中，连接部件602和604中的一个或多个是有源连接部件，包括嵌入和/或形成于其上的一个或多个有源电气部件，例如但不限于晶体管，信号放大器，信号滤波器，以及使一个或多个互连部件602和604能够如本文中所述起作用的任何其它有源电气部件。在其它实施例中，连接部件602和604中的一个或多个是无源中介层，即，连接部件602和604不包括附加的电气部件。在一些这样的实施例中，连接部件602和604中的一个或多个包括嵌入和/或形成于其上的一个或多个集成无源器件(IPD)，例如但不限于电阻器，电容器，电感器，以及使连接部件602和604能够如本文中所述起作用的任何其它无源电气部件。
图7是形成具有单个3D封装结构的IC器件(例如图3中所示的示例性IC器件300)的示例性方法700的流程图。参考图3-6，示例性方法700包括形成702至少一个连接部件，例如连接部件304，其具有在其中限定的腔324。附加地或替代地，方法700包括独立地形成704多个连接部件，例如连接部件502、504、506、508和/或602和604，并且将多个连接部件502、504、506、508和/或602和604定位706在衬底(例如衬底302)上以在其间限定腔(例如，相应地为腔524或624)。每个连接部件304、502、504、506、508和/或602和604包括相应地形成于再分布引线层334、534或634上的一个或多个引线接合垫(例如，相应地为引线接合垫326、526或626)。另外，衬底302包括形成于衬底302的有源表面331上的一个或多个引线接合垫330。
在示例性实施例中，方法700也包括将至少一个连接部件连接708到衬底302。附加地或替代地，连接708至少一个连接部件的操作还包括经由粘合剂接合，焊接微凸点306，以及使IC器件300能够如本文中所述起作用的任何其它电或非电接合工艺将至少一个连接部件接合710到衬底302。
在一些实施例中，方法700包括经由多个焊接微凸点322将至少一个存储器晶片312电连接712到衬底302，使得存储器晶片312定位在由至少一个连接部件限定的腔内。在一个这样的实施例中，将至少一个存储器晶片312电连接712到衬底302包括将存储器晶片312的有源表面316电连接714到衬底302。在替代实施例中，将至少一个存储器晶片312电连接712到衬底302的操作包括经由多个焊接微凸点322将多个硅通孔320电连接716到衬底302，即，将存储器晶片312的非有源表面连接到衬底302。
在示例性实施例中，方法700还包括将逻辑晶片308电连接718到存储器晶片312和连接部件的至少一部分。例如，逻辑晶片308经由多个焊接微凸点314连接到存储器晶片312。另外，逻辑晶片308经由多个焊接微凸点310连接到至少一个连接部件。在一个实施例中，逻辑晶片308完全覆盖存储器晶片312。在替代实施例中，逻辑晶片308仅仅部分地覆盖存储器晶片312。
而且，方法700包括经由引线332将连接部件接合垫(例如垫326、526或626)电连接720到衬底接合垫330。这便于将逻辑晶片308电连接到衬底302。
与至少一些已知的IC器件相比，连接部件和方法的上述实施例使得能够制造具有热有利布置、改善的散热以及减小的复杂性和制造成本的IC器件。具体地，公开的连接部件实施例包括配置成接收至少一个减小功率耗散部件(例如，存储器晶片(或存储器晶片堆叠))的腔。该腔便于将存储器晶片电连接到逻辑晶片和IC封装衬底，将存储器晶片竖直地定位在其间。这使典型地由于电互连的数量减少而位于逻辑晶片的顶部上的存储器晶片能够将其逻辑晶片连接直接连接到逻辑晶片并且将剩余连接连接到衬底上的其它电路。另外，这样的布置减少和/或消除了将在逻辑晶片中形成的硅通孔的需要，由此减小逻辑晶片的尺寸和复杂性。连接部件使逻辑晶片能够经由引线接合(例如，球形接合，楔形接合，和柔性接合)电连接到衬底上的电路，由此减少和/或消除在存储器晶片中形成硅通孔以从逻辑晶片传送电信号的需要。也具体地，连接部件便于减小制造本文中所述的IC器件的复杂性、时间和成本。
本文中所述的方法、系统和装置的示例性技术效果包括以下的至少一个：(a)将逻辑晶片放置在封装结构的外部上(而不是夹在存储器晶片和衬底之间)，导致更好的热管理和因此增强的性能；(b)减小逻辑晶片的复杂性(即，减少或消除硅通孔)并且由此减小制造成本；以及(c)进一步通过使用引线接合连接部件减小IC器件的总成本。
上面详细描述了限定3D堆叠晶片的腔的连接部件和方法的示例性实施例。具有腔的连接部件和使用这样的连接部件的方法不限于本文中所述的具体实施例，而是可以单独地和独立于本文中所述的其它部件和/或操作使用系统的部件和/或方法的操作。例如，示例性实施例可以结合当前配置成使用堆叠集成电路器件的许多其它应用被实现和使用。
尽管本公开的各种实施例的具体特征在一些图中示出而在其它图中未示出，但是这仅仅是为了方便。根据本公开的原理，图的任何特征可以与任何其它图的任何特征组合被引用/或要求权利。
该书面描述使用示例来公开包括最佳模式的实施例，并且也使本领域的任何技术人员能够实施实施例，包括制造和使用任何装置或系统并且执行任何包含的方法。本公开的专利范围由权利要求限定，并且可以包括本领域的技术人员想到的其它示例。这样的其它示例旨在属于权利要求的范围内，只要它们具有与权利要求的文字语言没有区别的结构元件，或者只要它们包括与权利要求的文字语言无实质区别的等效结构元件。

Claims (20)

1.一种集成电路器件，其包括：
衬底；
连接部件，所述连接部件包括通过其中限定的腔，所述连接部件耦合到所述衬底；
位于所述腔中的至少一个存储器晶片，所述至少一个存储器晶片电耦合到所述衬底；以及
逻辑晶片，所述逻辑晶片在所述连接部件的至少一部分和所述至少一个存储器晶片之上延伸，所述至少一个逻辑晶片电耦合到所述连接部件和所述至少一个存储器晶片，其中所述连接部件没有硅通孔，并且其中所述连接部件通过至少一个引线接合电耦合到所述衬底。
2.根据权利要求1所述的集成电路器件，其中所述连接部件包括再分布引线层，所述再分布引线层包括至少一个引线接合垫，并且所述衬底包括至少一个衬底接合垫，并且所述至少一个引线接合垫通过所述至少一个引线接合电耦合到所述衬底接合垫。
3.根据权利要求1所述的集成电路器件，其中所述至少一个存储器晶片包括有源表面，所述有源表面面对所述衬底并且背对着所述逻辑晶片。
4.根据权利要求1所述的集成电路器件，其中所述至少一个存储器晶片包括有源表面，所述有源表面面对所述逻辑晶片并且背对着所述衬底。
5.根据权利要求1所述的集成电路器件，其中所述连接部件是无源连接部件。
6.根据权利要求5所述的集成电路器件，其中所述无源连接部件包括嵌入其中的至少一个无源部件。
7.根据权利要求6所述的集成电路器件，其中所述无源部件包括以下中的一个或多个：电阻器；电容器；和电感器。
8.根据权利要求1所述的集成电路器件，其中所述连接部件是有源连接部件。
9.根据权利要求8所述的集成电路器件，其中所述有源连接部件包括嵌入其中的至少一个有源电气部件。
10.根据权利要求9所述的集成电路器件，其中所述有源电气部件包括以下中的一个或多个：晶体管；信号放大器；和信号滤波器。
11.一种集成电路器件，其包括：
包括第一有源表面的衬底，所述第一有源表面包括多个衬底接合垫；
耦合到所述第一有源表面的多个连接部件，所述多个连接部件布置成限定位于所述多个连接部件之间的腔，所述多个连接部件的每个连接部件包括与所述第一有源表面相反的第二有源表面，每个所述第二有源表面包括至少一个连接部件接合垫；
至少一个存储器晶片，所述至少一个存储器晶片位于所述腔内并且电耦合到所述第一有源表面；以及
逻辑晶片，所述逻辑晶片耦合到每个所述第二有源表面和所述至少一个存储器晶片，其中所述多个连接部件没有硅通孔，并且其中每个所述至少一个连接部件接合垫通过至少一个引线接合电耦合到所述多个衬底接合垫中的衬底接合垫。
12.根据权利要求11所述的集成电路器件，其中所述多个连接部件中的至少一个连接部件是无源连接部件。
13.根据权利要求12所述的集成电路器件，其中所述至少一个无源连接部件包括嵌入其中的至少一个无源部件。
14.根据权利要求13所述的集成电路器件，其中所述至少一个无源部件包括以下中的一个或多个：电阻器；电容器；和电感器。
15.根据权利要求11所述的集成电路器件，其中所述多个连接部件中的至少一个连接部件是有源连接部件。
16.根据权利要求15所述的集成电路器件，其中所述有源连接部件包括嵌入其中的至少一个有源电气部件。
17.根据权利要求16所述的集成电路器件，其中所述有源电气部件包括以下中的一个或多个：晶体管；信号放大器；和信号滤波器。
18.一种形成具有3D封装结构的集成电路器件的方法，所述方法包括：
形成没有硅通孔的连接部件，所述连接部件包括：通过其中限定的腔; 和再分布引线层, 所述再分布引线层包括连接部件接合垫；
将所述连接部件耦合到衬底，所述衬底包括衬底接合垫；
将至少一个存储器晶片耦合到所述衬底，使得所述存储器晶片位于所述腔内；
在所述连接部件的至少一部分和所述存储器晶片之上延伸逻辑晶片；
将所述逻辑晶片电耦合到所述连接部件的所述至少一部分和所述存储器晶片；以及
将所述连接部件接合垫通过至少一个引线接合电耦合到所述衬底接合垫。
19.根据权利要求18所述的方法，其中形成所述连接部件包括独立地形成多个连接部件，所述多个连接部件中的每个连接部件包括连接部件接合垫，并且其中将所述连接部件耦合到所述衬底包括：
将所述多个连接部件定位在所述衬底上，以限定位于所述多个连接部件之间的腔；以及
将所述多个连接部件耦合到所述衬底。
20.根据权利要求18所述的方法，其中将所述至少一个存储器晶片耦合到所述衬底包括：
将所述存储器晶片的第一表面电耦合到所述衬底；以及
通过形成于所述存储器晶片中的多个硅通孔将所述存储器晶片的第二表面电耦合到所述衬底，所述第二表面与所述第一表面相反。
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