CN112151527A - 包括分叉存储器模块的高容量半导体器件 - Google Patents

包括分叉存储器模块的高容量半导体器件 Download PDF

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Publication number
CN112151527A
CN112151527A CN201910575708.2A CN201910575708A CN112151527A CN 112151527 A CN112151527 A CN 112151527A CN 201910575708 A CN201910575708 A CN 201910575708A CN 112151527 A CN112151527 A CN 112151527A
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semiconductor
memory array
semiconductor device
dies
die
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杨旭一
马世能
张聪
邱进添
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Priority to CN201910575708.2A priority Critical patent/CN112151527A/zh
Priority to US16/818,752 priority patent/US11276669B2/en
Publication of CN112151527A publication Critical patent/CN112151527A/zh
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Abstract

本发明题为“包括分叉存储器模块的高容量半导体器件”。本发明公开了一种半导体器件，所述半导体器件包括堆叠的集成存储器模块的晶圆。本发明技术的半导体器件可包括多个存储器阵列半导体晶圆和CMOS控制器晶圆，所述多个存储器阵列半导体晶圆和所述CMOS控制器晶圆一起作为单个集成闪存存储器半导体器件工作。在实施方案中，所述CMOS控制器晶圆可包括半导体管芯，所述半导体管芯包括与存储器阵列逻辑电路集成在一起的ASIC逻辑电路。

Description

包括分叉存储器模块的高容量半导体器件
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储器设备诸如闪存存储卡已广泛用于满足对数字信息存储和交换的日益增长的需求。此类存储器设备的设计具有便携性、多功能性且坚固耐用，加上它们的可靠性高且容量大，使得它们成为用于各种电子设备的理想选择，包括例如数字相机、数字音乐播放器、视频游戏控制器、PDA、蜂窝电话和固态驱动器。
最近，已经提出了使用3D堆叠存储器结构的超高密度存储器设备，该结构具有形成为层的存储器单元串。一种此类存储设备有时被称为位成本缩减(BiCS)架构。除了分层存储器单元之外，3D存储器设备还包括用于控制存储器单元的读/写的逻辑电路。逻辑电路常使用互补金属氧化物半导体(CMOS)技术来制造，通常可形成在半导体晶圆内的堆叠存储器层下方。
目前，在数据中心中将闪存设备用为固态驱动器(SSD)是一项重大举措。随着3D存储器结构中的存储器层的数量增加以满足不断增长的数据中心存储器需求，将逻辑电路定位在3D存储器单元结构下方变得越来越困难。另外，针对存储器阵列形成而优化的过程参数可能不会针对逻辑电路形成进行优化。例如，利用热量使3D存储器单元结构退火是已知的。虽然热量对存储器单元结构有利，但可能会对逻辑电路的操作产生不利影响。
附图说明
图1是根据本发明技术的实施方案的用于形成包括控制器管芯的第一晶圆的流程图。
图2是根据本发明技术的实施方案的包括控制器管芯的第一半导体晶圆的第一主表面的顶视图。
图3是根据本发明技术的实施方案的第一半导体晶圆的控制器管芯的顶视图。
图4是根据本发明技术的实施方案的第一半导体晶圆的控制器管芯的横截面边缘视图。
图5是根据本发明技术的实施方案的控制器管芯的示意性框图。
图6是根据本发明技术的实施方案的用于形成包括存储器阵列管芯的第二晶圆的流程图。
图7是根据本发明技术的实施方案的包括存储器阵列管芯的第二半导体晶圆的第一主表面的顶视图。
图8是根据本发明技术的实施方案的第二半导体晶圆的存储器阵列管芯的顶视图。
图9是根据本发明技术的实施方案的第二半导体晶圆的存储器阵列管芯的横截面边缘视图。
图10是根据本发明技术的实施方案的用于形成半导体器件的流程图。
图11是根据本发明技术的实施方案的形成集成晶圆半导体器件的多个堆叠晶圆的透视图。
图12是根据本发明技术的实施方案的来自形成集成晶圆存储器模块的晶圆的多个堆叠半导体管芯的分解横截面边缘视图。
图13是根据本发明技术的耦接到主机设备的半导体器件的存储器模块的横截面边缘视图。
图14是根据本发明技术的实施方案的存储器模块的功能框图。
图15是根据本发明技术的实施方案的形成多通道集成晶圆半导体器件的多个堆叠晶圆的透视图。
图16是根据本发明技术的实施方案的多通道集成晶圆存储器模块的功能框图。
具体实施方式
现在将参考附图描述本发明的技术，附图在实施方案中涉及包括堆叠的集成存储器模块的晶圆的半导体器件。本发明技术的半导体器件可包括多个存储器阵列半导体晶圆和CMOS控制器晶圆，多个存储器阵列半导体晶圆和CMOS控制器晶圆一起作为单个集成闪存存储器半导体器件工作。在实施方案中，CMOS控制器晶圆可包括半导体管芯，该半导体管芯包括与存储器阵列逻辑电路集成在一起的ASIC逻辑电路。控制器晶圆管芯的ASIC逻辑电路执行存储器管理，并且充当与主机设备诸如数据中心内的服务器或主机的接口。控制器晶圆管芯的存储器阵列逻辑电路包括传感器放大器和外围功能，并且充当与存储器阵列晶圆管芯的存储器阵列的接口。
控制器和存储器阵列晶圆管芯可形成有硅通孔(TSV)，使得一旦将控制器和存储器阵列晶圆堆叠，相应堆叠半导体管芯的TSV就可彼此对准和附接，从而以电气和机械方式连接相应晶圆中的每个半导体管芯，以形成集成半导体器件。下文提供了根据本发明技术的集成半导体器件和TSV的更多细节。
应当理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是周密且完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下具体实施方式中，给出了许多具体细节，以便提供对本发明的周密理解。然而，对于本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为给定尺寸的±2.5％。
现在将参考图1的流程图以及图2至图5的视图解释包括控制器半导体管芯的第一晶圆的实施方案。在步骤50中，可将第一半导体晶圆100加工成多个第一半导体管芯102，如图2至图4所示。这些第一半导体管芯102在本文中也可被称为控制器管芯102，并且第一晶圆100在本文中也可被称为控制器晶圆100。第一半导体晶圆100开始时可以是晶圆材料的晶锭，晶圆材料可以是根据Czochralski(CZ)或浮区(FZ)工艺生长的单晶硅。然而，在另外的实施方案中，第一晶圆100可由其他材料并通过其他工艺形成。
控制器晶圆100可从晶锭切割并在第一主平坦表面104和与表面104相反的第二主平坦表面107(图4)两者上抛光，以提供平滑表面。第一主表面104可经历各种加工步骤以将晶圆100分成相应的第一半导体管芯102，并且在第一主表面104上和/或第一主表面104中形成相应第一半导体管芯102的集成电路。
具体地讲，在步骤50中，可在实施方案中加工第一半导体管芯102，以包括形成在包括层116的介电衬底中的ASIC逻辑电路112和存储器阵列逻辑电路114，如图4所示。图4示出了代表第一晶圆100上的所有管芯102的单个管芯102的横截面。下文参考图5描述了ASIC逻辑电路112和存储器阵列逻辑电路114的更多细节，但一般来讲，ASIC逻辑电路112执行存储器管理并充当控制与主机设备交换数据的接口。存储器阵列逻辑电路114包括传感器放大器(SA)和外围(peri)电路，这些外围电路充当切换模式接口电路，以便将位线/字线解码到缓冲器，然后在存储器阵列(如下所述)和ASIC逻辑电路112之间传输数据。在实施方案中，ASIC逻辑电路112可在晶圆100的层中在存储器阵列逻辑电路114上方制造(从图4的视角)。逻辑电路112、114可使用CMOS技术来制造，但在另外的实施方案中，逻辑电路可使用其他技术来制造。在如下所述的另外的实施方案中，控制器半导体管芯102可包括其他和/或附加集成电路。
在步骤52中，可在半导体管芯102的层中并且穿过半导体管芯102的层形成多层金属互连件和通孔120。这些金属互连件和通孔120可以电气方式耦接ASIC逻辑电路112和存储器阵列逻辑电路114。这些金属互连件和通孔120还可包括在第一晶圆100的顶部主平坦表面104和底部主平坦表面107之间延伸的硅通孔(TSV)120a的图案。
可通过在完成的TSV 120a的图案中穿过第一半导体管芯102蚀刻孔来形成TSV120a。然后，可将这些孔衬有防扩散的屏障。随后可通过PVD或CVD沉积晶种层，但在另外的实施方案中可通过其他技术来沉积。晶种层可由铜、铝、锡、镍、金、其合金或其他材料形成。然后可将导电材料电镀到晶种层上。导电材料可包含铜，但也可使用其他合适的材料，诸如铝、锡、镍、金、掺杂多晶硅及其合金或其组合。
可在介电膜层116的顶部形成钝化层128。在步骤54中，可在钝化层128上形成耦接到TSV 120a的接合焊盘108(图3和图4)。可在TSV120a上方蚀刻钝化层128，并且可在衬垫106上方形成接合焊盘108。如本领域中已知的，接合焊盘108可由例如铜、铝及其合金形成，并且衬垫106可由例如钛/氮化钛叠堆(诸如，例如Ti/TiN/Ti)形成，但在另外的实施方案中这些材料可有所不同。接合焊盘108和衬垫106一起可具有720nm的厚度，但在另外的实施方案中该厚度可更大或更小。
在步骤56中，可在背面研磨工艺中将控制器晶圆100变薄，以限定晶圆100的第二主平坦(无源)表面107。在步骤58中，可在第二主平坦表面107上形成重新分布层(RDL)130，如图4所示。RDL 130可将所选择的接合焊盘108和TSV 120a以电气方式连接到分布在RDL130上的微凸块132的图案。微凸块132可以是Cu、AgSn或可以在两个晶圆之间接合的其他金属。微凸块132的高度可为约1μm至50μm，但该高度可比另外的实施方案中的高度更薄或更厚。包括TSV 120a的金属互连件120可用于在管芯接合焊盘108和ASIC逻辑电路112之间以及在存储器阵列逻辑电路114和微凸块132之间传输信号和电流。
图2中在晶圆100上所示的半导体管芯102的数量和图案仅是示例性的。在另外的实施方案中，晶圆100可包括更多的第一半导体管芯102，并且可包括不同的图案。类似地，图3和图4包括一个半导体管芯102上的围绕半导体管芯102的外围的接合焊盘108的图案。然而，在另外的实施方案中，图3和图4中的第一半导体管芯102上的接合焊盘108的图案以及接合焊盘108的数量可有所不同。
图5是示出控制器管芯102上的ASIC逻辑电路112和存储器阵列逻辑电路114的更多细节的框图。ASIC逻辑电路112包括主机接口142，该主机接口连接到主机设备300并与该主机设备通信(图13)。在一个实施方案中，主机接口142提供PCIe接口。还可以使用其他接口，诸如SCSI、SATA等。主机接口142还连接到片上网络(NOC)134。NOC是集成电路上的通信子系统。NOC可跨越同步和异步时钟域，或者使用非时钟的异步逻辑。NOC技术将网络理论和方法应用于片上通信，并且与常规总线和交叉开关互连相比带来了显著的改善。与其他设计相比，NOC提高了片上系统(SoC)的可扩展性和复杂SoC的功效。NOC的导线和链路由许多信号共享。由于NOC中的所有链路可在不同的数据包上同时运行，因此实现了高水平的并行性。因此，随着集成子系统的复杂性不断增长，与先前的通信架构(例如，专用的点对点信号线、共享总线或具有桥的分段总线)相比，NOC提供增强的性能(诸如吞吐量)和可扩展性。连接到NOC 134并与其通信的是处理器136、ECC引擎138、存储器接口140和DRAM控制器144。DRAM控制器144用于操作本地高速易失性存储器146(例如，DRAM)并与之通信。在其他实施方案中，本地高速易失性存储器146可以是SRAM或其他类型的易失性存储器。
ECC引擎138执行错误校正服务。例如，ECC引擎138根据实现的ECC技术执行数据编码和解码。在一个实施方案中，ECC引擎138是由软件编程的电路。例如，ECC引擎138可以是可以被编程的处理器。在其他实施方案中，ECC引擎138是没有任何软件的定制且专用的硬件电路。在另一个实施方案中，ECC引擎138的功能由处理器136实现。
处理器136执行各种存储器操作。例如，存储器阵列模块(MM)是在处理器136上运行的用于执行编程、擦除、读取以及存储器管理过程的模块/过程。读取校准管理器(RC)是在处理器136上运行的用于执行读取校准过程的模块/过程。在一个实施方案中，读取校准管理器(RC)被实现为ECC引擎138的一部分。错误指示管理器(IOE)是在处理器136上运行的用于计算错误指示的模块/过程，其用于校准读取参考水平。在一个实施方案中，错误指示管理器(IOE)被实现为ECC引擎138的一部分或读取校准管理器(RC)的一部分。
在一个实施方案中，处理器136由固件编程，使得读取校准管理器(RC)和错误指示管理器(IOE)为固件/软件。在其他实施方案中，处理器136是没有任何软件的定制且专用的硬件电路。处理器136(单独或与ECC引擎138一起)可执行读取参考水平的重新校准，以便确定更新的读取参考水平，包括动态地且自适应地选择用于感测样本数据的测试读取参考水平。
处理器136还将转换模块(TM)实现为软件/固件过程或专用硬件电路。在许多系统中，使用与一个或多个存储器管芯相关联的物理地址在存储系统内部寻址非易失性存储器，如下所述。然而，主机系统将使用逻辑地址来寻址各种存储器位置。这使得主机能够将数据分配给连续的逻辑地址，同时存储系统可以在一个或多个存储器管芯的位置之间自由地存储数据。
存储器接口140与存储器阵列逻辑电路114通信。第二管芯202上的存储器阵列212(如下所述)可由第一管芯102上的存储器阵列逻辑电路114控制。存储器阵列逻辑电路114可具有用于访问、控制和驱动存储器阵列的存储器元件以实现诸如编程和读取的功能的电路。存储器阵列逻辑电路114与读/写电路168配合以在存储器阵列上执行存储器操作。读/写电路168可包括多个感测块(感测电路)，这些感测块允许并行地读取或编程来自存储器晶圆(如下所述)上的存储器阵列管芯的存储器单元的页面。
在实施方案中，逻辑电路114可包括状态机152、地址解码器154和功率控制模块156。状态机152提供存储器操作的芯片级控制。可提供存储区域153用于操作存储器阵列212，诸如对不同行或其他组的存储器单元的参数进行编程。这些编程参数可包括位线电压和验证电压。
地址解码器154提供主机设备或ASIC逻辑电路112使用的地址接口与解码器163和166使用的硬件地址之间的地址接口。功率控制模块156控制在存储器操作期间提供给字线和位线的功率和电压。功率控制模块可以包括用于3D配置中的字线层的驱动器、源极侧选择栅极、漏极侧选择栅极和源极线。源极侧选择栅极是NAND串的源极端处的栅极晶体管，并且漏极侧选择栅极是NAND串的漏极端处的晶体管。
根据本发明技术的方面，将上述ASIC逻辑电路112和存储器阵列逻辑电路114集成到单个半导体管芯102中，并且将存储器阵列212(如下所述)分离到其自身的芯片上。然而，应当理解，可以将ASIC逻辑电路112和存储器阵列逻辑电路114的一些上述功能卸载到存储器阵列半导体管芯上。在另外的实施方案中，可将附加组件和功能添加到控制器管芯102中。
在第一晶圆100上形成控制器半导体管芯之前、之后或与之并行，可将第二半导体晶圆200加工成多个第二半导体管芯202。现在将参考图6的流程图以及图7至图9的视图解释晶圆200上的半导体管芯202的制造和操作。
图7示出了第二半导体晶圆200的顶视图。第二半导体晶圆200开始时可以是根据CZ、FZ或其他工艺生长的单晶硅的晶锭。第二半导体晶圆200可在第一主表面204和与表面204相反的第二主表面207(图9)两者上切割和抛光，以提供平滑表面。第一主表面204可经历各种加工步骤以将第二晶圆200分成相应的第二半导体管芯202，并且在第一主表面204上和/或第一主表面204中形成相应第二半导体管芯202的集成电路。这些第二半导体管芯202在本文中也可被称为存储器阵列管芯202，并且第二晶圆200在本文中也可被称为存储器阵列晶圆200。
在一个实施方案中，可在步骤60中加工存储器阵列管芯202，以包括形成在包括层224和226的介电衬底中的存储器阵列212，如图9所示。图9示出了代表晶圆200上的所有管芯202的单个管芯202的横截面。下文提供了存储器阵列212的更多细节，但一般来讲，存储器阵列212可形成为3D堆叠存储器结构，该结构具有形成为层的存储器单元串。然而，应当理解，可加工第二半导体管芯202，以包括除3D堆叠存储器结构之外的集成电路。
在步骤62中，可在半导体管芯202的层中并且穿过半导体管芯202的层形成多层金属互连件和通孔220。这些金属互连件和通孔220可包括在第二晶圆200的顶部主平坦表面204和底部主平坦表面207之间延伸的TSV220a的图案。
如在晶圆100中一样，可通过在完成的TSV 220a的图案中穿过第二半导体管芯202蚀刻孔来形成晶圆200中的TSV 220a。然后，可将这些孔衬有屏障，并且可沉积晶种层。然后可将导电材料电镀到晶种层上。导电材料可包含铜，但也可使用其他合适的材料，诸如铝、锡、镍、金、掺杂多晶硅及其合金或其组合。
可在介电膜层226的顶部形成钝化层228。在步骤64中，可穿过钝化层228形成耦接到TSV 220a的接合焊盘208(图8和图9)。可在TSV220a上方蚀刻钝化层228，并且可在衬垫206上方形成接合焊盘208。如上文所述的焊盘108一样，接合焊盘208可由例如铜、铝及其合金形成，并且衬垫206可由例如钛/氮化钛叠堆(诸如，例如，Ti/TiN/Ti)形成，但在另外的实施方案中这些材料可有所不同。接合焊盘208和衬垫206一起可具有720nm的厚度，但在另外的实施方案中该厚度可更大或更小。
在步骤66中，可在背面研磨工艺中将存储器阵列晶圆200变薄，以限定晶圆200的第二主平坦(无源)表面207。在步骤68中，可在第二主平坦表面207上形成重新分布层(RDL)230，如图9所示。RDL 230可将所选择的接合焊盘208和TSV 220a以电气方式连接到分布在RDL 230上的微凸块232的图案。包括TSV 220a的金属互连件220可用于在存储器阵列212、管芯接合焊盘208和微凸块232之间传输信号和电流。
图7中在晶圆200上所示的半导体管芯202的数量和图案仅是示例性的。在另外的实施方案中，晶圆200可包括更多的存储器阵列半导体管芯202，并且可包括不同的图案。类似地，图8和图9包括半导体管芯202中的一个上的围绕半导体管芯202的外围的接合焊盘208的图案。然而，在另外的实施方案中，图8和图9中的第二半导体管芯202上的接合焊盘208的图案以及接合焊盘208的数量可有所不同。
存储器阵列晶圆200的管芯202可各自包括存储器单元的存储器结构，诸如存储器单元的阵列。存储器单元的阵列212(图9)可通过字线经由行解码器163(图5)并且通过位线经由列解码器166从控制器晶圆100上的控制器管芯102寻址。存储器阵列中的多个存储器元件可被配置为使得它们串联连接或使得每个元件可被单独访问。以非限制性示例的方式，NAND配置中的闪存存储器系统(NAND存储器)通常包含串联连接的存储器元件。NAND串是包括存储器单元和选择栅极晶体管的一组串联连接的晶体管的示例。
NAND存储器阵列可被配置为使得该阵列由存储器的多个串构成，其中串由共享单个位线并作为组被访问的多个存储器元件构成。另选地，存储器阵列的存储器元件可被配置为使得每个元件可被单独访问，例如NOR存储器阵列。NAND和NOR存储器配置是示例性的，并且存储器元件可以其他方式配置。
存储器阵列212可以是二维(2D)的或三维(3D)的。存储器阵列212可包括一个或多个存储器元件的阵列(也被称为存储器单元)。将3D存储器阵列布置成使得存储器元件占据多个平面或多个存储器设备级，从而形成三维结构(即，沿x、y和z方向，其中z方向基本上垂直于存储器阵列管芯102的主平坦表面204、207，并且x和y方向基本上平行于存储器阵列管芯102的主平坦表面204、207)。
根据本发明技术的方面，一个或多个存储器阵列晶圆200可与控制器晶圆100堆叠在一起形成半导体器件。现在将参考图10的流程图和图11至图16的视图解释此类半导体器件的结构和制造。
在步骤70中，可将第一存储器阵列晶圆200安装在临时载体上，诸如图11和12所示的临时载体250。临时载体250可以是例如金属、玻璃或硅。可使用临时粘合剂252将底部晶圆200粘附到临时载体250上，该临时粘合剂可以是激光/UV释放型膜、热释放型膜或机械释放型膜，以允许容易拆卸，如下所述。
在实施方案中，第一存储器阵列晶圆200可以是用于半导体器件中的唯一存储器阵列晶圆。然而，在另外的实施方案中，可在步骤72中将附加存储器阵列晶圆200堆叠在底部晶圆200上。在实施方案中，可存在n个总存储器阵列晶圆，其中n＝1、2、4、8、16、32或其他数量的晶圆。存储器阵列晶圆200可彼此对准和堆叠，使得一个晶圆的微凸块232安装在下一个较低晶圆的接合焊盘208的顶部上。
在将期望数量的存储器阵列晶圆200堆叠在临时载体上之后，可在步骤74中将控制器晶圆100安装在最上面的存储器阵列晶圆上，以形成半导体器件260，如图11所示。图11中的存储器晶圆200的数量仅是示例性的，并且可如上所述有所不同。
控制器晶圆100可与最上面的存储器阵列晶圆200对准并堆叠在其上，使得控制器晶圆100的微凸块132安装在最上面的存储器阵列晶圆200的接合焊盘208的顶部上。一旦已将所有晶圆100、200安装在临时载体250上，就可在步骤76中加热半导体器件260以回流微凸块132、232，以将晶圆和电连接固定在适当的位置。
晶圆100、200以这样的方式堆叠，使得一列存储器阵列管芯202彼此对准并与该列上方的控制器管芯102对准，该控制器管芯用作该列中的存储器阵列管芯202的控制器。图11示出了围绕一列存储器阵列管芯202和控制器管芯102的虚线框262。每个这样一列存储器阵列管芯202及其相关联的控制器管芯102在本文中可被称为存储器模块264。图12示出了来自半导体器件260的晶圆100、200的单个存储器模块264的分解横截面边缘视图。如本文所用，半导体器件可以是单个存储器模块264，或者半导体器件可以是所有一起的存储器阵列晶圆200和控制器晶圆100。
一旦将晶圆100、200安装在载体250上并在步骤76中附接，就可在步骤80中用环氧树脂或其他树脂或聚合物底部填充晶圆之间的任何空间。底部填充材料可作为液体施加，然后使其硬化为固态层。该底部填充步骤保护了晶圆之间的电连接，并且还将存储器模块列中的管芯彼此固定。各种材料可用作底部填充材料，但在实施方案中，底部填充材料可以是来自Henkel公司的Hysol环氧树脂，该公司在美国加利福尼亚州设有办事处。在另外的实施方案中，可省略底部填充步骤80。
接着是步骤82，可在步骤82中将载体250上的半导体器件260封装在外壳诸如模塑化合物中。模塑化合物可包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。此类模塑化合物可从例如Sumitomo公司和Nitto Denko公司获得，这两个公司的总部均在日本。设想了来自其他制造商的其他模塑化合物。模塑化合物可通过FFT(无流动薄)工艺或通过其他已知工艺(包括通过传递模塑或注射模塑技术)来施加。在另外的实施方案中，外壳可由其他材料形成，并且以其他方式围绕载体250上的半导体器件260形成。在另外的实施方案中，可省略封装步骤82。
在步骤84中，可通过溶解临时粘合剂252来移除载体250。可使用热量、机械力、化学物质、激光或UV光和/或通过其他方法来溶解临时粘合剂252。
在步骤86中，焊料球266可附接到晶圆100的上表面上的焊盘108，如图13所示。图13示出了包括焊料球266的单个存储器模块264，但焊料球266可设置在控制器晶圆100的上表面上的所有管芯的管芯接合焊盘108上。焊料球266可用于将半导体器件260以电气和机械方式耦接到主机设备300。主机设备300可以是例如耦接到数据中心内的服务器或主机的印刷电路板。应当理解，在另外的实施方案中，主机设备300可以是其他设备。
在实施方案中，半导体器件260由整个晶圆形成，以提供高容量存储设备，例如用于数据中心或其他高容量用途。在另外的实施方案中，可切割半导体器件260的晶圆100、200以提供单独的存储器模块264。如上所述，每个此类存储器模块264可包括封装在模塑化合物中的一列一个或多个存储器阵列管芯202和控制器管芯102。焊料球266可设置在控制器管芯102的管芯接合焊盘108上，以允许单独的存储器模块264附接到主机设备诸如印刷电路板上。可通过如激光器或锯片将半导体器件260切割成单独的存储器模块264。
图14是来自半导体器件260的单个存储器模块264的功能框图。如图所示，晶圆100中的每个控制器管芯102控制晶圆200中的一列n个存储器阵列管芯202。控制存储器阵列管芯202的操作的逻辑电路114在控制器管芯102中和与主机设备300交互的逻辑电路112集成在一起。
图11至图14示出了单通道存储器模块264，其中控制器管芯102控制单列存储器管芯202。图15和图16示出了包括四通道存储器模块264的半导体器件260的另选实施方案。如图15中的晶圆100、200的视图所示，该实施方案中的控制器晶圆100可包括比每个晶圆200中的存储器阵列管芯202更少的控制器管芯102。在该示例中，单个控制器管芯102可控制四列存储器阵列管芯202，如虚线框272所示。
如图16的功能框图所示，晶圆200上的存储器阵列管芯202可与上述的存储器阵列管芯相同。然而，在该实施方案中，每个通道存储器模块264的控制器管芯102可针对每个通道具有单独的存储器阵列逻辑电路114。单个ASIC逻辑电路112可与每个存储器阵列逻辑电路114交互，并且可如上所述与主机设备300交互。在另外的实施方案中，每个存储器模块264可以是n通道器件，其中控制器管芯102包括用于控制n列存储器阵列管芯202的n个存储器阵列逻辑电路114。
在上述实施方案中，将控制器晶圆100安装在半导体器件260的晶圆叠堆顶部。然而，在另外的实施方案中，控制器晶圆100可位于晶圆叠堆中的其他位置，诸如例如叠堆的底部。
总之，本发明技术的示例涉及被配置为与主机设备一起运行的半导体器件，该半导体器件包括：第一半导体管芯，该第一半导体管芯包括：被配置为与主机设备交互的ASIC逻辑电路，以及被配置为与存储器阵列交互的存储器阵列逻辑电路；以及耦接到第一半导体管芯的一组一个或多个第二半导体管芯，该一组一个或多个第二半导体管芯包括被配置为与第一半导体管芯的存储器阵列逻辑电路交互的存储器阵列。
在另一个示例中，本发明技术涉及被配置为与主机设备一起运行的半导体器件，该半导体器件包括：第一晶圆，该第一晶圆包括用于与主机设备交互的逻辑电路和用于与存储器阵列交互的逻辑电路中的至少一者；以及以物理和电气方式耦接到第一晶圆的多个第二晶圆，该多个第二晶圆包括多个存储器阵列。
在另一个示例中，本发明技术涉及被配置为与主机设备一起运行的半导体器件，该半导体器件包括：控制器晶圆，该控制器晶圆包括多个控制器半导体管芯，该多个控制器半导体管芯中的每个控制器半导体管芯包括：用于与主机设备交互的ASIC逻辑电路，用于与存储器阵列交互的存储器阵列逻辑电路；以及以物理和电气方式耦接到第一晶圆的多个存储器阵列晶圆，该多个存储器阵列晶圆各自包括具有存储器阵列的多个存储器阵列半导体管芯。
在另一个示例中，本发明技术涉及被配置为与主机设备一起运行的半导体器件，该半导体器件包括：第一半导体管芯，该第一半导体管芯包括：用于与主机设备交互的主机接口电路逻辑装置，以及用于与存储器阵列装置交互的存储器阵列电路逻辑装置；以及耦接到第一半导体管芯的一组一个或多个第二半导体管芯，该一组一个或多个第二半导体管芯包括用于存储数据的存储器阵列装置，该存储器阵列装置与第一半导体管芯的存储器阵列逻辑电路交互。
已出于例证和描述的目的提出本发明的上述具体实施方式。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地在各种实施方案中使用具有适合于所构想的特定用途的各种修改的本发明。本发明的范围旨在由所附权利要求书限定。

Claims (25)

1.一种被配置为与主机设备一起运行的半导体器件，所述半导体器件包括：
第一半导体管芯，所述第一半导体管芯包括：
被配置为与所述主机设备交互的ASIC逻辑电路，和
被配置为与存储器阵列交互的存储器阵列逻辑电路；和
耦接到所述第一半导体管芯的一组一个或多个第二半导体管芯，所述一组一个或多个第二半导体管芯包括被配置为与所述第一半导体管芯的所述存储器阵列逻辑电路交互的所述存储器阵列。
2.根据权利要求1所述的半导体器件，其中所述第一半导体管芯是第一晶圆的一部分，并且所述一组一个或多个第二半导体管芯是一个或多个第二晶圆的一部分，其中所述第一晶圆和所述一组一个或多个第二晶圆彼此堆叠。
3.根据权利要求1所述的半导体器件，其中所述第一半导体管芯是第一晶圆的一部分，并且所述一组一个或多个第二半导体管芯是一个或多个第二晶圆的一部分，其中所述第一晶圆和所述一组一个或多个第二晶圆彼此堆叠，并且所述第一半导体管芯和所述一组一个或多个第二半导体管芯在所述堆叠的晶圆中彼此成列对准。
4.根据权利要求1所述的半导体器件，其中所述半导体器件是单通道器件。
5.根据权利要求1所述的半导体器件，其中所述半导体器件是多通道器件。
6.根据权利要求5所述的半导体器件，其中所述第一半导体管芯包括用于所述多通道中的每个通道的存储器阵列逻辑电路。
7.根据权利要求1所述的半导体器件，其中所述第一管芯和所述一组一个或多个第二管芯通过所述第一管芯和所述一组一个或多个第二管芯中的硅通孔以电气方式耦接。
8.根据权利要求1所述的半导体器件，其中所述第一半导体管芯包括第一表面上的被配置为与所述主机设备的触点配合的一组接合焊盘，以及第二表面上的被配置为与所述一组一个或多个存储器阵列管芯的存储器阵列管芯的触点配合的一组导电凸块。
9.根据权利要求1所述的半导体器件，其中所述一组一个或多个第二半导体管芯包括三维堆叠的存储器结构，所述三维堆叠的存储器结构具有形成为层的存储器单元串。
10.一种被配置为与主机设备一起运行的半导体器件，所述半导体器件包括：
第一晶圆，所述第一晶圆包括用于与所述主机设备交互的逻辑电路和用于与存储器阵列交互的逻辑电路中的至少一者；和
以物理和电气方式耦接到所述第一晶圆的多个第二晶圆，所述多个第二晶圆包括多个存储器阵列。
11.根据权利要求10所述的半导体器件，其中所述第一晶圆包括用于与所述主机设备交互的逻辑电路和用于与存储器阵列交互的逻辑电路。
12.根据权利要求10所述的半导体器件，其中所述第一晶圆包括第一半导体管芯，所述第一半导体管芯包括用于与所述主机设备交互的逻辑电路和用于与存储器阵列交互的逻辑电路。
13.根据权利要求12所述的半导体器件，其中所述多个第二晶圆包括多个第二半导体管芯，所述多个第二半导体管芯各自包括存储器阵列。
14.根据权利要求12所述的半导体器件，其中所述第一半导体管芯和所述多个第二半导体管芯彼此成列堆叠。
15.根据权利要求10所述的半导体器件，其中所述第一晶圆和所述多个第二晶圆堆叠在彼此的顶部以形成晶圆的叠堆。
16.根据权利要求15所述的半导体器件，其中所述第一晶圆在所述晶圆的叠堆的顶部。
17.根据权利要求15所述的半导体器件，其中所述第一晶圆包括多个第一半导体管芯，并且所述多个第二晶圆各自包括多个第二半导体管芯，其中所述多个第一管芯中的第一管芯控制所述多个第二管芯中的一组第二管芯。
18.根据权利要求15所述的半导体器件，其中由所述第一管芯控制的一组第二管芯成列安装在所述第一管芯下方。
19.一种被配置为与主机设备一起运行的半导体器件，所述半导体器件包括：
控制器晶圆，所述控制器晶圆包括多个控制器半导体管芯，所述多个控制器半导体管芯中的每个控制器半导体管芯包括：
用于与所述主机设备交互的ASIC逻辑电路，
用于与存储器阵列交互的存储器阵列逻辑电路；和
以物理和电气方式耦接到所述第一晶圆的多个存储器阵列晶圆，所述多个存储器阵列晶圆各自包括具有存储器阵列的多个存储器阵列半导体管芯。
20.根据权利要求19所述的半导体器件，其中所述多个存储器阵列晶圆堆叠在彼此的顶部以形成晶圆的叠堆，其中相应存储器阵列晶圆的存储器阵列半导体管芯以物理和电气方式彼此成列接合。
21.根据权利要求20所述的半导体器件，其中所述控制器晶圆堆叠在所述晶圆的叠堆中的最上面的存储器阵列晶圆的上表面上。
22.根据权利要求20所述的半导体器件，其中所述多个控制器半导体管芯中的控制器半导体管芯以物理和电气方式耦接到一列存储器阵列半导体管芯，所述控制器半导体管芯控制所述一列存储器阵列半导体管芯。
23.根据权利要求19所述的半导体器件，还包括所述控制器晶圆的表面上的多个接合焊盘，以及所述多个接合焊盘上的多个焊料球，所述多个焊料球被配置为将所述半导体器件以电气和物理方式耦接到所述主机设备。
24.根据权利要求19所述的半导体器件，其中每个控制器管芯中的所述ASIC逻辑电路在每个控制器管芯的第一层中制造，并且所述存储器阵列逻辑电路在每个控制器管芯的与所述第一层不同的第二层中制造。
25.一种被配置为与主机设备一起运行的半导体器件，所述半导体器件包括：
第一半导体管芯，所述第一半导体管芯包括：
用于与主机设备交互的主机接口电路逻辑装置，和
用于与存储器阵列装置交互的存储器阵列电路逻辑装置；和
耦接到所述第一半导体管芯的一组一个或多个第二半导体管芯，所述一组一个或多个第二半导体管芯包括用于存储数据的所述存储器阵列装置，所述存储器阵列装置与所述第一半导体管芯的所述存储器阵列逻辑电路交互。
CN201910575708.2A 2019-06-28 2019-06-28 包括分叉存储器模块的高容量半导体器件 Pending CN112151527A (zh)

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