CN112151526A - 包括高速异质集成控制器和高速缓存的半导体设备 - Google Patents

包括高速异质集成控制器和高速缓存的半导体设备 Download PDF

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CN112151526A
CN112151526A CN201910575625.3A CN201910575625A CN112151526A CN 112151526 A CN112151526 A CN 112151526A CN 201910575625 A CN201910575625 A CN 201910575625A CN 112151526 A CN112151526 A CN 112151526A
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memory module
semiconductor
memory
memory array
semiconductor device
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CN201910575625.3A
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张亚舟
邱进添
周增钰
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Priority to CN201910575625.3A priority Critical patent/CN112151526A/zh
Priority to US16/818,290 priority patent/US11031378B2/en
Publication of CN112151526A publication Critical patent/CN112151526A/zh
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Abstract

本发明题为“包括高速异质集成控制器和高速缓存的半导体设备”。本发明公开了一种半导体设备，该半导体设备包括控制器管芯和存储器模块。控制器管芯可以是具有ASIC逻辑电路、存储器阵列逻辑电路和高速缓存结构的异质集成控制器管芯。在示例中，存储器模块可在面朝上或面朝下的配置中具有连续形成的硅通孔。

Description

包括高速异质集成控制器和高速缓存的半导体设备
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储器设备，诸如闪存存储卡，已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量，使得此类存储器设备理想地用于多种电子设备中，包括例如数字相机、数字音乐播放器、视频游戏控制器、PDA、蜂窝电话和固态驱动器。
近来，已使用具有形成为层的存储器单元串的3D堆叠存储器结构来提出超高密度存储器设备。一种此类存储设备有时被称为位成本可扩展(BiCS)体系结构。除了分层存储器单元之外，3D存储器设备还包括用于控制对存储器单元进行读取/写入的逻辑电路。常常使用互补金属氧化物半导体(CMOS)技术制造的逻辑电路通常可在半导体晶圆内的堆叠存储器层下方形成。
当前，在数据中心中对于将闪存存储器设备用作固态驱动器(SSD)存在显著的推动作用。随着3D存储器结构中的存储器层数的増加，以满足日益增长的数据中心存储器需求，将逻辑电路定位在3D存储器单元结构下方变得更困难。另外，针对存储器阵列形成而进行优化的工艺参数可不针对逻辑电路形成进行优化。例如，在多种制造步骤中，加热3D存储器单元结构是已知的。虽然对存储器单元结构是有利的，但加热可不利地影响逻辑电路的操作。
附图说明
图1是根据本技术的实施方案的用于形成包括控制器管芯的第一晶圆的流程图。
图2是根据本技术的实施方案的包括控制器管芯的第一半导体晶圆的第一主表面的顶视图。
图3是根据本技术的实施方案的第一半导体晶圆的控制器管芯的顶视图。
图4是根据本技术的实施方案的第一半导体晶圆的控制器管芯的横截面边视图。
图5是根据本技术的实施方案的控制器管芯的示意性框图。
图6是根据本技术的实施方案的用于形成包括存储器阵列管芯的第二晶圆的流程图。
图7是根据本技术的实施方案的包括存储器阵列管芯的第二半导体晶圆的第一主表面的顶视图。
图8是根据本技术的实施方案的第二半导体晶圆的存储器阵列管芯的顶视图。
图9是根据本技术的实施方案的第二半导体晶圆的存储器阵列管芯的横截面边视图。
图10是根据本技术的实施方案的用于形成“面朝上的”半导体设备的流程图。
图11至图13是示出根据本技术的实施方案的用于堆叠在一起的存储器阵列半导体管芯的制备的边视图。
图14至图15是示出根据本技术的实施方案的可在其上堆叠存储器阵列管芯的临时载体的制备的边视图。
图16至图19是示出根据本技术的实施方案的处于不同制造阶段的面朝上的存储器阵列晶圆堆叠的边视图。
图20是根据本技术的实施方案的完整的存储器阵列晶圆堆叠的透视图。
图21是根据本技术的实施方案的用于形成“面朝下的”半导体设备的流程图。
图22至图23是示出根据本技术的实施方案的处于不同制造阶段的面朝下的存储器阵列晶圆堆叠的边视图。
图24是半导体设备的分解边视图，该半导体设备包括用于安装在基板上的存储器阵列半导体管芯堆叠和控制器半导体管芯。
图25是根据本技术的实施方案的完整的半导体设备的边视图。
图26是根据本技术的实施方案的半导体设备的功能性框图。
具体实施方式
现在将参考附图来描述本技术，在实施方案中，该附图涉及半导体设备，该半导体设备包括一个或多个存储器阵列半导体管芯和控制器管芯，该控制器管芯包括异质集成ASIC逻辑电路、存储器阵列逻辑电路和高速缓存结构。控制器管芯的ASIC逻辑电路执行存储器管理并充当与主机设备的接口。控制器管芯的存储器阵列逻辑电路包括传感器放大器和外围功能，并且充当与存储器阵列晶圆管芯的存储器阵列的接口。高速缓存结构可定位在ASIC逻辑电路和存储器阵列逻辑电路之间以为有源数据提供临时存储。与访问存储器阵列半导体管芯相反，ASIC逻辑电路可从高速缓存结构读取有源数据和/或将有源数据写入高速缓存结构以缩短访问时间，减少延迟并改善输入/输出(I/O)。
在实施方案中，存储器阵列半导体管芯可使用“连续形成的”硅通孔(TSV)堆叠并电耦接至彼此，这意味着用于TSV的孔以单个工艺通过管芯堆叠中的存储器阵列半导体管芯中的每个存储器阵列半导体管芯来形成。存储器阵列堆叠可具有“面朝上的”TSV配置或“面朝下的”TSV配置。在面朝上的TSV配置中，电连接器可形成在管芯堆叠的底部处，并且在面朝上的TSV配置中，电连接器可形成在管芯堆叠的顶部处。与传统的TSV技术相比，面朝上的TSV配置和面朝下的TSV配置这两者省略了若干工艺，诸如针对每个晶圆的通孔蚀刻，晶种层沉积，在研磨晶圆的每个背面上的隔离层制造，两侧铜凸块制造，管芯级凸块接合和管芯间的底层填料填充。
应当理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是周密且完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下具体实施方式中，给出了许多具体细节，以便提供对本发明的周密理解。然而，对于本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为给定尺寸的±2.5％。
现在将参考图1的流程图以及图2至图5的视图解释包括控制器半导体管芯的第一晶圆的实施方案。在步骤50中，可以将第一半导体晶圆100处理成如图2至图4所示的多个第一半导体管芯102。这些第一半导体管芯102在本文中也可称为异质集成控制器管芯102，或简单地称为控制器管芯102。第一晶圆100在本文中也可称为异质集成控制器晶圆100，或简单地称为控制器晶圆100。第一半导体晶圆100可以晶圆材料的晶锭而开始，该晶圆材料可以是根据直拉法工艺(Czochralski(CZ))或浮区(FZ)工艺生长的单晶硅。然而，在另外的实施方案中，第一晶圆100可由其他材料并通过其他工艺形成。
控制器晶圆100可以从晶锭切割下来并在第一主平坦表面104和与该表面104相背对的第二主平坦表面107(图4)两者上抛光，以提供平滑表面。第一主表面104可经历各种处理步骤以将晶圆100分成相应第一半导体管芯102并在第一主表面104上和/或中形成相应第一半导体管芯102的集成电路。
具体地讲，在步骤50中，可在实施方案中处理第一半导体管芯102以包括在如图4所示的包括层116的介电基板中形成的ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构115。图4示出了代表第一晶圆100上的所有管芯102的单个管芯102的横截面。下文参考图5描述ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构115的更多细节，但一般来讲，ASIC逻辑电路112执行存储器管理并充当控制与主机设备交换数据的接口。存储器阵列逻辑电路114包括传感器放大器(SA)和外围(周边)电路，该外围电路用作切换模式接口电路以便将位线/字线解码到缓冲器，并且然后在存储器阵列(在下文中说明)和ASIC逻辑电路112之间传输数据。高速缓存结构115可为ASIC逻辑电路提供临时存储以缩短访问时间，减少延迟并改善输入/输出(I/O)。
在实施方案中，ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构115可各自在晶圆100的相应介电层116中来制造，其中高速缓存结构115夹置在ASIC逻辑电路112下方和存储器阵列逻辑电路114上方(从图4的角度来看)。逻辑电路112、114可使用CMOS技术来制造，但是在另外的实施方案中，逻辑电路可使用其他技术来制造。如在下文中说明的另外的实施方案中，控制器半导体管芯102可包括其他和/或附加集成电路。
在步骤52中，可在半导体管芯102的各层中并通过该各层形成多层金属互连件和通孔120。这些金属互连件和通孔120可电耦接ASIC逻辑电路112和存储器阵列逻辑电路114，以及ASIC逻辑电路112和高速缓存结构115。
可在介电膜层116的顶部上形成钝化层128。在步骤54中，接合焊盘108(图3和图4)可形成在钝化层128上，耦接至TSV 120a。接合焊盘108可在衬垫106之上形成。如本领域中已知的，接合焊盘108可由例如铜、铝及其合金形成，并且衬垫106可由例如钛/氮化钛堆叠(诸如例如，Ti/TiN/Ti)形成，但是这些材料在另外的实施方案中可变化。接合焊盘108和衬垫106一起可以具有720nm的厚度，但是在另外的实施方案中该厚度可以更大或更小。
在步骤56中，可在背面研磨工艺中使控制器晶圆100变薄以限定晶圆100的第二主平坦(无源)表面107。在步骤58中，可以在第二主平坦表面107上形成重新分布层(RDL)130，如图4所示。RDL 130可将接合焊盘108和TSV 120a中的选择的一者电连接到分布在RDL 130上的微凸块132的图案。微凸块132可为Cu、AgSn或可在两个晶圆之间接合的其他金属。微凸块132的高度可为约1μm至50μm，但是这些微凸块可比另外的实施方案中的那些薄或厚。金属互连件和通孔120可用于在管芯接合焊盘108和ASIC逻辑电路112之间、在ASIC逻辑电路112和高速缓存结构115之间、在ASIC逻辑电路112和存储器阵列逻辑电路114之间以及在存储器逻辑电路114和微凸块132之间传输信号和电流。
图2中的晶圆100上所示的半导体管芯102的数量和图案仅以举例的方式示出。在另外的实施方案中，晶圆100可包括更多的第一半导体管芯102，并且以不同的图案。相似地，图3和图4包括围绕半导体管芯102的周边的半导体管芯102中的一个半导体管芯上的接合焊盘108的图案。然而，图3和图4中的第一半导体管芯102上的接合焊盘108的图案以及接合焊盘108的数量在另外的实施方案中可变化。
图5是示出了控制器管芯102上的ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构的更多细节的示意性框图。ASIC逻辑电路112包括主机接口142，该主机接口连接到主机设备300并与该主机设备通信(图26)。在一个实施方案中，主机接口142提供PCIe接口。也可使用其他接口，诸如SCSI、SATA等。主机接口142还连接到片上网络(NOC)134。NOC是集成电路上的通信子系统。NOC可跨越同步和异步时钟域，或者使用非时钟的异步逻辑。NOC技术将网络理论和方法应用于片上通信，并且与常规总线和交叉开关互连相比带来了显著的改善。与其他设计相比，NOC提高了片上系统(SoC)的可扩展性以及复杂SoC的电源效率。NOC的导线和链路由许多信号共享。由于NOC中的所有链路可在不同的数据包上同时运行，因此实现了高水平的并行性。因此，随着集成子系统的复杂性不断增长，与先前的通信架构(例如，专用的点对点信号线、共享总线或具有桥的分段总线)相比，NOC提供增强的性能(诸如吞吐量)和可扩展性。连接到NOC 134并与该NOC通信的是处理器136、ECC引擎138、存储器接口140和DRAM控制器144。DRAM控制器144用于操作本地高速易失性存储器146(例如，DRAM)并与该本地高速易失性存储器通信。在其他实施方案中，本地高速易失性存储器146可为SRAM或另一种类型的易失性存储器。
ECC引擎138执行错误校正服务。例如，ECC引擎138根据实现的ECC技术执行数据编码和解码。在一个实施方案中，ECC引擎138是由软件编程的电路。例如，ECC引擎138可为可编程的处理器。在其他实施方案中，ECC引擎138是不具有任何软件的定制的专用硬件电路。在另一个实施方案中，ECC引擎138的功能由处理器136实现。
处理器136执行各种存储器操作。例如，存储器阵列模块(MM)是在处理器136上运行以用于执行编程、擦除、读取以及存储器管理过程的模块/过程。读取校准管理器(RC)是在处理器136上运行以用于执行读取校准过程的模块/过程。在一个实施方案中，读取校准管理器(RC)被实现为ECC引擎138的一部分。错误指示管理器(IOE)是在处理器136上运行以用于计算错误指示的模块/过程，该处理器用于校准读取参考水平。在一个实施方案中，误差指示管理器(IOE)被实现为ECC引擎138的一部分或为读取校准管理器(RC)的一部分。
在一个实施方案中，处理器136由固件编程，使得读取校准管理器(RC)和错误指示管理器(IOE)为固件/软件。在其他实施方案中，处理器136是不具有任何软件的定制的专用硬件电路。处理器136(单独地或与ECC引擎138一起)可执行读取参考水平的重新校准以确定更新的读取参考水平，包括动态且自适应地选择用于感测样本数据的测试读取参考水平。
处理器136还实现翻译模块(TM)，作为软件/固件过程或作为专用硬件电路。在许多系统中，使用与一个或多个存储器管芯相关联的物理地址将非易失性存储器向内寻址到存储系统，下文讨论。然而，主机系统将使用逻辑地址来寻址各种存储器位置。这使主机能够将数据分配给连续的逻辑地址，同时存储系统空闲下来按希望的那样在一个或多个存储器管芯的位置间存储数据。
存储器接口140与存储器阵列逻辑电路114通信。第二管芯202上的存储器阵列212(下文讨论)可由第一管芯102上的存储器阵列逻辑电路114控制。存储器阵列逻辑电路114可具有用于访问、控制和驱动存储器阵列的存储器元件以完成诸如编程和读取功能的电路。存储器阵列逻辑电路114与读取/写入电路168协作以在存储器阵列上执行存储器操作。读取/写入电路168可包括多个感测块(感测电路)，该多个感测块允许来自存储器晶圆上的存储器阵列管芯(在下文中说明)的存储器单元的一页被并行地读取或编程。
在实施方案中，逻辑电路114可包括状态机152、地址解码器154和功率控制模块156。状态机152提供存储器操作的芯片级控制。可提供存储区153以用于操作存储器阵列212，诸如用于不同行或其他存储器单元组的编程参数。这些编程参数可包括位线电压和验证电压。
地址解码器154提供主机设备或ASIC逻辑电路112使用的地址接口与解码器163和166使用的硬件地址之间的地址接口。功率控制模块156控制在存储器操作期间供应给字线和位线的功率和电压。该功率控制电路可包括用于3D配置中的字线层的驱动器、源极侧选择栅极、漏极侧选择栅极和源线。源极侧选择栅极是在NAND串的源极端处的栅极晶体管，并且漏极侧选择栅极是NAND串的漏极端处的晶体管。
高速缓存结构115可位于存储器阵列逻辑电路114中的ASIC逻辑电路112之间。高速缓存结构115可被组织为SRAM，但是在另外的实施方案中该高速缓存结构可具有其他配置。高速缓存结构115可充当存储器阵列212(在下文中说明)的磁盘高速缓存和/或处理器136的处理器高速缓存。可将数据存储在高速缓存结构115上和/或可将该数据读取到该高速缓存结构，而不是与存储器阵列进行交接。这提供了较短的访问时间，减少的延迟和改善的输入/输出(I/O)。ASIC逻辑电路112可从高速缓存结构115读取数据并将该数据写入该高速缓存结构。存储器阵列逻辑电路114还可从高速缓存结构115读取数据并将该数据写入该高速缓存结构。
根据本技术的方面，将上述ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构115集成到单个半导体管芯102中，并且将存储器阵列212(下文所述)分离到其自身的芯片上。然而，应当理解，在另外的实施方案中，ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存115的上述功能中的一些功能可卸载到存储器阵列半导体管芯上。在另外的实施方案中，可将附加组件和功能添加至控制器管芯102。
在第一晶圆100上形成控制器半导体管芯之前、之后或同时，可将第二半导体晶圆200处理成多个第二半导体管芯202。现在将参考图6的流程图以及图7至图9的视图解释晶圆200上的半导体管芯202的制造和操作。
图7示出了第二半导体晶圆200的顶视图。第二半导体晶圆200可以根据CZ、FZ或其他工艺生长的单晶硅的晶锭而开始。第二半导体晶圆200可以切割下来并在第一主表面204和与该表面204相背对的第二主表面207(图9)两者上抛光，以提供平滑表面。第一主表面204可经历各种处理步骤以将第二晶圆200分成相应第二半导体管芯202并在第一主表面204上和/或中形成相应第二半导体管芯202的集成电路。这些第二半导体管芯202在本文中也可称为存储器阵列管芯202，并且第二晶圆200在本文中也可称为存储器阵列晶圆200。
在一个实施方案中，可在步骤60中处理存储器阵列管芯202以包括形成在包括如图9所示的层224和226的介电基板中的存储器阵列212。图9示出了代表晶圆200上的所有管芯202的单个管芯202的横截面。下面提供了存储器阵列212的更多细节，但一般来讲，存储器阵列212可形成为具有形成为层的存储器单元串的3D堆叠存储器结构。然而，应当理解，可将第二半导体管芯202处理成包括除3D堆叠存储器结构之外的集成电路。
在步骤62中，可在半导体管芯202的介电层226中并通过该介电层形成多层金属互连件和通孔220。可在介电膜层226的顶部上形成钝化层228。在步骤64中，接合焊盘208(图8和图9)可穿过钝化层228形成，耦接至金属互连件和通孔220。接合焊盘208可在衬垫206之上形成。如上所述，对于焊盘108而言，接合焊盘208可由例如铜、铝及其合金形成，并且衬垫206可由例如钛/氮化钛堆叠(诸如例如，Ti/TiN/Ti)形成，但是这些材料在另外的实施方案中可变化。接合焊盘208和衬垫206一起可以具有720nm的厚度，但是在另外的实施方案中该厚度可以更大或更小。
图7中的晶圆200上所示的半导体管芯202的数量和图案仅以举例的方式示出。在另外的实施方案中，晶圆200可包括更多的存储器阵列半导体管芯202，并且以不同的图案。相似地，图8和图9包括围绕半导体管芯202的周边的半导体管芯202中的一个半导体管芯上的接合焊盘208的图案。然而，图8和图9中的第二半导体管芯202上的接合焊盘208的图案以及接合焊盘208的数量在另外的实施方案中可变化。
存储器阵列晶圆200的管芯202可各自包括存储器单元的存储器结构，诸如存储器单元阵列。存储器单元阵列212(图9)能够通过字线经由行解码器163(图5)以及通过位线经由列解码器166从控制器晶圆100上的控制器管芯102寻址。存储器阵列中的多个存储器元件可以被配置为使得该多个存储器元件串联连接或使得每个元件是能够单独访问的。以非限制性示例的方式，NAND配置中的闪存存储器系统(NAND存储器)通常包含串联连接的存储器元件。NAND串是包括存储器单元和选择栅极晶体管的一组串联连接的晶体管的示例。
NAND存储器阵列可被配置为使得该阵列由存储器的多个串构成，其中串由共享单个位线并作为组被访问的多个存储器元件构成。另选地，存储器阵列的存储器元件可被配置为使得每个元件是能够单独访问的，例如，NOR存储器阵列。NAND和NOR存储器配置是示例性的，并且存储器元件可以其他方式配置。
存储器阵列212可为二维(2D)或三维(3D)。存储器阵列212可包括一个或多个存储器元件阵列(也称为存储器单元)。布置3D存储器阵列，使得存储器元件占据多个平面或多个存储器设备级，从而形成三维结构(即，在x方向、y方向和z方向上，其中z方向基本上垂直于存储器阵列管芯202的主平坦表面204、207，并且x方向和y方向基本上平行于该存储器阵列管芯的这些主平坦表面)。
根据本技术的方面，一个或多个存储器阵列晶圆200可堆叠在一起以形成存储器阵列管芯堆叠。首先将参考图10的流程图和图11至图20的视图来描述包括面朝上的TSV存储器阵列管芯堆叠的第一实施方案。然后将参考图21的流程图和图22至图23的视图来描述包括面朝下的TSV存储器阵列管芯堆叠的第二实施方案。
在步骤70中，可通过将介电膜沉积在有源表面204之上以嵌入接触焊盘108来处理多个存储器阵列晶圆200以用于堆叠。介电膜可以是氮化硅，但是在另外的实施方案中，该介电膜可以是其他材料。步骤70还可包括可执行CMP抛光工艺以进行表面平坦化。图11示出了包括有源服务204上的接合焊盘208的存储器阵列晶圆200的半导体管芯202，并且图12示出了在介电膜层240的施加和抛光之后的有源表面204。在步骤72中，可在背面研磨工艺中使存储器阵列晶圆200变薄以限定晶圆200的第二主平坦(无源)表面207，如图13所示。
在步骤70和步骤72中制备第二晶圆200之前、期间或之后，也可在步骤74和步骤76中制备临时载体。图14中示出了临时载体250的一个示例。临时载体250可以例如是金属、玻璃或硅。在步骤74中，可在临时载体250的主表面255上形成金属接触焊盘254。接触焊盘254可通过光刻印刷工艺、电镀工艺或其他已知工艺形成。在步骤76中，可将剥离膜256施加到载体250的主表面255上，如图15所示。剥离膜256可为大致平面的并且可至接触焊盘254的高度。在步骤76中，可将剥离膜256固化至B阶段。膜256可为临时粘合剂，其可例如使用激光/紫外光、加热、化学物质和/或力来溶解或移除，如在下文中说明。
在步骤78中，可将多个(n个)存储器阵列晶圆200(包括膜240)堆叠在载体250的主表面255的顶部上，如图16所示。在实施方案中，可存在n个总存储器阵列晶圆，其中n＝1、2、4、8、16、32或其他数量的晶圆。存储器阵列晶圆200可彼此对准并堆叠，使得相应晶圆200的存储器阵列半导体管芯202彼此对准。如上所述，图16中的存储器晶圆200的数量仅以举例的方式示出，并且在可变化。
一旦所有晶圆200已安装在载体250上，晶圆200就可以在步骤82中彼此永久性地接合。这种永久性接合将晶圆彼此物理地附接。可使用各种已知的粘结工艺将晶圆永久性地彼此接合，诸如熔合接合和混合接合。
一旦接合，TSV 264可在步骤84至步骤88中穿过晶圆中的每个晶圆来形成，以电耦接至图17所示的相应晶圆的接合焊盘208。根据本技术的方面，TSV 264可通过晶圆叠层250的管芯202“连续形成”，这意味着用于TSV 264的孔在晶圆堆叠在一起之后通过堆叠250中的管芯中的每个管芯以单个工艺来形成。具体地讲，可通过在步骤84中在成品TSV 264的图案中蚀刻穿过存储器阵列半导体管芯202的孔来形成TSV 264。孔的硅侧壁也可在步骤84中被蚀刻。硅侧壁蚀刻结构可以为两个相邻管芯之间的铜填充(下面说明)提供强钉扎效应，以提高信号传输的可靠性。然后可在步骤86中，蚀刻孔衬有隔离层以防止扩散。
在步骤88中，然后可电镀蚀刻孔，并且该蚀刻孔填充有导电材料以形成TSV 264。导电材料可包括铜，但也可使用其他合适的材料，诸如铝、锡、镍、金、掺杂多晶硅、以及它们的合金或它们的组合。本技术的一个特征是可省略常规形成于隔离层之上的晶种层。具体来讲，如下所述，蚀刻的孔可以从底部向上电镀和/或填充导电材料，诸如铜。在重力作用下从底部向上填充允许省略种子层。
在该面朝上的配置中，聚酰亚胺膜268可接着在步骤90中的晶圆堆叠260的上表面上形成，如图18所示。提供聚酰亚胺膜268以密封和保护晶圆堆叠260的上表面。在步骤91中，可如图19所示移除载体250。在步骤92中，可将剥离膜256溶解或以其他方式移除，如图19所示。如图所示，最初形成于载体250上的接触焊盘254被传送到管芯堆叠260的下表面262。随着剥离膜256的移除，接触焊盘254被暴露。
如上所述，在制造的此时，存储器阵列管芯202仍然是在堆叠260中这些存储器阵列管芯的相应晶圆200的一部分，例如如图20所示。在步骤93中，可对堆叠260进行分割以提供单个存储器模块266。每个存储器模块266可为存储器阵列管芯202的堆叠并对齐的列，如图20中的虚线框265所示。晶圆堆叠260可通过沿切口线269切割而进行分割，这些切口线中的两个切口线由图20中的虚线指示。晶圆堆叠可例如通过激光、锯片、喷水或其他方法切割。
图11至图20示出了面朝上的存储器模块266的制造，其中接触焊盘254用于存储器模块266在模块的底部表面262上的外部电连接。图21至图23示出了面朝下的存储器模块266的制造的另一个实施方案，其中用于存储器模块266的外部电连接的电触点位于模块的上表面上。
参见图21的流程图，面朝下的存储器模块266可在步骤70至步骤88中以与面朝上的存储器模块相同的方式来形成。具体地讲，多个存储器阵列晶圆200可堆叠在载体250上，并且TSV 264可如上所述形成到图17所示的制造阶段。然后，在步骤94中，可将导电层施加到晶圆堆叠的上表面272上并将该导电层显影成图案。接着，在步骤95中，接触焊盘270可被电镀到显影图案上，如图22所示。接触焊盘270可形成在接合焊盘208之上并且电耦接至该接合焊盘。
在步骤96中，可移除载体250，如图23所示。然后，可将聚酰亚胺膜276施加到存储器阵列晶圆堆叠260的底部表面。提供聚酰亚胺膜276以密封和保护晶圆堆叠260的下表面。然后，可如上所述对存储器阵列晶圆堆叠260进行分割以提供单个完整的存储器模块266。
在根据上述实施方案中的任一个实施方案完成存储器模块266时，存储器模块266可与控制器管芯102一起安装在基板278上，如图24和图25所示。面朝上的TSV配置可被降低到控制器管芯102上(面朝下的TSV配置可被反转，并且然后降低到控制器管芯102上)。存储器模块266的接触焊盘254可物理地接合并电接合到接触焊盘108。
然后，可将存储器模块266和控制器管芯102安装在基板278上，其中控制器管芯102的微凸块132物理地耦接并电耦接至基板的接触焊盘282，以提供如图25所示的完整的半导体设备284。然后可通过基板278的表面上的焊料球286将设备284安装到主机设备300(图26)，诸如例如印刷电路板。半导体设备284可在附连到主机设备300之前任选地包封在保护性模塑中。
图26是根据本技术的实施方案的半导体设备284的功能性框图。如图所示，控制器管芯102控制存储器模块266中的一列n个存储器阵列管芯202。将ASIC逻辑电路112、存储器阵列逻辑电路114和高速缓存结构115中的每一者制造成单个异质集成半导体管芯102。在图26中，存储器逻辑阵列114被分离成存储器阵列逻辑电路和存储器阵列模拟电路，其中高速缓存结构115在ASIC逻辑电路与存储器阵列逻辑电路和模拟电路两者之间进行交接。ASIC逻辑电路112经由主机接口与主机设备300通信。ASIC逻辑电路112和存储器阵列逻辑电路114经由存储器阵列接口与存储器模块266通信。
概括地说，本技术的一个示例涉及一种半导体设备，该半导体设备被配置为与主机设备一起操作，包括：第一半导体管芯，该第一半导体管芯包括：ASIC逻辑电路，该ASIC逻辑电路被配置为与主机设备进行交接；存储器阵列逻辑电路，该存储器阵列逻辑电路被配置为与存储器阵列进行交接；和高速缓存结构，该高速缓存结构被配置为在第一半导体管芯内提供存储；和一组一个或多个第二半导体管芯，该一组一个或多个第二半导体管芯耦接至第一半导体管芯并且包括被配置为与第一半导体管芯的存储器阵列逻辑电路进行交接的存储器阵列。
在另一个示例中，本技术涉及一种半导体设备，该半导体设备被配置为与主机设备一起操作，包括：第一半导体管芯，该第一半导体管芯包括：ASIC逻辑电路，该ASIC逻辑电路被配置为与主机设备进行交接；存储器阵列逻辑电路，该存储器阵列逻辑电路被配置为与存储器阵列进行交接；和高速缓存结构，该高速缓存结构被配置为在第一半导体管芯内提供存储；存储器模块，该存储器模块耦接至第一半导体管芯并且包括具有存储器阵列的多个第二半导体管芯；和多个硅通孔，该多个硅通孔穿过存储器模块连续形成并且包括电导体，该电导体将多个第二半导体管芯彼此电耦接。
在另一个示例中，本技术涉及一种半导体设备，该半导体设备被配置为与主机设备一起操作，包括：第一半导体管芯，该第一半导体管芯包括：用于与主机设备进行交接的ASIC逻辑电路装置，用于与存储器阵列进行交接的存储器阵列逻辑电路装置，和用于在第一半导体管芯内提供存储的高速缓存装置；存储器模块，该存储器模块耦接至第一半导体管芯并且包括具有存储器阵列的多个第二半导体管芯；和电连接器装置，该电连接器装置穿过存储器模块连续形成并且包括电导体，用于将多个第二半导体管芯彼此电耦接。
已出于例证和描述的目的提出本发明的上述具体实施方式。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地在各种实施方案中使用具有适合于所构想的特定用途的各种修改的本发明。本发明的范围旨在由所附权利要求书限定。

Claims (20)

1.一种被配置为与主机设备一起操作的半导体设备，包括：
第一半导体管芯，所述第一半导体管芯包括：
ASIC逻辑电路，所述ASIC逻辑电路被配置为与所述主机设备进行交接，
存储器阵列逻辑电路，所述存储器阵列逻辑电路被配置为与存储器阵列进行交接，和
高速缓存结构，所述高速缓存结构被配置为在所述第一半导体管芯内提供存储；和
一组一个或多个第二半导体管芯，所述一组一个或多个第二半导体管芯耦接至所述第一半导体管芯并且包括被配置为与所述第一半导体管芯的所述存储器阵列逻辑电路进行交接的所述存储器阵列。
2.根据权利要求1所述的半导体设备，其中所述ASIC逻辑电路、所述高速缓存结构和所述存储器阵列逻辑电路设置在所述第一半导体管芯的连续介电层中。
3.根据权利要求1所述的半导体设备，其中所述高速缓存结构为所述ASIC逻辑电路提供临时输入/输出存储。
4.根据权利要求1所述的半导体设备，其中所述高速缓存结构为所述存储器阵列逻辑电路提供临时输入/输出存储。
5.根据权利要求1所述的半导体设备，其中所述一组一个或多个第二管芯包括存储器模块，所述存储器模块具有通过硅通孔彼此电耦接的多个半导体管芯。
6.根据权利要求5所述的半导体设备，其中所述硅通孔是连续形成的。
7.根据权利要求6所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝上的存储器模块，所述面朝上的存储器模块在所述存储器模块的与所述第一表面相背对的第二表面上具有接触焊盘。
8.根据权利要求6所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝下的存储器模块，所述面朝下的存储器模块在所述存储器模块的所述第一表面上具有接触焊盘。
9.根据权利要求1所述的半导体设备，其中所述第一半导体管芯包括位于第一表面上的一组接合焊盘和位于第二表面上的一组导电凸块，所述一组接合焊盘被配置为与所述主机设备的触点配合，所述一组导电凸块被配置为与所述一组一个或多个存储器阵列管芯中的存储器阵列管芯的触点配合。
10.根据权利要求1所述的半导体设备，其中所述一组一个或多个第二半导体管芯包括三维堆叠存储器结构，所述三维堆叠存储器结构具有形成为层的存储器单元串。
11.一种被配置为与主机设备一起操作的半导体设备，包括：
第一半导体管芯，所述第一半导体管芯包括：
ASIC逻辑电路，所述ASIC逻辑电路被配置为与所述主机设备进行交接，
存储器阵列逻辑电路，所述存储器阵列逻辑电路被配置为与存储器阵列进行交接，和
高速缓存结构，所述高速缓存结构被配置为在所述第一半导体管芯内提供存储；
存储器模块，所述存储器模块耦接至所述第一半导体管芯并且包括具有所述存储器阵列的多个第二半导体管芯；和
多个硅通孔，所述多个硅通孔穿过所述存储器模块连续形成并且包括电导体，所述电导体将所述多个第二半导体管芯彼此电耦接。
12.根据权利要求11所述的半导体设备，其中所述存储器模块中的所述多个第二半导体管芯在列中彼此堆叠。
13.根据权利要求11所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝上的存储器模块，所述面朝上的存储器模块在所述存储器模块的与所述第一表面相背对的第二表面上具有接触焊盘。
14.根据权利要求11所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝下的存储器模块，所述面朝下的存储器模块在所述存储器模块的所述第一表面上具有接触焊盘。
15.根据权利要求11所述的半导体设备，其中所述ASIC逻辑电路、所述高速缓存结构和所述存储器阵列逻辑电路设置在所述第一半导体管芯的连续层中。
16.根据权利要求11所述的半导体设备，其中所述高速缓存结构为所述ASIC逻辑电路提供临时输入/输出存储。
17.根据权利要求11所述的半导体设备，其中所述高速缓存结构为所述存储器阵列逻辑电路提供临时输入/输出存储。
18.一种被配置为与主机设备一起操作的半导体设备，包括：
第一半导体管芯，所述第一半导体管芯包括：
用于与所述主机设备进行交接的ASIC逻辑电路装置，
用于与存储器阵列进行交接的存储器阵列逻辑电路装置，和
用于在所述第一半导体管芯内提供存储的高速缓存装置；
存储器模块，所述存储器模块耦接至所述第一半导体管芯并且包括具有所述存储器阵列的多个第二半导体管芯；和
电连接器装置，所述电连接器装置穿过所述存储器模块连续形成并且包括电导体，用于将所述多个第二半导体管芯彼此电耦接。
19.根据权利要求18所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝上的存储器模块，所述面朝上的存储器模块在所述存储器模块的与所述第一表面相背对的第二表面上具有接触焊盘。
20.根据权利要求18所述的半导体设备，其中所述存储器模块的所述多个半导体管芯中的每个半导体管芯包括面向所述存储器模块的第一表面的接合焊盘，所述存储器模块包括面朝下的存储器模块，所述面朝下的存储器模块在所述存储器模块的所述第一表面上具有接触焊盘。
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