TWI741015B - 積體電路裝置及組裝其之方法 - Google Patents

積體電路裝置及組裝其之方法 Download PDF

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TWI741015B
TWI741015B TW106129247A TW106129247A TWI741015B TW I741015 B TWI741015 B TW I741015B TW 106129247 A TW106129247 A TW 106129247A TW 106129247 A TW106129247 A TW 106129247A TW I741015 B TWI741015 B TW I741015B
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connection
substrate
die
memory die
connection component
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TW106129247A
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TW201826485A (zh
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艾朗 維盧派克夏 格達
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美商奇異電器公司
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
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Abstract

描述一種積體電路(IC)裝置。該IC裝置包含一基板。包含穿過其之一腔之一連接組件經附接至該基板。一記憶體晶粒經定位於該連接組件之該腔中，且經電耦合至該基板。一邏輯晶粒延伸在該記憶體晶粒及該連接組件的至少一部分上方，且經電耦合至該連接組件及該記憶體晶粒。該連接組件經形成不含有貫穿矽通路，且係經由焊線電耦合至該基板。

Description

積體電路裝置及組裝其之方法
本文中所揭示之標的物大致係關於積體電路裝置，且更特定言之，係關於包含一中介層之三維堆疊積體電路裝置。 在習知三維(3D)堆疊積體電路(IC)封裝中，半導體裝置經堆疊並彼此垂直地互連，其實現一更小IC封裝尺寸並促進經增加電效能(例如，經增加頻寬、經減少電力消耗等)。至少一些已知3D堆疊IC裝置歸因於需要連接至外部電路之邏輯裝置之互連之經增加數目而包含放置於一邏輯裝置之頂部上之一記憶體裝置或一記憶體堆疊。然而，通常，邏輯裝置已經增加功率耗散，且因此，相較於記憶體裝置而已經增加作業溫度。因此，就至少一些3D堆疊IC裝置而言，將邏輯裝置定位於記憶體裝置與3D堆疊IC裝置之一基板之間並非是一熱有利配置。 另外，至少一些已知3D堆疊IC裝置包含形成在邏輯裝置中之貫穿矽通路(TSV)以促進將記憶體裝置電連接至外部電路，其增加邏輯裝置之製造之複雜度及成本。在至少一些已知3D堆疊IC裝置中，邏輯裝置與記憶體之間之互連及外部電路之數目將需要增加記憶體裝置中之TSV之數目，藉此減小記憶體裝置面積之有效使用及成本效益。
在一項態樣中，提供一種積體電路(IC)裝置。該IC裝置包含一基板。該IC裝置亦包含一連接組件，該連接組件包含穿過其界定之一腔。該連接組件經耦合至基板。另外，該IC裝置包含定位於該腔中之至少一個記憶體晶粒。該至少一個記憶體晶粒經電耦合至該基板。此外，該IC裝置包含延伸在該至少一個記憶體晶粒上方之一邏輯晶粒及該連接組件之至少一部分。該至少一個邏輯晶粒經電耦合至該連接組件及該至少一個記憶體晶粒。該連接組件不含有貫穿矽通路，且經由至少一個焊線電耦合至該基板。 在另一態樣中，提供另一積體電路(IC)裝置。該IC裝置包含具有一第一主動表面之一基板。該第一主動表面包含複數個基板焊墊。該IC裝置亦包含經耦合至該基板之該第一主動表面之複數個連接組件。該複數個連接組件經配置以在該複數個連接組件之間界定一腔。該複數個連接組件之各連接組件包含與該基板之該第一主動表面相對之一第二主動表面。各第二主動表面包含至少一個連接組件焊墊。此外，該IC裝置包含定位於該腔內及經電耦合至該基板之該第一主動表面之至少一個記憶體晶粒。另外，該IC裝置包含經耦合至各第二主動表面及該至少一個記憶體晶粒之一邏輯晶粒。該複數個連接組件不含有貫穿矽通路。此外，該至少一個連接組件焊墊之各者經電耦合至該複數個基板焊墊之一基板焊墊。 在又另一態樣中，提供一種形成具有一3D封裝結構之一IC裝置之方法。該方法包含形成不含有貫穿矽通路之一連接組件。該連接組件包含穿過其界定之一腔及包含一連接組件焊墊之一重佈佈線層。該方法亦包含將該連接組件耦合至一基板。該基板包含一基板焊墊。此外，該方法包含將至少一個記憶體晶粒耦合至該基板使得記憶體晶粒定位於該腔內。此外，該方法包含將一邏輯晶粒上方在該記憶體晶粒及該連接組件之至少一部分延伸，且將該邏輯晶粒電耦合至該記憶體晶粒及該連接組件之該至少一部分。另外，該方法包含將該連接組件焊墊電耦合至該基板焊墊。
在下列說明書及申請專利範圍中，將對數個術語作出參考，該等術語應經定義以具有以下含義。 除非本文另有明確規定，否則單數形式的「一」、「一個」及「該」包含複數參考。 「可選」或「視情況」意謂：隨後所描述之事件或情況可發生或可不發生，且描述包含其中發生該事件之例項及其中不發生該情況之例項。 如本文中整個說明書及申請專利範圍所使用，近似語言可被應用於修改可在不導致相關之基本功能中之一改變的情況下獲准變動的任何數量表示。相應地，藉由一術語或該等術語(諸如「約」、「近似」及「實質上」)修改之一值不限於特定精確值。在至少一些例項中，近似語言可對應於用於量測值之一儀器之精確度。此處且遍及說明書及申請專利範圍，可組合及/或互換範圍限制；除非文本或語言另有指示，否則識別此等範圍且包含其中包含之全部子範圍。 本文中所描述之裝置及方法藉由組態一被動連接組件以圍繞經連接至且經定位於一邏輯晶粒與一封裝基板之間之一記憶體晶粒來促進增加一積體電路裝置的效率。邏輯晶粒及記憶體晶粒經彼此耦合且經由焊料微凸塊直接通訊。邏輯晶粒係經由經由焊料微凸塊定位於記憶體晶粒周圍之被動連接組件而電耦合至封裝基板。提供具有貫穿矽通路(TSV)之記憶體晶粒，以實現邏輯晶粒與封裝基板之間的通訊。另外，記憶體晶粒係經由焊料微凸塊直接耦合至基板封裝。因而，本文中所描述之實施例藉由在遠離封裝基板之記憶體晶粒(較低功率耗散組件)上方定位邏輯晶粒(較高功率耗散組件)來提供增加熱耗散或邏輯晶粒之效率。此促進邏輯晶粒之經增加熱管理及經增加效能。另外，所描述之實施例減少用於提供邏輯晶粒中之TSV的需要，以使記憶體晶粒能夠直接連接至封裝基板。此藉由減小邏輯晶粒之尺寸及複雜度來促進減少邏輯晶粒之製造成本。 圖1係形成為一單一三維(3D)封裝結構之一先前技術積體電路(IC)裝置100之一示意前視圖。一典型3D封裝結構包含經安裝於另一晶粒之頂部上之至少一個晶粒，其中下晶粒具有TSV以允許上晶粒與下晶粒及封裝基板通訊。例如，如圖1中所展示，IC裝置100經製造為包含一邏輯晶粒102及至少一個記憶體晶粒104之一單一3D封裝。邏輯晶粒102及記憶體晶粒104係經由焊料微凸塊110直接耦合至彼此且垂直地整合(即，記憶體晶粒104經定位於實質上覆蓋邏輯晶粒102之邏輯晶粒102的頂部上)。邏輯晶粒102係經由複數個焊料微凸塊112耦合至一封裝基板108。邏輯晶粒102包含使記憶體晶粒104的至少一些連接部能夠經由焊料微凸塊112耦合至封裝基板108的複數個TSV 106。在相較於通常在堆疊封裝結構中發現的焊線減小TSV 106的長度時，如本文中所描述，TSV 106增加邏輯晶粒102的尺寸及複雜度。此導致與邏輯晶粒102相關聯之一經增加製造成本。另外，因為由邏輯晶粒102產生之熱被傳輸至記憶體晶粒104，所以減小IC裝置100的熱效率。此外，熱不能直接自邏輯晶粒102容易地移除。 圖2係形成為一單一2.5維( 2.5D)封裝結構之一先前技術IC裝置200之一示意前視圖。一典型2.5D封裝結構包含經安裝緊靠在一單一平面中之另一晶粒之至少一個晶粒，其中一中介層放置於中介層具有將金屬層連接於其上及下表面上之TSV之封裝基板與兩個晶粒之間。例如，如圖2中所展示，IC裝置200經製造為包含一邏輯晶粒202 (至少一個記憶體晶粒204 )及一中介層206之一單一2.5D封裝。邏輯晶粒202及記憶體晶粒204在一並排配置中各別地經由焊料微凸塊208及210直接耦合至中介層206。中介層206包含實現邏輯晶粒202與記憶體晶粒204之間之直接通訊之電路(未展示)。中介層206通常自矽製造，儘管亦使用其他材料(諸如玻璃、陶瓷及/或有機材料)。中介層206包含使邏輯晶粒202及記憶體晶粒204之至少一些連接能夠經由焊料微凸塊216耦合至一封裝基板214之複數個TSV 212。然而，並排2.5D封裝結構導致IC裝置200之一經增加尺寸。另外，相較於圖1中所展示之3D封裝結構增加邏輯晶粒202與記憶體晶粒204之間之連接路徑之長度，其導致IC裝置200之額外低效率。另外，中介層206包含用於邏輯晶粒202及記憶體晶粒204之TSV 212及連接電路，其導致與IC裝置200相關聯之一經增加製造成本。 圖3係形成為一單一3D封裝結構之一例示性IC裝置300之一剖視圖。圖4係在圖3中所展示之IC裝置300之一示意平面圖。參考圖3及圖4，IC裝置300經製造為一單一3D封裝且包含一封裝基板302、一中介層組件或連接組件304、至少一個邏輯晶粒308及至少一個記憶體晶粒312。連接組件304經由複數個焊料微凸塊306耦合至封裝基板302。至少一個邏輯晶粒308經定位於相對封裝基板302之連接組件304上。邏輯晶粒308經由複數個焊料微凸塊310直接耦合至連接組件304。在一些實施例中，邏輯晶粒308係一單一晶片，且在其他實施例中，邏輯晶粒308係一多晶片(例如，一並排晶片配置)封裝。邏輯晶粒308包含例如(且不限於)一處理器、處理裝置或控制器(諸如一通用中央處理單元(CPU)、一圖形處理單元(GPU)、一加速處理單元(APU)、一微控制器、一精簡指令集電腦(RISC)處理器、一特定應用積體電路(ASIC)、一可程式化邏輯電路(PLC)、一可程式化邏輯單元(PLU)、一場可程式化閘陣列(FPGA)、閘陣列、一數位信號處理(DSP)裝置及/或使IC裝置300能夠用作本文中所描述之任何其他邏輯電路或處理裝置)。 在例示性實施例中，連接組件304經形成為圍繞邏輯晶粒308之一周邊延伸且具有界定之一腔324之一單一組件。腔324經由自連接組件304之一大致中心部分移除材料而形成於其中。如圖4中所展示，連接組件304大致係矩形形狀並界定一大致矩形形狀腔324。在連接組件304經展示具有一大致矩形形狀時，替代地，連接組件304具有使連接組件304能夠用作本文中所描述之任何形狀。另外，腔324可在連接組件304中之任何位置中形成且不需要大致中心定位。 此外，在例示性實施例中，連接組件304由矽製造且包含一或多個重佈佈線層334。替代地，由使連接組件304能夠用作本文中所描述之任何材料(例如(且不限於)玻璃、陶瓷、有機材料、鍺、砷化鎵、磷化銦及碳化矽)製造連接組件304。重佈佈線層334促進邏輯晶粒308之電連接點或接腳(未展示) (例如對應於焊料微凸塊310之位置)可用於連接組件304上之其他位置。因此，重佈佈線層334促進繞線邏輯晶粒308之電連接點或接腳至連接組件304上之有利位置以促進使自邏輯晶粒308上之不同位置能夠接合至連接組件304上之類似及/或鄰近位置，藉此簡化IC裝置300之總成。 此外，在例示性實施例中，連接組件304係一被動中介層。在一些實施例中，例如(且不限於)連接組件304不包含僅包含一或多個重佈佈線層334之額外電氣組件。在其他實施例中，連接組件304包含嵌入於其中及/或在其上形成之一或多個積體被動裝置(IPD) (例如(且不限於)電阻器、電容器、電感器或使連接組件304能夠用作本文中所描述之任何其他被動電子裝置)。因此，在例示性實施例中，連接組件304不包含主動電氣組件(例如(且不限於)電晶體、信號放大器、信號濾波器或任何其他主動電氣組件)。替代地，在一些實施例中，連接組件304係一主動中介層並包含嵌入於其中及/或在其上形成之一或多個主動電氣組件。 參考圖3及圖4，在例示性實施例中，記憶體晶粒312表示一經堆疊的或多個晶片配置。替代地，記憶體晶粒312可為一單一晶片及/或一非堆疊晶片配置。在例示性實施例中，邏輯晶粒308及記憶體晶粒312經由焊料微凸塊314直接彼此耦合且經垂直地整合(即，記憶體晶粒312相對於邏輯晶粒308經垂直地定位 )。在替代實施例中，邏輯晶粒308及記憶體晶粒312使用使IC裝置300能夠用作本文中所描述之任何連接方法(例如(且不限於)經由擴散接合、共晶接合、熱壓縮接合及導電聚合物之使用)彼此直接耦合。在例示性實施例中，記憶體晶粒312經定位於邏輯晶粒308之下方。更特定言之，記憶體晶粒312經垂直地定位於邏輯晶粒308與封裝基板302之間使得邏輯晶粒308上覆記憶體晶粒312。記憶體晶粒312經定位於連接組件304之腔324中，且邏輯晶粒308完全上覆記憶體晶粒312。在替代實施例中，邏輯晶粒308僅部分上覆記憶體晶粒312。 在例示性實施例中，如圖3中所展示，記憶體晶粒312之一主動表面316經定向朝向邏輯晶粒308之一主動表面318，並背向基板302 (即，邏輯晶粒308及記憶體晶粒312經定向成一面對面配置)。記憶體晶粒312包含經形成於其中之複數個貫穿矽通路(TSV) 320，以實現直接電連接至封裝基板302。TSV 320係經由複數個焊料微凸塊322直接耦合至基板302。在替代實施例中，TSV 320使用使IC裝置300能夠用作本文中所描述之任何連接方法(例如(且不限於)經由擴散接合、共晶接合、熱壓縮接合及導電聚合物之使用)直接耦合至基板302。在一些實施例中，TSV 320使用任何已知製造技術(諸如雷射鑽孔、機械鑽孔及/或蝕刻處理)來形成在記憶體晶粒312中。TSV 320及焊料微凸塊322使記憶體晶粒312之至少一個電連接能夠連接至基板302上之其他電路(未展示)而不通過邏輯晶粒308。此促進增加IC裝置300的效率，以及減少與IC裝置300之製造相關聯的製造成本。 在替代實施例中，可定向記憶體晶粒312，使得記憶體晶粒312之主動表面316定向成背向邏輯晶粒308之主動表面318且面向基板302。在此等實施例中，記憶體晶粒312之TSV 320促進直接電連接至邏輯晶粒308。再者，在此等實施例中，TSV 320係經由焊料微凸塊(諸如焊料微凸塊314 )直接耦合至邏輯晶粒308。因而，TSV 320及焊料微凸塊314使記憶體晶粒312之至少一個電連接部能夠直接連接至邏輯晶粒308而不通過基板302。在替代實施例中，邏輯晶粒308及TSV 320使用使IC裝置300能夠用作本文中所描述之任何連接方法(例如(且不限於)經由擴散接合、共晶接合、熱壓縮接合及導電聚合物之使用)彼此直接耦合。 在例示性實施例中，如圖3及圖4中所展示及在本文中所描述，邏輯晶粒308係經由複數個焊料微凸塊310直接耦合至連接組件304。連接組件304包含在重佈佈線層334上形成之一或多個焊線墊326。焊墊326係經由在重佈佈線層334上形成之一電路(未展示)及/或在連接組件304之一或多個堆積層(未展示)內形成之內部電路328電連接至至少一個焊料微凸塊310。因此，一電信號(未展示)係自邏輯晶粒308傳輸至一或多個焊線墊326。此外，基板302包含一或多個焊線墊330，其係經由在基板302之一主動表面331上/中形成之一電路及/或內部電路(未展示)連接至其他電路(未展示)。應注意，相對於至少一些已知中介層，連接組件304不含有貫穿矽通路，藉此促進減少製造連接組件304之一複雜度及製造成本。 在例示性實施例中，連接組件焊墊326及基板焊墊330係經由導線332電耦合在一起。此促進將邏輯晶粒308直接連接至基板302。自(例如)(且不限於)金、鋁、銅及其合金製造導線332。經由導線332將邏輯晶粒308耦合至基板302促進用於將IC裝置300耦合至其他裝置及/或電路(未展示)之一具成本效率及靈活性技術。 圖5係形成為一單一3D封裝結構之一IC裝置500之一示意平面圖。參考圖3及圖5，在例示性實施例中，IC裝置500經製造實質上類似於如在本文中所描述之IC裝置300。IC裝置500包含封裝基板302、至少一個邏輯晶粒308及至少一個記憶體晶粒312。然而，相對於參考IC裝置300在本文中所描述之單體連接組件304，IC裝置500包含一或多個連接組件(例如連接組件502、504、506及508 )，如圖5中所展示。連接組件502、504、506及508經由複數個焊料微凸塊306耦合至封裝基板302。邏輯晶粒308經定位於相對封裝基板302之連接組件502、504、506及508上並耦合至相對封裝基板302之連接組件502、504、506及508。邏輯晶粒308經由複數個焊料微凸塊310直接耦合至連接組件502、504、506及508。在一些實施例中，邏輯晶粒308係一單一晶片，且在其他實施例中，邏輯晶粒308係一多晶片(例如，一並排晶片配置)封裝。如在本文中所描述，邏輯晶粒308包含例如(且不限於)一處理器、處理裝置或控制器(諸如一通用中央處理單元(CPU)、一圖形處理單元(GPU)、一加速處理單元(APU)、一微控制器、一精簡指令集電腦(RISC)處理器、一特定應用積體電路(ASIC)、一可程式化邏輯電路(PLC)、一可程式化邏輯單元(PLU)、一場可程式化閘陣列(FPGA)、閘陣列、一數位信號處理(DSP)裝置及/或使IC裝置500能夠用作本文中所描述之任何其他邏輯電路或處理裝置)。 在例示性實施例中，連接組件502、504、506及508係定位於接近邏輯晶粒308之一周邊之離散組件，於其間界定用於接收記憶體晶粒312之一腔524。如圖5中所展示，連接組件502、504、506及508係經定位以界定一大致矩形形狀腔524之大致矩形形狀組件。然而，應注意在連接組件502、504、506及508經展示具有大致矩形時，可預期連接組件502、504、506及508可具有使連接組件502、504、506及508用作本文中所描述之任何形狀。 在例示性實施例中，連接組件502、504、506及508之各者僅部分藉由邏輯裝置308上覆。在此一實施例中，一或多個連接組件502、504、506及508可為一主動連接組件。例如，在一項實施例中，一或多個連接組件502、504、506及508包含嵌入於其中及/或在其上形成之主動電氣組件(例如(且不限於)電晶體、信號放大器、信號濾波器及使一或多個連接組件502、504、506及508用作本文中所描述之任何其他主動電氣組件)。此等主動電氣組件經放置於不藉由邏輯裝置308上覆之連接組件502、504、506及508之部分上。 在替代實施例中，一或多個連接組件502、504、506及508係一被動中介層。在一些此替代實施例中，例如(且不限於)一或多個連接組件502、504、506及508不包含額外電氣組件。在其他此等實施例中，一或多個連接組件502、504、506及508包含嵌入於其中及/或在其上形成之一或多個積體被動裝置(IPD) (例如(且不限於)電阻器、電容器、電感器及使連接組件502、504、506及508用作本文中所描述之任何其他被動電氣組件)。 此外，在例示性實施例中，連接組件502、504、506及508自矽製造且包含一或多個重佈佈線層334 (即，及主動表面)。替代地，自使連接組件502、504、506及508能夠用作本文中所描述之任何材料(例如(且不限於)玻璃、陶瓷、有機材料、鍺、砷化鎵、磷化銦及碳化矽)製造連接組件502、504、506及508。重佈佈線層334促進邏輯晶粒308之電連接點或接腳(未展示) (例如對應於焊料微凸塊310)可用於連接組件502、504、506及508上之其他位置之位置。因此，重佈佈線層334促進繞線邏輯晶粒308之電連接點或接腳至連接組件502、504、506及508上之有利位置以促進使自邏輯晶粒308上之不同位置能夠接合至連接組件502、504、506及508上之類似及/或鄰近位置，藉此簡化IC裝置500之總成。 參考圖3及圖5，邏輯晶粒308及記憶體晶粒312經由焊料微凸塊314直接耦合至彼此且垂直地整合(即，記憶體晶粒312經垂直地定位於邏輯晶粒308之下方)。更特定言之，記憶體晶粒312經垂直地定位於邏輯晶粒308與封裝基板302之間使得邏輯晶粒308上覆記憶體晶粒312。在此一實施例中，記憶體晶粒312由連接組件502、504、506及508界定定位於腔524中，且邏輯晶粒308全部上覆記憶體晶粒312。替代地，邏輯晶粒308僅部分上覆記憶體晶粒312。 在例示性實施例中，邏輯晶粒308經由複數個焊料微凸塊310直接耦合至連接組件502、504、506及508。連接組件502、504、506及508包含在重佈佈線層534上形成之一或多個焊線墊526。焊墊526經由在重佈佈線層534上形成之一電路(未展示)及/或在連接組件502、504、506及508之一或多個堆積層(未展示)內形成之內部電路328電連接至至少一個焊料微凸塊310。因此，一電信號(未展示)自邏輯晶粒308傳輸至一或多個焊線墊526。應注意，相對於至少一些已知中介層，連接組件502、504、506及508不含有貫穿矽通路，藉此促進減少製造連接組件502、504、506及508之一複雜度及製造成本。 在例示性實施例中，連接組件焊墊526及基板焊墊330經一起電耦合至導線332。此促進將邏輯晶粒308直接連接至基板302。如本文中所描述，導線332自例如(且不限於)金、鋁、銅及其合金製造。經由導線332將邏輯晶粒308耦合至基板302促進用於將IC裝置500耦合至其他電子裝置及/或電路(未展示)之一具成本效率及靈活性技術。 圖6係形成為一單一3D封裝結構之一IC裝置600之一示意平面圖。參考圖3及圖6，在例示性實施例中，IC裝置600經製造實質上類似於如在本文中所描述之IC裝置300及500。例如，IC裝置600包含封裝基板302、至少一個邏輯晶粒308及至少一個記憶體晶粒312。然而，相對於各別地參考IC裝置300及500在本文中所描述之單體連接組件304或大致矩形形狀連接組件502、504、506及508，IC裝置600包含一或多個「L形狀」連接組件(例如連接組件602及604)，如圖6中所展示。連接組件602及604經由複數個焊料微凸塊306耦合至封裝基板302。邏輯晶粒308經定位於相對封裝基板302之連接組件602及604上並經耦合至相對封裝基板302之連接組件602及604。邏輯晶粒308經由複數個焊料微凸塊310直接耦合至連接組件602及604。 在例示性實施例中，連接組件602及604係定位於邏輯晶粒308之約一周邊之離散組件，其界定用於接收記憶體晶粒312之其間之一腔624。如圖6中所展示，連接組件602及604經定位以界定一大致矩形形狀腔624。邏輯晶粒308及記憶體晶粒312經彼此直接耦合使得記憶體晶粒312經垂直地定位於邏輯晶粒308與封裝基板302之間。在此一實施例中，記憶體晶粒312經定位於由連接組件602及604界定之腔624中，且邏輯晶粒308全部上覆記憶體晶粒312。替代地，邏輯晶粒308僅部分上覆記憶體晶粒312。 在例示性實施例中，如圖3及圖6中所展示，邏輯晶粒308經由複數個焊料微凸塊310直接耦合至連接組件602及604。連接組件602及604包含在重佈佈線層634上形成之一或多個焊線墊626。焊墊626經由在重佈佈線層634上形成之一電路(未展示)及/或在連接組件602及604之一或多個堆積層(未展示)內形成之內部電路328電連接至至少一個焊料微凸塊310。因此，一電信號(未展示)自邏輯晶粒308傳輸至一或多個焊線墊626。應注意，相對於至少一些已知中介層，連接組件602及604不含有貫穿矽通路，藉此促進減少製造連接組件602及604之一複雜度及製造成本。 此外，在例示性實施例中，連接組件焊墊626及基板焊墊330經由導線332電耦合在一起。此促進將邏輯晶粒308直接連接至基板302。如本文中所描述，導線332自例如(且不限於)金、鋁、銅及其合金製造。經由導線332將邏輯晶粒308耦合至基板302促進用於將IC裝置600耦合至其他電子裝置及/或電路(未展示)之一具成本效率及靈活性技術。 此外，在例示性實施例中，連接組件602及604以如連接組件304及/或連接組件502、504、506及508實質上相同方式形成。例如，連接組件602及604自矽製造且包含一或多個重佈佈線層634。替代地，連接組件602及604自使連接組件602及604能夠用作本文中所描述之任何材料(例如(且不限於)玻璃、陶瓷、有機材料、鍺、砷化鎵、磷化銦及碳化矽)製造。另外，在一些實施例中，一或多個連接組件602及604係包含嵌入於其中及/或在其上形成之一或多個主動電氣組件之一主動連接組件(例如(且不限於)電晶體、信號放大器、信號濾波器及使一或多個連接組件602及604能夠用作本文中所描述之任何其他主動電氣組件)。在其他實施例中，一或多個連接組件602及604係一被動中介層(即，連接組件602及604不包含額外電氣組件)。在一些此等實施例中，一或多個連接組件602及604包含嵌入於其中及/或在其上形成之一或多個積體被動裝置(IPD) (例如(且不限於)電阻器、電容器、電感器及使連接組件602及604能夠用作本文中所描述之任何其他被動電氣組件)。 圖7係形成具有一單一3D封裝結構(諸如圖3中所展示之例示性IC裝置300 )之一IC裝置之一例示性方法700之一流程圖。參考圖3至圖6，例示性方法700包含形成具有其中界定之一腔324之至少一個連接組件(例如連接組件304 ) ( 702 )。另外地或替代地，方法700包含分離地形成複數個連接組件(例如，連接組件502、504、506、508及/或602及604 ) ( 704 )及將複數個連接組件502、504、506、508及/或602及604定位於一基板(諸如基板302 )上以在其間界定一腔(例如，各別地腔524或624 ) ( 706 )。各連接組件304、502、504、506、508及/或602及604包含各別地在重佈佈線層334、534或634上形成一或多個焊線墊(例如，各別地焊線墊326、526或626 )。另外，基板302包含在基板302之主動表面331上形成之一或多個焊線墊330。 在例示性實施例中，方法700亦包含將至少一個連接組件耦合至基板302 ( 708 )。另外地或替代地，耦合至少一個連接組件( 708 )之操作進一步包含經由黏著接合、焊料微凸塊306及使IC裝置300能夠用作本文中所描述之任何其他電子或非電子接合程序將至少一個連接組件接合至基板302 ( 710 )。 在一些實施例中，方法700包含經由複數個焊料微凸塊322將至少一個記憶體晶粒312電耦合至基板302 ( 712 )，使得記憶體晶粒312經定位於由至少一個連接組件界定之腔內。在一項此實施例中，將至少一個記憶體晶粒312電耦合至基板302 ( 712 )包含將記憶體晶粒312之主動表面316電耦合至基板302 ( 714 )。在一替代實施例中，將至少一個記憶體晶粒312電耦合至基板302 ( 712 )之操作包含經由複數個焊料微凸塊322將複數個TSV 320電耦合至基板302 (即，將記憶體晶粒312之一非主動表面耦合至基板302 ) ( 716 )。 在例示性實施例中，方法700進一步包含將邏輯晶粒308電耦合至記憶體晶粒312及連接組件之至少一部分( 718 )。例如，邏輯晶粒308經由複數個焊料微凸塊314耦合至記憶體晶粒312。另外，邏輯晶粒308經由複數個焊料微凸塊310耦合至至少一個連接組件。在一項實施例中，邏輯晶粒308全部上覆記憶體晶粒312。在一替代實施例中，邏輯晶粒308僅部分上覆記憶體晶粒312。 此外，方法700包含經由導線332將連接組件焊墊(例如墊326、526或626 )電耦合至基板焊墊330 ( 720 )。此促進將邏輯晶粒308電耦合至基板302。 連接組件及方法之上文所描述之實施例實現具有熱有利配置、改良熱耗散及減少如相較於至少一些已知IC裝置之複雜度及製造之成本之IC裝置之製造。特定言之，所揭示之連接組件實施例包含經組態以接收至少一個減小功率耗散組件(例如，一記憶體晶粒(或記憶體晶粒堆疊) )之一腔。腔促進將記憶體晶粒電耦合至一邏輯晶粒及一IC封裝基板，其將記憶體晶粒垂直地定位於其間。此使記憶體晶粒(其歸因於電子互連之一減小數目而通常定位於邏輯晶粒之頂部上)能夠具有直接耦合至邏輯晶粒之其邏輯晶粒連接及保持至耦合至基板上之其他電路之連接。另外，此一配置減少及/或消除對在邏輯晶粒中要形成之TSV的需要，藉此減少邏輯晶粒之尺寸及複雜度。連接組件使邏輯晶粒經由焊線(例如，球接合、斜楔接合及柔性接合)能夠電連接至基板上之電路，藉此減少及/或消除對在記憶體晶粒中形成之TSV以自邏輯晶粒通過電信號之需要。亦特定言之，連接組件促進減少本文中所描述之製造IC裝置之複雜度、時間及成本。 本文中所描述之方法、系統及設備之一例示性技術效應包含以下之至少一者：(a)將邏輯晶粒放置於封裝結構(對夾置於一記憶體晶粒與基板之間)之外部上，其導致更佳熱管理且因此導致經增強效能；(b)減小邏輯晶粒之複雜度(即，減少或消除TSV)且藉此減小製造成本；及(c)進一步經由經接合連接組件之一導線之使用而減小IC裝置之總成本。 在上文中詳細描述界定用於3D堆疊晶粒之腔之連接組件之例示性實施例及方法。具有腔之連接組件及使用此等連接組件之方法不限於本文中所描述之特定實施例，而是可獨立地及分離地自本文中所描述之其他組件及/或操作利用系統之組件及/或方法之操作。例如，可實施例示性實施例並結合當前經組態以使用堆疊積體電路裝置之許多其他應用而利用。 儘管可在一些圖式中展示且不在其他圖式中展示本發明之各種實施例之特定特徵，此僅係為了方便。根據本發明之原理，可結合任何其他圖式之任何特徵參考及/或主張一圖式之任何特徵。 此書面之描述使用實例來揭示本實施例(包含最佳模式)，且亦使熟習此項技術者能夠實踐本實施例，包含製造及使用任何裝置或系統並執行任何併入方法。本發明之專利範疇係藉由申請專利範圍所界定，且可包含對熟習此項技術者發生之其他實例。若此等其他實例具有與申請專利範圍之文字語言並無不同之結構元件或若該等實例包含與申請專利範圍之文字語言並無實質不同之等效結構元件，則此等其他實例旨在落在申請專利範圍之範疇內。
100‧‧‧積體電路(IC)裝置102‧‧‧邏輯晶粒104‧‧‧記憶體晶粒106‧‧‧TSV(貫穿矽通路)108‧‧‧封裝基板110‧‧‧焊料微凸塊112‧‧‧焊料微凸塊200‧‧‧積體電路(IC)裝置202‧‧‧邏輯晶粒204‧‧‧記憶體晶粒206‧‧‧中介層208‧‧‧焊料微凸塊210‧‧‧焊料微凸塊212‧‧‧TSV(貫穿矽通路)214‧‧‧封裝基板216‧‧‧焊料微凸塊300‧‧‧積體電路(IC)裝置302‧‧‧封裝基板304‧‧‧中介層組件或連接組件306‧‧‧焊料微凸塊308‧‧‧邏輯晶粒310‧‧‧焊料微凸塊312‧‧‧記憶體晶粒314‧‧‧焊料微凸塊316‧‧‧主動表面318‧‧‧主動表面320‧‧‧貫穿矽通路(TSV)322‧‧‧焊料微凸塊324‧‧‧腔326‧‧‧焊線墊328‧‧‧內部電路330‧‧‧焊線墊/基板焊墊332‧‧‧導線334‧‧‧重佈佈線層500‧‧‧積體電路(IC)裝置502‧‧‧連接組件504‧‧‧連接組件506‧‧‧連接組件508‧‧‧連接組件524‧‧‧腔526‧‧‧焊線墊/連接組件焊墊534‧‧‧重佈佈線層600‧‧‧積體電路(IC)裝置602‧‧‧連接組件604‧‧‧連接組件624‧‧‧腔626‧‧‧焊線墊/連接組件焊墊634‧‧‧重佈佈線層700‧‧‧方法702‧‧‧形成具有其中界定之一腔324之至少一個連接組件704‧‧‧分離地形成複數個連接組件706‧‧‧將複數個連接組件502、504、506、508及/或602及604定位於一基板上以在其間界定一腔708‧‧‧將至少一個連接組件耦合至基板302710‧‧‧經由黏著接合、焊料微凸塊306及使IC裝置300能夠用作本文中所描述之任何其他電子或非電子接合程序將至少一個連接組件接合至基板302712‧‧‧將至少一個記憶體晶粒312電耦合至基板302714‧‧‧將記憶體晶粒312之主動表面316電耦合至基板302716‧‧‧經由複數個焊料微凸塊322將複數個TSV 320電耦合至基板302 (即，將記憶體晶粒312之一非主動表面耦合至基板302 )718‧‧‧將邏輯晶粒308電耦合至記憶體晶粒312及電氣組件之至少一部分720‧‧‧經由導線332將連接組件焊墊(例如墊326、526或626 )電耦合至基板焊墊330
當參考附圖閱讀以下詳細描述時，將更能理解本發明之此等及其他特徵、態樣及優點，所有圖式之相同元件符號代表相同部件，其中： 圖1係形成為一單一三維(3D)封裝結構之一先前技術積體電路(IC)裝置之一示意前視圖； 圖2係形成為一單一2.5維(2.5D)封裝結構之一先前技術IC裝置之一示意前視圖； 圖3係形成為一單一3D封裝結構之一例示性IC裝置之一剖視圖； 圖4係在圖3中所展示之IC裝置之一示意平面圖； 圖5係形成為一單一3D封裝結構之一替代IC裝置之一示意平面圖； 圖6係形成為一單一3D封裝結構之另一替代IC裝置之一示意平面圖；及 圖7係形成具有一單一3D封裝結構之一IC裝置(諸如圖3中所展示之例示性IC裝置)之一例示性方法之一流程圖。 除非另有指示，否則在本文中所提供之圖式意指繪示本揭示之實施例之特徵。據信此等特徵可用於包括本揭示之一或多項實施例之一廣泛範圍之系統中。因而，圖式不意指包含本文中所揭示之實施例之實踐需要之由此等熟習此項技術者所知之全部習知特徵。
300‧‧‧積體電路(IC)裝置
302‧‧‧封裝基板
304‧‧‧中介層組件或連接組件
306‧‧‧焊料微凸塊
308‧‧‧邏輯晶粒
310‧‧‧焊料微凸塊
312‧‧‧記憶體晶粒
314‧‧‧焊料微凸塊
316‧‧‧主動表面
318‧‧‧主動表面
320‧‧‧貫穿矽通路(TSV)
322‧‧‧焊料微凸塊
324‧‧‧腔
326‧‧‧焊線墊
328‧‧‧內部電路
330‧‧‧焊線墊/基板焊墊
332‧‧‧導線
334‧‧‧重佈佈線層
504‧‧‧連接組件
508‧‧‧連接組件
524‧‧‧腔
526‧‧‧焊線墊/連接組件焊墊
534‧‧‧重佈佈線層
602‧‧‧連接組件
604‧‧‧連接組件
624‧‧‧腔
626‧‧‧焊線墊/連接組件焊墊
634‧‧‧重佈佈線層

Claims (20)

  1. 一種積體電路(IC)裝置，其包括：一基板；一連接組件，其包括穿過其界定之一腔，該連接組件經耦合至該基板；至少一個記憶體晶粒，其等經定位於該腔中，該至少一個記憶體晶粒經電耦合至該基板；及一邏輯晶粒，其延伸在該至少一個記憶體晶粒及該連接組件之至少一部分上方(over)，該至少一個邏輯晶粒經電耦合至該連接組件及該至少一個記憶體晶粒，其中該連接組件不含有貫穿矽通路(through silicon vias)，且其中該連接組件經由至少一個焊線(wire bond)電耦合至該基板。
  2. 如請求項1之IC裝置，其中該連接組件包括含有至少一個焊線墊之一重佈佈線層，該基板包含至少一個基板焊墊，及該至少一個焊線墊係經由該至少一個焊線電耦合至該基板焊墊。
  3. 如請求項1之IC裝置，其中該至少一個記憶體晶粒包括一主動表面，該主動表面面向該基板且背向該邏輯晶粒。
  4. 如請求項1之IC裝置，其中該至少一個記憶體晶粒包括一主動表面，該主動表面面向該邏輯晶粒且背向該基板。
  5. 如請求項1之IC裝置，其中該連接組件係一被動連接組件。
  6. 如請求項5之IC裝置，其中該被動連接組件包括經嵌入於其中之至少一個被動組件。
  7. 如請求項6之IC裝置，其中該被動組件包括以下之一或多個：電阻器、電容器及電感器。
  8. 如請求項1之IC裝置，其中該連接組件係一主動連接組件。
  9. 如請求項8之IC裝置，其中該主動連接組件包括經嵌入於其中之至少一個主動電氣組件。
  10. 如請求項9之IC裝置，其中該主動電氣組件包括以下之一或多個：電晶體、信號放大器及信號濾波器。
  11. 一種積體電路(IC)裝置，其包括：一基板，其包括一第一主動表面，該第一主動表面包括複數個基板焊墊；複數個連接組件，其等經耦合至該第一主動表面，該複數個連接組件經配置以在該複數個連接組件之間界定一腔，該複數個連接組件之各連接組件包括相對該第一主動表面之一第二主動表面，各該第二主動表面包 括至少一個連接組件焊墊；至少一個記憶體晶粒，其等經定位於該腔內且經電耦合至該第一主動表面；及一邏輯晶粒，其經耦合至各該第二主動表面及該至少一個記憶體晶粒，其中該複數個連接組件不含有貫穿矽通路，且其中各該至少一個連接組件焊墊經由至少一個焊線電耦合至該複數個基板焊墊之一基板焊墊。
  12. 如請求項11之IC裝置，其中該複數個連接組件之至少一個連接組件係一被動連接組件。
  13. 如請求項12之IC裝置，其中該至少一個被動連接組件包括經嵌入於其中之至少一個被動組件。
  14. 如請求項13之IC裝置，其中該至少一個被動組件包括以下之一或多個：電阻器、電容器及電感器。
  15. 如請求項11之IC裝置，其中該複數個連接組件之至少一個連接組件係一主動連接組件。
  16. 如請求項15之IC裝置，其中該主動連接組件包括經嵌入於其中之至少一個主動電氣組件。
  17. 如請求項16之IC裝置，其中該主動電氣組件包括以下之一或多個： 電晶體、信號放大器及信號濾波器。
  18. 一種形成具有一3D封裝結構之一IC裝置之方法，該方法包括：形成不含有貫穿矽通路之一連接組件，該連接組件包含穿過其界定之一腔，且一重佈佈線層包含一連接組件焊墊；將該連接組件耦合至一基板，該基板包含一基板焊墊；將至少一個記憶體晶粒耦合至該基板，使得記憶體晶粒係定位於該腔內；將一邏輯晶粒延伸在該記憶體晶粒及該連接組件之至少一部分上方；將該邏輯晶粒電耦合至該記憶體晶粒及該連接組件之至少一部分；及將該連接組件焊墊經由至少一個焊線電耦合至該基板焊墊。
  19. 如請求項18之方法，其中形成該連接組件包括分離地形成複數個連接組件，該複數個連接組件之各連接組件包含一連接組件焊墊，且其中將該連接組件耦合至一基板包括：將該複數個連接組件定位於該基板上，以在該複數個連接組件之間界定一腔；及將該複數個連接組件耦合至該基板。
  20. 如請求項18之方法，其中將該至少一個記憶體晶粒耦合至該基板包括：將該記憶體晶粒之一第一表面電耦合至該基板；及 經由經形成於該記憶體晶粒中之複數個貫穿矽通路，將該記憶體晶粒之一第二表面電耦合至該基板，該第二表面相對該第一表面。
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