CN107785334A - 电子封装结构及其制法 - Google Patents

电子封装结构及其制法 Download PDF

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CN107785334A
CN107785334A CN201710107044.8A CN201710107044A CN107785334A CN 107785334 A CN107785334 A CN 107785334A CN 201710107044 A CN201710107044 A CN 201710107044A CN 107785334 A CN107785334 A CN 107785334A
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package structure
structure according
electron package
bearing part
metal frame
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CN107785334B (zh
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邱志贤
黄承文
钟兴隆
蔡文荣
洪家惠
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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Abstract

一种电子封装结构及其制法，该电子封装结构包括：承载件、设于该承载件上的电子元件与多个导电元件、结合至该多个导电元件上的金属架、以及形成于该承载件与该金属架上且包覆该电子元件与该多个导电元件的包覆层，且通过该金属架外露于该包覆层以作为电性接点，而使用共用模压模具形成该包覆层即可，故无需配合该电子封装结构的尺寸使用特定尺寸的模压模具，因而能降低生产成本。

Description

电子封装结构及其制法
技术领域
本发明关于一种半导体结构，特别是关于一种电子封装结构及其制法。
背景技术
随着近年来可携式电子产品的蓬勃发展，各类相关产品的开发也朝向高密度、高性能以及轻、薄、短、小的趋势，各态样的堆叠封装(package on package，简称PoP)也因而配合推陈出新，以期能符合轻薄短小与高密度的要求。
图1为现有半导体封装结构1的剖视示意图。如第1图所示，该半导体封装结构1的制法于一基板10的上、下两侧设置半导体元件11与被动元件11’，再以封装胶体14包覆该多个半导体元件11与被动元件11’，并使该基板10的接点(I/O)100外露于该封装胶体(molding compound)14，之后形成多个焊球13于该多个接点100上，以于后续制程中，该半导体封装结构1透过该焊球13接置如电路板或另一线路板的电子装置(图略)。
然而，现有半导体封装结构1中，由于该封装胶体14的模压(molding)范围缩减以外露该多个接点100，因而需视该半导体封装结构1的尺寸而使用特定尺寸的模压模具，故单一模压模具无法适用于各种半导体封装结构1的尺寸，因而增加生产成本。
又，该多个半导体元件11与被动元件11’包覆于该封装胶体14中，致使该多个半导体元件11与被动元件11’的散热效果不佳。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子封装结构及其制法，能降低生产成本。
本发明的电子封装结构，包括：承载件；电子元件，其接置于该承载件上；多个导电元件，其设置于该承载件上；金属架，其包含有多个电性接触垫，以供结合至该多个导电元件上；以及包覆层，其形成于该承载件及/或该金属架上以包覆该电子元件及/或该多个导电元件。
本发明还提供一种电子封装结构的制法，包括：提供一电子组件，其包含承载件、接置于该承载件上的电子元件与多个导电元件；将该电子组件透过该导电元件结合至一金属架上，其中，该金属架包含有多个电性接触垫，以供该金属架通过该多个电性接触垫结合该导电元件；以及形成包覆层于该承载件及/或该金属架上，以包覆该电子元件及/或该多个导电元件。
前述的电子封装结构及其制法中，该承载件为封装基板、无核心层的线路结构或导线架。
前述的电子封装结构及其制法中，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上分别设有该电子元件。
前述的电子封装结构及其制法中，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上方分别设有该金属架。
前述的电子封装结构及其制法中，该电子元件位于该承载件与该金属架之间。
前述的电子封装结构及其制法中，该导电元件为锡膏、导电胶、焊球、铜核心球、被动元件或金属件。
前述的电子封装结构及其制法中，至少一该导电元件通过绝缘体结合该承载件。
前述的电子封装结构及其制法中，该金属架为导线架。
前述的电子封装结构及其制法中，该电性接触垫外露于该包覆层。
另外，前述的电子封装结构及其制法中，该金属架还包含对应该电子元件位置的板体。例如，该电性接触垫与该板体相分离。该板体未接触该电子元件；该板体接触该电子元件；该板体与该电性接触垫的高度相同或不同；该板体通过中介层结合至该电子元件上。
由上可知，本发明的电子封装结构及其制法中，主要通过将电子组件的导电元件结合该金属架，且使该金属架外露于该包覆层以作为电性接点，故相比于现有技术，本发明使用共用模压模具形成该包覆层即可，而无需配合该电子封装结构的尺寸，因而能降低生产成本。
此外，通过该金属架包含板体的设计，以提升该电子封装结构的散热效果。
附图说明
图1为现有半导体封装结构的剖面示意图；
图2A至图2C为本发明的电子封装结构的制法第一实施例的剖面示意图；其中，图2A’及图2C’为图2A及图2C的另一实施例，图2C”为图2C的又一实施例；
图3为本发明的电子封装结构第二实施例的剖面示意图；
图3A为图3的下视示意图；
图3B为图3A的另一实施例；
图4A至图4C为图3的其它实施例的剖面示意图。
图5A及图5B为图2C导电元件的其它实施例；
图6A及图6B为图2C的其它实施例；
图7A为图5A的另一实施例的剖面示意图；以及
图7B为图7A的金属架的上视示意图。
符号说明：
1 半导体封装结构
10 基板
100 接点
11 半导体元件
11’ 被动元件
13 焊球
14 封装胶体
2,2’,3,5,5’,6,6’,7 电子封装结构
2a,2a’ 电子组件
20 承载件
20a 第一侧
20b 第二侧
200 线路层
21,41,41’ 第一电子元件
210,220 导电凸块
22,22’ 第二电子元件
23,23’,23”,53,53’ 导电元件
24 第一包覆层
25,25”,35,45,45’,45”,55 金属架
25’ 支撑件
250,550 电性接触垫
26 第二包覆层
26a 第一表面
26b 第二表面
26c 侧面
351,451,451’,451”,551 板体
48 中介层
53” 绝缘体
a,b,c,d,e 高度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装结构2的制法第一实施例的剖面示意图。
如图2A所示，提供一电子组件2a，其包含一承载件20、设于该承载件20上的第一电子元件21、第二电子元件22,22’与导电元件23。
所述的承载件20具有相对的第一侧20a与第二侧20b。于本实施例中，该承载件20为如具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其具有多个线路层200，如扇出(fan out)型重布线路层(redistribution layer，简称RDL)。应可理解地，该承载件20也可为其它可供承载如晶片等电子元件的承载单元，例如导线架(leadframe)，并不限于上述。
所述的第一电子元件21设于该承载件20的第一侧20a上。于本实施例中，该第一电子元件21为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体晶片，且该被动元件例如为电阻、电容及电感。例如，该第一电子元件21通过多个如焊锡材料的导电凸块210以覆晶方式设于该线路层200上并电性连接该线路层200；或者，该第一电子元件21可通过多个焊线(图略)以打线方式电性连接该线路层200。然而，有关该第一电子元件21电性连接该承载件20的方式不限于上述。
所述的第二电子元件22,22’设于该承载件20的第二侧20b上。于本实施例中，该第二电子元件22,22’为主动元件(如标号22)、被动元件(如标号22’)或其二者组合等，其中，该主动元件例如为半导体晶片，且该被动元件例如为电阻、电容及电感。例如，该第二电子元件22通过多个如焊锡材料的导电凸块220以覆晶方式设于该线路层200上；或者，该第二电子元件22可通过多个焊线(图略)以打线方式电性连接该线路层200。抑或，该第二电子元件22’可直接接触该线路层200。然而，有关该第二电子元件22,22’电性连接该承载件20的方式不限于上述。
所述的导电元件23设于该承载件20的第一侧20a的线路层200上。于本实施例中，该导电元件23为焊球(solder ball)，但不限于上述。
另外，该电子组件2a还包含一形成于该承载件20第二侧20b上以包覆该第二电子元件22,22’的第一包覆层24。
于本实施例中，形成该第一包覆层24的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材(molding compound)。
于其它实施例中，如图2A’所示，该电子组件2a’可不形成该第一包覆层24。
如图2B所示，接续图2A的制程，将该电子组件2a以其导电元件23结合至一金属架25上。
于本实施例中，该金属架25例如为导线架(leadframe)，其包含多个相分离的电性接触垫250，以结合各该导电元件23。
此外，可选择性地，先将该金属架25设于一如胶带(tape)的支撑件25’上，再将该电子组件2a结合至该金属架25上。
应可理解地，也可将该电子组件2a结合至多个该金属架25上。
如图2C所示，形成一第二包覆层26于该承载件20第一侧20a与该金属架25(或该支撑件25’)之间，也就是透过单面模压制程，使该第二包覆层26包覆该第一电子元件21与该多个导电元件23。之后，移除该支撑件25’，以形成电子封装结构2。
于本实施例中，形成该第二包覆层26的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材(molding compound)，且该第二包覆层26具有相对的第一表面26a与第二表面26b，使该第二包覆层26以其第二表面26b结合该承载件20的第一侧20a，且该金属架25嵌设于该第二包覆层26的第一表面26a，并使该多个电性接触垫250外露于该第二包覆层26的第一表面26a(例如，该多个电性接触垫250的表面齐平该第二包覆层26的第一表面26a)，以于该多个电性接触垫250的外露表面上形成有如焊球的焊锡材料(图略)，俾供接置如电路板或另一线路板的电子装置。
此外，若接续图2A’的制程，如图2C’所示，于形成该第二包覆层26时，透过双面模压制程，该第二包覆层26同时包覆该第一电子元件21及该多个第二电子元件22,22’，以形成电子封装结构2’。
另外，也可选择仅形成第一包覆层24或第二包覆层26的其中一者，如图6A所示，仅形成第一包覆层24而未形成该第二包覆层26，抑或如图6B所示，仅形成第二包覆层26而未形成该第一包覆层24。
应可理解地，该第二包覆层26的材质与该第一包覆层24的材质可相同或不相同。
又，如图2C”所示，该导电元件23’,23”也可为铜核心球(Cu core ball)、被动元件或金属件(如柱状、块状或针状)等。具体地，左侧的导电元件23’为铜核心球，而右侧的导电元件23”为被动元件，例如电阻、电容及电感，图中为以去耦合电容(decouplingcapacitor)为例。或者，如图5A所示，导电元件53也可为锡膏或导电胶等，且依需求调整电性接触垫550高度(例如增加高度)。抑或，如图5B所示，导电元件53’与电性接触垫550为一体成形的金属件，且通过如环氧树脂(epoxy)的绝缘体53”结合该承载件20的第一侧20a，以令至少一该导电元件53’与该电性接触垫550仅作为支撑用而未电性连接该承载件20。应可理解地，该导电元件23,23’,23”,53,53’可于同一封装件中混合上述各种态样使用，如图2C”所示。
另外，该承载件20的第二侧20b的线路层200上也可形成导电元件23，如图2C”所示，且结合至另一金属架25”。
本发明的制法中，于结合该金属架25,25”后，再形成该第二包覆层26，使该金属架25,25”外露于该第二包覆层26以作为电性接点，故无需配合该电子封装结构2,2’的尺寸而使用特定尺寸的模压模具，也就是使用共用模压模具形成该第二包覆层26即可，因而能降低生产成本。
图3为本发明的电子封装结构3的第二实施例的剖面示意图。本实施例与第一实施例的差异在于金属架的构造，故以下仅说明相异处，而不再赘述相同处。
如图3所示，该金属架35包含多个用以结合该导电元件23的电性接触垫250、及对应该第一电子元件21位置的一板体351。
所述的板体351与该多个电性接触垫250相分离，且如图3A所示，该多个电性接触垫250围绕该板体351的边缘外。应可理解地，于该板体351的外围可环绕多圈的电性接触垫250，如图3B所示的两环圈。
于本实施例中，该板体351未接触该第一电子元件21，也就是该板体351与该第一电子元件21之间设有该第二包覆层26。
另该板体351的高度(厚度)可与该电性接触垫250的高度(厚度)相同。
此外，如图4A所示的金属架45，该板体451也可接触该第一电子元件41。或者，如图4B所示的金属架45’，该板体451也可通过一中介层48结合至该第一电子元件21上，其中，该中介层48例如为薄膜(film)、环氧树脂(epoxy)或热介面材料(thermal interfacematerial，简称TIM)。
又，如图4C所示的金属架45”，其包含多个相分离的板体451’,451”，且该多个电性接触垫250仍围绕于该多个板体451’,451”所占用的总区域的外围。例如，部分该板体451’可对应该第一电子元件41’的位置，而部分该板体451”可作为电性接触垫，即通过该导电元件23结合至该承载件20的第一侧20a上，以增加接点(如作为讯号接点、接地接点、或电源接点)的数量。
另外，应可理解地，如图7A所示的电子封装结构7，也可依据图5A的金属架55新增板体551，即该金属架55包含有板体551及位于该板体551周围的电性接触垫550(如图7B所示)。具体地，该金属架55的制作为将导线架进行半蚀刻制程，而使导线架形成断差(即该电性接触垫550的高度d与该板体551的高度e不同)，以用同一导线架形成支撑(stand-off)并联结该承载件20，且该承载件20的第一表面20a上较高的元件(如第一电子元件21)不会碰触该金属架55。例如，该第一包覆层24的高度a为430微米(um)、该承载件20的高度b为160微米(um)、该导电元件53的高度c为50微米(um)、该电性接触垫550的高度d为385微米(um)、及该板体551的高度e为125微米(um)。
因此，本发明的电子封装结构3,7，通过该板体351,451,451’,551的设计，以传导该多个第一电子元件21,41,41’的热量，故能提升该电子封装结构3,7的散热效果。
另外，该电性接触垫250也可外露于该第二包覆层26的侧面26c(如图3及图3A所示)，使该电子封装结构3类似四方平面无引脚封装(Quad Flat No-leads，简称QFN)结构。
本发明提供一种电子封装结构2,2’,3,5,5’,6,6’,7，其包括：一承载件20、第一电子元件21,41,41’、第二电子元件22,22’、多个导电元件23,23’,23”,53,53’、至少一金属架25,25”,35,45,45’,45”,55以及一第一与第二包覆层24,26。
所述的承载件20具有相对的第一侧20a与第二侧20b。
所述的第一电子元件21,41,41’设于该承载件20的第一侧20a上。
所述的第二电子元件22,22’设于该承载件20的第二侧20b上。
所述的导电元件23,23’,23”,53,53’设于该承载件20的第一侧20a及/或该第二侧20b上。
所述的金属架25,25”,35,45,45’,45”,55包含有多个结合至该多个导电元件23,23’,23”,53,53’上的电性接触垫250,550。
所述的第一与第二包覆层24,26形成于该承载件20及/或该金属架25,25”,35,45,45’,45”,55上且包覆该第二电子元件22,22’及/或该第一电子元件21,41,41’及/或该多个导电元件23,23’,23”,53,53’。
于一实施例中，该导电元件23,23’,23”,53,53’为锡膏、导电胶、焊球、铜核心球、被动元件或金属件。
于一实施例中，该电性接触垫250外露于该第二包覆层26的第一表面26a(及侧面26c)。
于一实施例中，该金属架35,45,45’,45”,55还包含对应该第一电子元件21,41,41’位置的板体351,451,451’,551。例如，该电性接触垫250与该板体351,451,451’,551相分离。
于一实施例中，该板体351,451’,551未接触该第一电子元件21,41’。
于一实施例中，该板体451接触该第一电子元件41。
于一实施例中，该板体451通过中介层48结合至该第一电子元件21上。
于一实施例中，该导电元件53’通过绝缘体53”结合该承载件20。
综上所述，本发明的电子封装结构及其制法，通过在导电元件上结合该金属架，且使该金属架外露于该包覆层以作为电性接点，故使用共用模压模具形成该包覆层即可，而无需配合该电子封装结构的尺寸，因而能降低生产成本。
此外，通过该板体的设计，以提升该电子封装结构的散热效果。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (28)

1.一种电子封装结构，其特征为，该电子封装结构包括：
承载件；
电子元件，其接置于该承载件上；
多个导电元件，其接置于该承载件上；
金属架，其包含有多个电性接触垫以供结合至该多个导电元件上；以及
包覆层，其形成于该承载件及/或该金属架上，以包覆该电子元件及/或该多个导电元件。
2.根据权利要求1所述的电子封装结构，其特征为，该承载件为封装基板、无核心层的线路结构或导线架。
3.根据权利要求1所述的电子封装结构，其特征为，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上分别设有该电子元件。
4.根据权利要求1所述的电子封装结构，其特征为，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上方分别设有该金属架。
5.根据权利要求1所述的电子封装结构，其特征为，该电子元件位于该承载件与该金属架之间。
6.根据权利要求1所述的电子封装结构，其特征为，该导电元件为锡膏、导电胶、焊球、铜核心球、被动元件或金属件。
7.根据权利要求1所述的电子封装结构，其特征为，该金属架为导线架。
8.根据权利要求1所述的电子封装结构，其特征为，该电性接触垫外露于该包覆层。
9.根据权利要求1所述的电子封装结构，其特征为，该金属架还包含有对应该电子元件位置的板体。
10.根据权利要求9所述的电子封装结构，其特征为，该电性接触垫与该板体相分离。
11.根据权利要求9所述的电子封装结构，其特征为，该板体与该电性接触垫的高度相同或不同。
12.根据权利要求9所述的电子封装结构，其特征为，该板体接触或未接触该电子元件。
13.根据权利要求9所述的电子封装结构，其特征为，该板体通过中介层结合至该电子元件上。
14.根据权利要求1所述的电子封装结构，其特征为，至少一该导电元件通过绝缘体结合该承载件。
15.一种电子封装结构的制法，其特征为，该制法包括：
提供一电子组件，其包含承载件、以及接置于该承载件上的电子元件与多个导电元件；
将该电子组件透过该导电元件结合至一金属架上，其中，该金属架包含有多个电性接触垫，以供该金属架通过该多个电性接触垫结合该导电元件；以及
形成包覆层于该承载件及/或该金属架上，以包覆该电子元件及/或该多个导电元件。
16.根据权利要求15所述的电子封装结构的制法，其特征为，该承载件为封装基板、无核心层的线路结构或导线架。
17.根据权利要求15所述的电子封装结构的制法，其特征为，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上分别设有该电子元件。
18.根据权利要求15所述的电子封装结构的制法，其特征为，该承载件具有相对的第一侧与第二侧，且于该第一侧与该第二侧上方分别设有该金属架。
19.根据权利要求15所述的电子封装结构的制法，其特征为，该电子元件位于该承载件与该金属架之间。
20.根据权利要求15所述的电子封装结构的制法，其特征为，该导电元件为锡膏、导电胶、焊球、铜核心球、被动元件或金属件。
21.根据权利要求15所述的电子封装结构的制法，其特征为，该金属架为导线架。
22.根据权利要求15所述的电子封装结构的制法，其特征为，该电性接触垫外露于该包覆层。
23.根据权利要求15所述的电子封装结构的制法，其特征为，该金属架还包含有对应该电子元件位置的板体。
24.根据权利要求23所述的电子封装结构的制法，其特征为，该电性接触垫与该板体相分离。
25.根据权利要求23所述的电子封装结构的制法，其特征为，该板体与该电性接触垫的高度相同或不同。
26.根据权利要求23所述的电子封装结构的制法，其特征为，该板体接触或未接触该电子元件。
27.根据权利要求23所述的电子封装结构的制法，其特征为，该板体通过中介层结合至该电子元件上。
28.根据权利要求15所述的电子封装结构的制法，其特征为，至少一该导电元件通过绝缘体结合该承载件。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110473867A (zh) * 2018-05-09 2019-11-19 矽品精密工业股份有限公司 电子封装件及其制法
CN112054005A (zh) * 2019-06-05 2020-12-08 矽品精密工业股份有限公司 电子封装件及其制法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102117477B1 (ko) * 2015-04-23 2020-06-01 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조방법
KR102039711B1 (ko) * 2018-03-13 2019-11-01 삼성전자주식회사 팬-아웃 부품 패키지
JP2021190847A (ja) * 2020-05-29 2021-12-13 株式会社村田製作所 高周波モジュールおよび通信装置
KR20240133730A (ko) * 2022-01-04 2024-09-04 스카이워크스 솔루션즈, 인코포레이티드 세장형 상호연결 부재들을 갖는 기계적으로 강화된 전기 패키지들
WO2023158970A1 (en) * 2022-02-15 2023-08-24 Skyworks Solutions, Inc. Electrical packages with non-linear interconnect members

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325755A (zh) * 2012-03-21 2013-09-25 南茂科技股份有限公司 半导体封装结构
CN104733419A (zh) * 2013-12-20 2015-06-24 乾坤科技股份有限公司 三维空间封装结构及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790378A (en) * 1995-09-22 1998-08-04 National Semiconductor Corporation High density integrated circuit package including interposer
US6137164A (en) * 1998-03-16 2000-10-24 Texas Instruments Incorporated Thin stacked integrated circuit device
US6424034B1 (en) * 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
JP5707902B2 (ja) * 2010-12-02 2015-04-30 ソニー株式会社 半導体装置及びその製造方法
US9312198B2 (en) * 2013-03-15 2016-04-12 Intel Deutschland Gmbh Chip package-in-package and method thereof
KR102337876B1 (ko) * 2014-06-10 2021-12-10 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10546847B2 (en) * 2015-03-27 2020-01-28 Fairchild Semiconductor Corporation Substrate interposer on a leadframe

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325755A (zh) * 2012-03-21 2013-09-25 南茂科技股份有限公司 半导体封装结构
CN104733419A (zh) * 2013-12-20 2015-06-24 乾坤科技股份有限公司 三维空间封装结构及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110473867A (zh) * 2018-05-09 2019-11-19 矽品精密工业股份有限公司 电子封装件及其制法
CN112054005A (zh) * 2019-06-05 2020-12-08 矽品精密工业股份有限公司 电子封装件及其制法

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