TWI235464B - Carried structure of integrated electronic element and method for fabricating the same - Google Patents

Carried structure of integrated electronic element and method for fabricating the same Download PDF

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Publication number
TWI235464B
TWI235464B TW093130822A TW93130822A TWI235464B TW I235464 B TWI235464 B TW I235464B TW 093130822 A TW093130822 A TW 093130822A TW 93130822 A TW93130822 A TW 93130822A TW I235464 B TWI235464 B TW I235464B
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TW
Taiwan
Prior art keywords
layer
core board
semiconductor
integrated electronic
patent application
Prior art date
Application number
TW093130822A
Other languages
Chinese (zh)
Other versions
TW200612522A (en
Inventor
Chi-Ming Chen
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093130822A priority Critical patent/TWI235464B/en
Application granted granted Critical
Publication of TWI235464B publication Critical patent/TWI235464B/en
Publication of TW200612522A publication Critical patent/TW200612522A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A carried structure of integrated electronic element and a method for fabricating the same are proposed. A core substrate formed with a metal layer, capacitive material, and another metal layer on at least one surface thereof is provided to thereby form a plurality of capacitors and circuit structure thereon. At least one hole is formed within the core substrate for accommodating at least a semiconductor element formed with conductive pads thereon. A patterned insulating layer is formed on the core substrate with a plurality of openings to expose the circuit structure, conductive pads, and capacitors. A conductive layer is formed on the surface of the insulating layer and its corresponding openings, and a patterned resist layer is formed thereon to form a circuit structure on the conductive layer via an electroplating process, so as to fabricate a carried structure of integrated electronic element.

Description

1235464 九、發明說明： 【發明所屬之技術領域】 -種整合電子元件之承載板結構及其製法，尤指—種 整合有主動及被動元件之承載板結構及其製作方法。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，i主要 係在-基板或導線架上先裝置半導體晶片，再將半導體晶 片電性連接在基板或導線架上，接著以封装膠體進行封^ 製程，藉以包覆住半導體晶片。其中球栅陣列式（㈣咖 嶋y，BGA)為一種先進的半導體封裝技術，其特點在於採 用基板來女置半導體晶片，並利用自動對位 (self-alignment)技術以於該基板背面植置魏個成拇狀陣 列排列之錫球（Solder ball)，使相同單位面積之半導體晶片 承ΐ件ΐ可以容納更多輸人7輸出連接端_ e峨ecti〇n) 以符合高度集積化（lntegrati0n)之半導體晶片所需以藉由 此些錫球將整個封裝單元鮮結並電性連接至外部之印^電 路板。 惟傳統半導體封裝結構係將半導體晶片直接黏貼在基 板頂面位置上並以膠體封裝，而在基板底面植接錫球，如 此由下彺上連續疊置的結構使得整體高度增加，即無法達 到薄小的目的。為降低封裝結構的高度，業界發展出、在基 板上開設有開孔(hole)’以將半導體晶片冑設在開孔内，藉 以降低封裝高度，如美國專利第6,515,356號及第 17930 6 1235464 6,586,824號等所揭露。 請茶閱第1圖，其係為美國專利第6,515,356號所示 之一底穴置晶朝下型球柵陣列式半導體封裝件（cavity DownBGASemlconductorpackage)，其結構係在基板 n 上設有：開孔⑴’於該開孔U1内置入一半導體晶片12, 且6亥半導體晶片12與基板n之間以導線13作電性連接， 並於基板11底面謂體14封裝及在基板11周邊植接複數 個錫球15’使該半導體晶片12位在基板n的開孔⑴内。 —另請參閱第2圖，其係為美國專利第6,586,824號所 不之-底穴置晶朝上型球柵陣型式(Cavity, _㈣ 訂叩，⑽GA)封裝結構，其與前述之結構大致相同，不同 處在於基板21與丰導轉s y ^ 干V版日日片22的作用面朝上，即用以 裝的朦體24位在上方；其主要結構係在基板21上設有一 開孔2H，於該開孔211内置入半導體晶片^， 體晶片22與基板21頂面的作用面之間以導線23電性連 :開封裝’而將半導體晶片22封裝在基板21 幵二又在基板21底面的另-作用面植接錫球 半導之，下型之封裝相似，不同處僅在於 係朝向上方，即供電性連接的面位 在頂面’而作為外部電性連接的錫球25係位在另—面上 然而不管底穴置晶朝上型或底穴置晶朝下型的封裝方 式’ e亥半導體晶片12、22以麟雕1 再作其它的連接m^ ^ 24固定後，並無法 低封裝產品的應用=性°片$接或基㈣裝等，因此降 17930 7 1235464 又該半導體晶片12、2 21丨時係藉由膠帶暫時因〜入基板1卜21的開孔ill、 之接觸面積實際上报小〜而膠T與半導體晶片12、22 之打線或封裝作業時：：：體晶片12、22進行後續 的情況，故有待改進。/ 肢晶片12、22容易產生移位 再者，無論是採用打線式封農 辛 程，該基板之製程與半導 封封裝製 】之;程機具與製程步驟’且其製程ί:%::::不 另一方面，對於打線式封裝穿、、以成本同。 周圍之線弧密度極高，極易^成八:半導體晶片 ⑽㈣，增加打線作業困：；成另Τ:真觸接產生短路 中，俾氧成片與導線之電路板置於-封錢^ ’、 樹曰（Epoxy)材料置入模且中而妒成田、，6 覆該晶片與導線之封裝膠體。然而程 = 具由於受限於半導體封裝件之設計，故 位置勢必有所# Sn 又/、棋八尺寸與失壓 差/、而4成無法緊密夹固等問題，俟 脂材料時，容易導致封裝耀趙溢 ' * 降低該半導體封裝件之表面平整辦：路=’非但 木“路板上趣欲植㈣叙料位置，㈠彡㈣ 電性連接品質，嚴重影響該半導體封二生 產口口質及產品信賴度。 、此外，前述一般半導體裝置之製程，係首先由晶片承 载件製造業者（例如基板或電路板製造商）生產適用於半導 體裝置之晶片承載件；之後，再將該些晶片承裁件交由半 17930 8 1235464 導體封裝業者進行置晶、模壓、以及植球等製程；最後， 方可完成客戶端所需之電子功能之半導體裝置。其間涉及 不同製程業者（即包含有晶片承載件製造業者與半導體封 裝業者），因此於實際製造過程中不僅步驟煩瑣且界面整合 不易，況且，若客戶端欲進行變更功能設計時，其牽涉變 更與整合層面更是複雜，亦不符合需求變更彈性與經濟效 益。 同對對於現今電子產品在高功能及高速化的趨勢下， 漸需在半導體封裝件上整合有例如電阻器（Resistors)、電 容器（Capacitors)及電感器（Inductors)等被動元件（Passive component)，藉以提昇或穩定電子產品的電性功能。惟一 般多數之被動元件係安置於基板之表面，為避免該被動元 件阻礙半導體晶片與基板多數銲接墊（Bonding fingers)間 之電性連結，傳統上多將該被動元件安置於基板之角端位 置或半導體晶片接置區域外之基板額外佈局面積上。惟限 定被動元件安設位置將縮小基板表面線路佈局 (Routability)之靈活性；同時需考量銲接墊位置，導致該等 被動元件佈設數量受到侷限，不利半導體裝置高度集積化 之發展趨勢；甚者，被動元件佈設數量隨著半導體封裝件 南性能之要求而相對地遽增’如採習知方法該基板表面必 須同時容納多數半導體晶片以及大量被動元件，而迫使裝 件體積增大，亦不符合半導體封裝件輕薄短小之發展潮流。 【發明内容】 鑑於前述習知技術之缺失，本發明之主要目的係在提 9 17930 1235464 供-種整合電子元件之承 元件定位於承載板中。 八衣法，以有效將電子 本發明之次_目的係在提供 結構及其製法，藉以在二:包子兀件之承載 被動元件’以提供較佳電性功^。’整合主動元件與 本發明之又-目的係在 結構及其製法，以省去半導體封褒製^电子凡件之承載 結構= = -種整合 量，並增加線路體裝置—之佈設數 本發明之再一目的係在帝 結構及其製法，俾降低半導"/w子7"件之承载 平丨牛低+導體裝置之整體高度。 載社構及^ = 3目的係在提供—種整合電子元件之承 戰、口構及八W法，以形成半曰曰 製程，藉以提供客戶曰片與曰曰片承載件之整合 f程牛驟“彈性’並簡化半導體業者 衣耘步私、成本及界面整合問題。 結構目的：本發明之整合電子元件之承載 衣/ 乂^土只施步驟係包括：提供至 形成有金屬層m料展μ 依序 杆…： 另—金屬層之核心板，並進 、案衣程於該金屬層、電容材料層及另-金屬層，藉 以在s亥核心板表面形成複數電容元件與線路結構；於該核 板中$成至少—開孔’俾供收納至少—表面具電性連接 塾,半導體元件；於該收納有半導體元件之核心板表面廋 合絕緣層’並加以圖案化該絕緣層以形成複數開口，俾顯 17930 10 1235464 路出部分線路結構、電性 及其對應開口處表面形成導 ^兀件’·於該絕緣層 層，並加以圖案化，俾;=二：該導電層上形成- 圖案化線路結構，以形成整合有；二:δ亥導電層上形成 續即可移除該阻層及其所覆蓋件之：載結構。後 核心板表面之電容元件與線二=電性連接塾及 供更成電容元件及/或增層叫 透過别述製程，本發明亦揭 恭么士媸^, 句路種整合電子元件之承 戰、、、口構’係包括：一且右5小 $，丨、一 /、有至夕一開孔之核心板，該核心板 至少一側表面形成有電容元件， a開孔中收納有至少一 半^肢兀件；一形成於琴妨、、4c y 取、4核心板上之絕緣層；以及至少一 形成於該絕緣層上並電性$康垃 運接至核心板表面之電容元件及 該半導體元件之圖案化線路結構。 因此’本發明之整合電子元件之承載結構及其製法主 要係在：核心板至少一側表面形成電容元件及線路結構 後’再形成複數之開孔’以供例如半導體晶片或晶片型被 動元件等表面設有複數電性連㈣之半導體元件收納於該 開孔’其後再於該核心、板上形成至少—得以電性連接至該 核心板表面之電容元件與線路結構以及半導體元件之圖案 化線路結構，藉此即可形成一同時整合有例如半導體晶片 之主動元件與例如電容元件之被動元件的承載結構，藉以 提供較佳電性功能。此外，本發明係將半導體元件收納於 11 17930 1235464 中，故可降低半導體裳置之整體厚度 小目的，以及將被動元件整合其中， =:紐 佈設數量，並增加表面線路 兀件之 ::裝製程，提供客戶端較大需 製程與界面協調問題。 干¥版業者 【實施方式】 以下心藉由特定的具體實施例說明本發明之實施方 ^，熟習此技藝之人士可由本說明書所揭示之内容 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體貫施例加以施行或應用，本制#巾的各項細節亦 可基於不同觀點與應用’在不悖離本發明之精神下進 種修飾與變更。 以下之貫施例係進一步詳細說明本發明之觀點，但並 非以任何觀點限制本發明之範轉。 請參閱第3A圖至第3M圖，係為本發明所揭露一種 整合電子元件之承載結構之製法剖面示意圖。 如苐3A圖所示，提供一表面依序形成有金屬層、電 容材料層及另一金屬層之核心板。該核心板之製程係可先 提供一上、下表面形成有金屬層30a之核心板30以及表面 具金屬層3la之電容材料層31，以於該表面具金屬層3〇a 之核心板30至少一側表面壓合該表面具金屬層3 1 a之電容 材料層3 1(如第3B圖所示）；其中，該電容材料層31可先 覆蓋於至少一表面具有金屬層3(^之核心板3〇後，再與另 一金屬層31a接合；亦或可使電容材料層31與金屬層31a 12 17930 1235464 先行接合後，再與至少一表面具有 相互接合。川&之核心板30 、，该核心板30可例如為絕緣有機材料或陶 尤材枓’錄其巾形成有多數導通上下 ?! π® Φ \ 鍛導通 、者、不，以作為核心板兩側所形成線路之電性導 通。當然’該核心板並不限於僅由單 亦可由不同絕緣材料 ”斤>成， 成，该金屬層3〇a，31a可 心電容材料層31可例如為介電常數大之高介 毛曰’如μ子材m材m粉末 及其相似物等所組成。 八 同刀子 如弟3C圖所示，圖案化該電容材料層31表面之 層31=及該電容材料層31，以在部分電容材料層31上 形成電谷7L件之第_平行板31b。該圖案化 熟悉之光阻進行影像轉移後飿刻移除完成，在此並不予資 述。接者，再加以圖案化該核心板3G表面金屬層30a，以 /成構成包谷元件之第二平行板3〇b及線路結構列C，藉 以在該核心板表面形成有複數電容元件31()與線路結構曰 3〇c(如第3D圖所示）。 如第3E圖所不’於該核心板3〇中形成至少一開孔 如〇’亚於該核心板3〇之一側設置承載件32，藉以封閉住 :開孔300之一側（如第3F圖所示）。其中，該承載件％ 係可採用一膠片、乾膜膠片、絕緣板或金屬板等，且該承 载件32表面可使其呈黏性或微黏性。 一如第3G圖所示，將至少一表面具電性連接墊33〇之 半導體元件33安置於該承載件32上，並收納於該核心板 17930 1235464 30之開孔300巾；復於該收納有半導體元件％之核心板 3〇表面壓合一絕緣層34,並使該絕緣層34充填於該半導 體兀件33與核心板3〇開孔则間之間隙，以使該半導體 元件33於絕緣層34固化後，可有效固定於該核心板如 開孔300中。其後，復可移除該承載件32，並於先前接置 該承載件32之-側壓合另一絕緣層35(如第3H圖所示 其中，該半導體元件33可為半導體晶片或晶片型被動元 如第31圖所示’圖案化該絕緣層3(35以形成複數開 。40’350，俾頦露出部分線路結構、電性連接塾 及電容元件31〇,並於該絕緣層34,35及其對應開口 340,350處表面形成導電層36。其中，該導電層36主要作 ::述進仃電鍍製程所需之電流傳導路徑，其可由金屬、 合金、p積數層金屬層或導電高分子所構成。 、如第3J圖所示，於該導電層36上形成阻層37，並加 ' θ案化俾藉由電鍍製程以於該導電層％上形成圖案化 ::結構38’如第3Κ圖所示。其中，該阻層37係作用為 二，層’且其可為乾膜或光阻等’以利用印刷、旋塗或 .等方式形成於該導電層36上，再利用曝光、顯影等方 式加以圖案化。 士口 G气 it L圖所示，後續即可移除該阻層37及其所覆芸 之^導> 雷Μ。< Jxa* k °卩分，如此即可在該核心板30中收納有半導 ^ 且在核心板30表面形成有電容元件310,並透 、回案化線路結構38加以電性連接，藉以形成整合有電子 14 17930 1235464 凡件之承载結構。 如第3Μ圖所示1徭庐 上形成電容元件39及'/或二二於該圖案化線路結構38 復請參閱第3L圖所示，士八 元件之承載結構，係包括.且^月亦揭露一種整合電子 板3。，該核心板3。二:成:有具:…開一 30c，且該開孔300中收納有至^谷兀件310及線路結構 成於該核心板上之絕緣層他：二:體元件33; -形 緣層34,35上並電性連接 〆一形成於該絕 及該半導體元株Μ 表面之電容元件310 牛^肢兀件33之圖案化線路結構38。 因此’本發明之整人兩工一 要孫i 一分 。电子几件之承载結構及其製法主 後：少一側表面形成電容元件及線路結構 動凡件寺表面設有複數電性連接塾之被 開孔，其後再於該核心板上形成至少一得二電性=於该 核：板表面之電容元件與線路結構以及半導體元件之^亥 化線路結構，藉此即可形成—同時整合有例，案 之主動元件與例如電容元件之被動元件的承載結：趙= 提供父：電性功能。此外，本發明係將半導； 核心，中’故可降低半導體裝置之整體厚度： 佈設數量’並增加表面線路佈局靈活性，皮動：：之 封裝製程’提供客戶端較大需求彈性 二‘虹 汉間化+導體業者 17930 15 1235464 製程與界面協調問題。 惟以上僅為本發明之較 本發明之實只施例而已，並非用以限定 ί:定義二=錢圍’本發明之實質技術内容係廣 == 專利範圍中，任何他人完成之技術 二下述之申請專利範圍所定義者係完全 利範圍'中π $心更’均將被視為涵蓋於此申請專 【圖式簡單說明】 ，第1圖係為美國專利第6,515,356號之底穴置晶朝下 里球拇陣列式半導體封裝件之剖面示意圖； 第2圖係為美國專利第6,586,824號之底穴置晶朝上 型球柵陣型式封裝結構之剖面示意圖；以及 第3 Α至31V[圖係為本發明之整合電子元件之承載結 構4法之剖面示意圖。 【主要元件符號說明】 11 基板 111 開孔 12 半導體晶片 13 導線 14 膠體 15 錫球 21 基板 211 開孔 22 半導體晶片 16 17930 1235464 23 導線 24 膠體 25 錫球 30 核心板 30a 金屬層 30b 第二平行板 30c 線路結構 300 開孔 31 電容材料層 31a 金屬層 31b 第一平行板 310 電容元件 32 承載件 33 半導體元件 330 電性連接墊 34,35 絕緣層 340,350 絕緣層開口 36 導電層 37 阻層 38 圖案化線路結構 39 電容元件1235464 IX. Description of the invention: [Technical field to which the invention belongs]-A carrier board structure with integrated electronic components and a manufacturing method thereof, in particular-a carrier board structure with integrated active and passive components and a manufacturing method thereof. [Previous technology] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types, i is mainly mounted on a substrate or lead frame, and then the semiconductor wafer is electrically connected to On the substrate or the lead frame, a sealing process is performed with a packaging gel to cover the semiconductor wafer. Among them, ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized by using a substrate to place a semiconductor wafer, and using self-alignment technology to place it on the back of the substrate. Wei ’s solder balls arranged in a thumb-shaped array enable semiconductor wafer support units of the same unit area to accommodate more input terminals (7 output connection terminals_e ecti〇n) to comply with high integration (lntegrati0n ) Of the semiconductor chip is required to use the solder balls to freshly knot the entire package unit and electrically connect to an external printed circuit board. However, the traditional semiconductor packaging structure is to directly paste the semiconductor wafer on the top surface of the substrate and encapsulate it with a gel, and solder balls are implanted on the bottom surface of the substrate. The structure of continuous stacking on the chin makes the overall height increase, that is, it cannot be thin. Small purpose. In order to reduce the height of the packaging structure, the industry has developed a "hole" on the substrate to set the semiconductor wafer in the hole, thereby reducing the packaging height, such as US Patent Nos. 6,515,356 and 17930 6 1235464 6,586,824 No. revealed. Please refer to Fig. 1. It is a cavity downBGASemlconductor package (cavity downBGASemlconductorpackage) shown in one of the U.S. Patent No. 6,515,356. Its structure is provided on the substrate n: openings ⑴ 'A semiconductor wafer 12 is built into the opening U1, and the semiconductor wafer 12 and the substrate n are electrically connected by a wire 13 and are packaged on the substrate 14 on the bottom surface of the substrate 11 and a plurality of substrates are planted around the substrate 11. Each solder ball 15 'positions the semiconductor wafer 12 in the opening ⑴ of the substrate n. — Please also refer to FIG. 2, which is shown in US Patent No. 6,586,824-Cavity-type crystal upward ball grid array (Cavity, _㈣ order, ⑽GA) package structure, which is approximately the same as the aforementioned structure The difference is that the active surface of the substrate 21 and Fengdaozhu sy ^ dry V-version sunscreen film 22 is facing up, that is, the body for mounting is 24 above; its main structure is provided with an opening 2H on the substrate 21 A semiconductor wafer is built into the opening 211, and the body wafer 22 and the active surface of the top surface of the substrate 21 are electrically connected with a lead 23: unpacking, and the semiconductor wafer 22 is packaged on the substrate 21, and then the substrate 21 The other side of the bottom surface is implanted with a solder ball semiconductor. The package of the lower type is similar, except that it is oriented upwards, that is, the surface of the power supply connection is on the top surface, and the 25 ball series is used as an external electrical connection. It is located on the other side, but it doesn't matter whether the bottom cavity is set up or the bottom cavity is set down. 'E Hai semiconductor wafers 12, 22 are formed by lindiao 1 and then other connections are fixed. It cannot be used for low-package products = properties such as chip connection or base mounting, so it is reduced by 17930 7 1235464 The semiconductor wafers 12, 2 and 21 are caused by the tape temporarily contacting the openings ill in the substrate 1 and 21, and the contact area is actually small. The bonding or bonding of the glue T to the semiconductor wafers 12, 22: : The subsequent conditions of the body wafers 12 and 22 need to be improved. / The limb chips 12 and 22 are prone to displacement. Moreover, whether it is a wire bonding process, the process of the substrate and the semiconducting package]; process equipment and process steps'; and its manufacturing process:% :: :: On the other hand, the cost is the same for wire-type packaging. The density of the surrounding arcs is extremely high, which makes it easy to ^ into eight: semiconductor wafers, increase the difficulty of wire bonding :; another T: in the case of a short circuit caused by true contact, the circuit board of the oxygen film and the wire is placed-sealed ^ ', Epoxy material was placed in the mold and jealous of Narita, 6 encapsulating gel covering the chip and wires. However, Cheng = Due to the limited design of the semiconductor package, the position is bound to have # Sn and /, the size and pressure drop difference, and 40% can not be tightly clamped, etc., when grease materials, it is easy to cause Package Yiu Zhao Yi '* Reduce the surface leveling of this semiconductor package: Road =' Feidanmu 'road boards are interested in planting the location of the materials, and the quality of electrical connection, which seriously affects the production of this semiconductor package. Quality and product reliability. In addition, in the aforementioned general semiconductor device manufacturing process, wafer carrier manufacturers (such as substrate or circuit board manufacturers) first produce wafer carriers suitable for semiconductor devices; after that, these wafers The contracted parts are handed over to the semi-conductor packaging company for the process of crystal placement, molding, and ball implantation; finally, the semiconductor device with the electronic functions required by the client can be completed. In the meantime, different process operators (including chips) are involved. Carrier manufacturers and semiconductor packaging manufacturers), so in the actual manufacturing process, not only the steps are cumbersome and the interface integration is not easy. Moreover, if the client wants When changing the function design, it involves more complicated changes and integration, and it does not meet the needs of change flexibility and economic benefits. For the current trend of high-function and high-speed electronic products, the same needs to be integrated on semiconductor packages. There are passive components such as resistors, capacitors, and inductors to improve or stabilize the electrical functions of electronic products. However, most passive components are generally placed on the surface of the substrate. In order to prevent the passive element from hindering the electrical connection between the semiconductor wafer and most of the bonding fingers of the substrate, traditionally, the passive element is usually placed on the corner position of the substrate or on the additional layout area of the substrate outside the semiconductor wafer connection area. However, limiting the placement of passive components will reduce the flexibility of the surface layout of the substrate. At the same time, the position of the solder pads needs to be considered, which limits the number of these passive components, which is not conducive to the development trend of highly integrated semiconductor devices. , The number of passive component layout with the semiconductor package south The demand for energy has increased relatively. If the conventional method is adopted, the substrate surface must accommodate most semiconductor wafers and a large number of passive components at the same time, forcing the mounting volume to increase, and it does not meet the trend of thin and thin semiconductor packages. [Invention Content] In view of the lack of the aforementioned conventional technology, the main purpose of the present invention is to provide 9 17930 1235464-a type of integrated electronic component supporting component positioned in the supporting plate. It is to provide a structure and a manufacturing method thereof, so as to provide a better electrical performance in the second aspect: the passive components of the buns are provided with a passive element. 'The integration of active components with the present invention is aimed at the structure and the manufacturing method to eliminate Semiconductor sealing system ^ The carrying structure of electronic parts = =-a kind of integration amount, and increase the number of circuit body devices-Another object of the present invention is in the emperor structure and its manufacturing method, to reduce the semiconductor " / w 子7 " the overall height of the load-bearing flat 丨 low + conductor device. The purpose of the company structure and ^ = 3 is to provide a kind of integrated electronic components, the structure and the eight-W method, to form a half-day process, in order to provide customers with film and film carrier integration f The step of "elasticity" and simplifies the integration of the semiconductor industry, the cost, and the integration of the interface. Structural purpose: The carrier / integrated application step of the integrated electronic component of the present invention includes the steps of: providing to the material exhibition where the metal layer is formed. μ Sequential rod ...: Another—the core board of the metal layer, progresses in parallel with the metal layer, the capacitor material layer, and the other-metal layer, so as to form a plurality of capacitor elements and circuit structures on the surface of the core board; In the core board, at least—the openings are provided for receiving at least—the surface is electrically connected to the semiconductor element; an insulating layer is bonded to the surface of the core board containing the semiconductor element and the insulating layer is patterned to form a plurality. Opening, display 19730 10 1235464 The circuit structure, electrical properties, and the surface of the corresponding openings form a conductive element on the surface of the opening, and the pattern is formed on the insulating layer, 俾; = 二: The conductive layer is formed- pattern Circuit structure to form an integrated structure; second: the delta layer is formed on the conductive layer to remove the resistive layer and its covered components: the carrier structure. The capacitive element and the line on the surface of the rear core board are electrically connected; and For the conversion of capacitive elements and / or additional layers, the process is described in other ways. The present invention also reveals the respect of the integration of electronic components, including the following: 1 and the right 5 small $ A core board with openings at the end of the day, a capacitive element is formed on at least one side surface of the core board, and at least half of the limbs are stored in the openings; one is formed in the piano, 4c y And an insulating layer on the core board; and at least one capacitive element and a patterned circuit structure of the semiconductor element formed on the insulating layer and electrically connected to the surface of the core board. Therefore, the 'integration of the present invention The load-bearing structure of electronic components and its manufacturing method are mainly: after the capacitor element and the circuit structure are formed on at least one surface of the core board, a plurality of openings are formed to provide multiple electrical properties on the surface such as a semiconductor wafer or a wafer-type passive component. Flail semiconductor devices It is housed in the opening and then formed at least on the core and the board—capacitive elements and circuit structures electrically connected to the surface of the core board and patterned circuit structures of semiconductor elements, thereby forming a simultaneous integration. There are supporting structures such as active components of semiconductor wafers and passive components such as capacitors to provide better electrical functions. In addition, the present invention stores semiconductor components in 11 17930 1235464, so the overall thickness of the semiconductor can be reduced. Small purpose, and the integration of passive components, =: the number of layout, and increase the number of surface circuit components :: assembly process, to provide the client with large-scale process and interface coordination issues. Dry version industry [Implementation] The following The specific embodiments are used to explain the implementation of the present invention. Those skilled in the art can understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments, and various details of the ## towel can also be modified and changed based on different viewpoints and applications' without departing from the spirit of the present invention. The following examples are provided to further illustrate the viewpoints of the present invention, but they are not intended to limit the scope of the present invention in any way. Please refer to FIG. 3A to FIG. 3M, which are schematic cross-sectional views of a manufacturing method of an integrated electronic component carrying structure disclosed in the present invention. As shown in Fig. 3A, a core board having a metal layer, a capacitor material layer, and another metal layer sequentially formed on a surface is provided. The manufacturing process of the core board can first provide a core board 30 with a metal layer 30a formed on the upper and lower surfaces and a capacitor material layer 31 with a metal layer 31a on the surface, so that the core board 30 with the metal layer 30a on the surface is at least A capacitor material layer 3 1 with a metal layer 3 1 a on the surface is laminated on one surface (as shown in FIG. 3B); wherein, the capacitor material layer 31 may cover at least one surface having a core with a metal layer 3 (^ After the plate 30, it is then joined with another metal layer 31a; or the capacitor material layer 31 and the metal layer 31a 12 17930 1235464 can be joined before joining with at least one surface. The core plate 30 of Sichuan & The core board 30 may be, for example, an insulating organic material or a ceramic material, and its towel is formed with a large number of continuities ?! π® Φ \ Forging continuity, or, no, as the electrical continuity of the lines formed on both sides of the core board. Of course, 'the core board is not limited to being made of a single material but also of different insulating materials. The metal layer 30a, 31a can be a high-capacitance material layer 31 having a high dielectric constant. 'Such as μ child wood m wood m powder and the like As shown in Figure 3C, Batong knife patterned the layer 31 on the surface of the capacitor material layer 31 = and the capacitor material layer 31 to form a _parallel plate 31b of a 7L electric valley on a part of the capacitor material layer 31. The patterned photoresist is etched and removed after image transfer, which is not described here. Then, the patterned metal layer 30a on the 3G surface of the core board is patterned to form the first part of the valley-coated element. The two parallel plates 30b and the line structure row C form a plurality of capacitor elements 31 () and a line structure 30c on the surface of the core board (as shown in FIG. 3D). As shown in FIG. 3E At least one opening hole is formed in the core plate 30, and a carrier 32 is provided on one side of the core plate 30, so as to close: one side of the opening 300 (as shown in FIG. 3F). Among them, The bearing member can be a film, a dry film, an insulating plate or a metal plate, and the surface of the bearing member 32 can be made sticky or slightly sticky. As shown in FIG. 3G, at least one surface The semiconductor element 33 having the electrical connection pad 33 is disposed on the carrier 32 and is housed in the core board 17930 1 235464 30 openings of 300 towels; an insulating layer 34 is laminated on the surface of the core board 30 which contains semiconductor components%, and the insulating layer 34 is filled in the semiconductor element 33 and the core board 30 openings After the insulation layer 34 is cured, the semiconductor element 33 can be effectively fixed in the core board such as the opening 300. Thereafter, the carrier 32 can be removed, and the carrier can be previously connected. 32 of the side-pressing another insulating layer 35 (as shown in FIG. 3H, wherein the semiconductor element 33 may be a semiconductor wafer or a wafer-type passive element as shown in FIG. 31 'patterning the insulating layer 3 (35 to form Plural open. At 40'350, a part of the circuit structure, electrical connection, and capacitor element 31 are exposed, and a conductive layer 36 is formed on the surface of the insulating layers 34, 35 and their corresponding openings 340, 350. Among them, the conductive layer 36 is mainly used as a current conduction path required for the electroplating process, and may be composed of a metal, an alloy, a p-layer metal layer, or a conductive polymer. 3. As shown in FIG. 3J, a resist layer 37 is formed on the conductive layer 36, and a 'θ pattern is added to form a pattern on the conductive layer by electroplating process :: Structure 38' as shown in FIG. 3K Show. The resist layer 37 functions as two layers, and the layer can be a dry film or a photoresist. The resist layer 37 is formed on the conductive layer 36 by printing, spin coating, or other methods, and then applied by exposure, development, or the like. Patterned. As shown in the figure of Shikou G gas it L, the resist layer 37 and its cover can be removed later. < Jxa * k ° 卩 minutes, so that semiconductors can be housed in the core board 30, and a capacitive element 310 is formed on the surface of the core board 30, and the circuit structure 38 is transparently and electrically connected, thereby Form a bearing structure with integrated electronics 14 17930 1235464. As shown in FIG. 3M, a capacitive element 39 and / or 22 are formed on the patterned circuit structure 38. Please refer to FIG. 3L. The bearing structure of the Shiba element includes: Disclose an integrated electronic board 3. The core board 3. Two: Cheng: There is a: ... open a 30c, and the opening 300 contains the ^ Valley Wu 310 and the wiring structure formed on the core board insulation layer he: two: the body element 33;-shape edge layer 34,35 are electrically connected to a patterned circuit structure 38 of a capacitor element 310 and a limb member 33 formed on the surface of the semiconductor element M. Therefore, ‘the whole person has two jobs and one job for Sun i. The load-bearing structure of several electronic parts and its manufacturing method are as follows: a capacitor element and a circuit structure are formed on the surface of the small side; a plurality of electrical connection holes are provided on the surface of the temple; and at least one of them is then formed on the core board. The second electrical property = at the core: the capacitor element and circuit structure on the surface of the board and the semiconductor circuit structure, which can be formed at the same time-at the same time, the active element of the case and the passive element such as the capacitive element Bearer knot: Zhao = Provide parent: electrical function. In addition, the present invention is a semi-conductor; the core, medium 'so it can reduce the overall thickness of the semiconductor device: the number of layouts' and increase the flexibility of the surface circuit layout, the skinny :: the packaging process 'provides greater flexibility for the client's second demand' Honghan Intermediate + Conductor Industry 17930 15 1235464 Process and interface coordination issues. However, the above is only an example of the present invention and is more than an example of the present invention. It is not intended to limit ί: Definition 2 = Qianwei 'The essential technical content of the present invention is wide == In the scope of the patent, any other person has completed the second technology. The scope of the patent application described above is defined as the full range of benefits. “中 π $ 心 更” will be considered to be included in this application. [Simplified illustration of the figure], Figure 1 is the bottom hole of US Patent No. 6,515,356. Figure 2 is a schematic cross-sectional view of a ball-thumb-array semiconductor package with a crystal facing down; Figure 2 is a schematic cross-sectional view of a bottom-hole crystal-facing ball grid array type package structure of US Patent No. 6,586,824; and 3A to 31V [ The figure is a schematic cross-sectional view of the method 4 of the supporting structure of the integrated electronic component of the present invention. [Description of main component symbols] 11 substrate 111 opening 12 semiconductor wafer 13 wire 14 colloid 15 solder ball 21 substrate 211 hole 22 semiconductor wafer 16 17930 1235464 23 wire 24 colloid 25 solder ball 30 core board 30a metal layer 30b second parallel plate 30c Circuit structure 300 Opening 31 Capacitive material layer 31a Metal layer 31b First parallel plate 310 Capacitive element 32 Carrier 33 Semiconductor element 330 Electrical connection pad 34, 35 Insulating layer 340, 350 Insulating layer opening 36 Conductive layer 37 Resistive layer 38 Patterning Circuit structure 39 capacitor

Claims (1)

1235464 十、申請專利範圍： r一種整合電子元件之承载結構之製法，係包括. 及另提二至：一側表面依序形成有金屬層、電容材料層 及另一金屬層之核心板，· ^ ΎΎ 3 圖案化該金屬層、電容材料層及另一全 # 在該核心板表面形成複數電容元件； θ，错以 於該核心板中形成至少一開孔:俾供 面具電性連接墊之半導體元件； ^表 於該收納有半導體元件之核心板表 層，並加以圖幸化兮紹έ矣昆 豕 α木化n緣層以形成複數開口 琶性連接墊及電容元件； 早颂路出 於該絕緣層及其對應開口處表面形成導電 :該導電層上形成阻層，並加以圖案曰’ 錄製程以於該導電層上形成圖案化線路結構。错“ .:申f專利範圍第1項之整合電子元件之承载結構之制 八中，該電容材料層可先覆蓋於至少一衣 屬層之核心板後，再與另一金屬層接合。、/、有金 3.=申請專利範圍第！項之整合電子元件之㈣ 容材料層與金屬層先行接合後:。再與： 1面/、有i屬層之核心板相互接入。 〆、 1申請項之整合電子‘之錢結 法，设包括移除該阻層及其所覆蓋之導♦層 衣 範圍第4項之整合電子元件:心 法，復包括於該圖案化線路結構上形成電容元件’藉2 17930 1235464 提供更多電性功能。 6. 如申請專利範圍第4項之整 法，稽白缸从 凡件之承载結構之劁 ::括於該圖案化線路結構：衣 7. 如申請專利範㈣丨項之整合電子θ =路結構。 法，其中，於圖案化該核心板表面之八：承載結構之製 有線路結構。 板表面之金屬層時，係形成 項之整合電子元件之承載結構之製 ^半¥月旦元件為半導體晶片。 .、：：：利範圍第!項之整合電子元 法，其中，該半導體元件為被動元件。I·。構之製 1 〇.如申请專利範圍第丨項 人 製法，其中，”容材料二:電子7^件之承載結構之 11. 如申請專利範圍第i ，丨宅材枓。 势法，苴Λ σ电子70件之承载結構之 二/、，s亥核心板之一侧係設置有承载件，，以封 :该核心板開孔之一側’俾供半導體元件接：、 12. 如申請專利範圍第1 敕人命 八上。 製法，1中，兮絕绫展古古正σ电子兀件之承載結構之 八中5亥絕緣層充填於該半導體元件蛊桉、、心 範圍乙項之整合電子元件之承載結構之 者。，、中’忒¥電層為金屬層及導電高分子之其中一 14:申請專利範圍第】項之整合電子元 製法，其中，該阻層係作用為電鑛阻層。構之 15· 一種整合電子元件之承載結構，係包括： 17930 19 1235464 八有至少一開孔之核心板，該核心板表面形成有 毛谷兀件’且該開孔中收納有至少—半導體元件； 形成於該核心板上之絕緣層；以及 至 > 一形成於該絕緣層上並電性連接至核心板表 面之電容元件及料導體元件之圖案化線路結構。 16=申請專利範圍第15項之整合電子元件之承载結構， 八中，該核心板表面復形成有線路結構。 17. 如申請專利範圍第15項之整合電子元件之承载社構， 极包括形成於該圖案化線路結構上之電容元件。 18. 如申請專利範圍第15項之整合電子元件之承载結構， 後包括形成於該圖案化線路結構上之增層線路结構。 19·如申請專利範圍第15項之整合電子元件之承 其中，該半導體元件係為半導體晶片。 請專：範圍第15項之整合電子元件之承 其中，該半導體元件係為被動元件。 再 2L如申請專利範圍第15項之整合電子元件之承 ， 其中，該電容材料為介電常數大之高介電材料。 22.如申請專利範圍第15項之整合電子元件之承載 其中，該絕緣層充填於該半導體元件與核心、° ’ 間隙，以使該半導體元件固定於該核心板中。 B之 17930 201235464 10. Scope of patent application: r A manufacturing method of integrated electronic component load-bearing structure, including. And mention two to one: a core board in which a metal layer, a capacitor material layer and another metal layer are sequentially formed on one surface, · ^ ΎΎ 3 patterning the metal layer, the capacitor material layer, and another # forming a plurality of capacitive elements on the surface of the core board; θ, at least one opening is formed in the core board: 俾 for the electrical connection pad of the mask Semiconductor components; ^ The surface of the core board containing the semiconductor components is shown on the surface of the core board, and the structure is composed of the α-wooden n edge layer to form a plurality of open-shaped pads and capacitor elements. The surface of the insulating layer and its corresponding opening is conductive: a resistive layer is formed on the conductive layer, and a pattern is recorded to form a patterned circuit structure on the conductive layer. False ".: In the eighth system of the integrated electronic component bearing structure of the first patent application, the capacitor material layer can be covered with at least one core layer of the core board, and then bonded with another metal layer., / 、 Youjin 3. = Integrated electronic components of the scope of the patent application! Item 材料 The capacitive material layer and the metal layer are first joined together: and then connected to: 1 side /, the core board with i layer is connected to each other. 〆, 1 The application of the integrated electronics' money settlement method includes the removal of the resistive layer and the guides it covers. The integrated electronic component of item 4 of the coating: the heart method, which is formed on the patterned circuit structure. Capacitor element 'provides more electrical functions by 2 17930 1235464. 6. If the whole method of the fourth scope of the patent application is applied, the white cylinder shall bear the bearing structure of all parts :: enclosed in the patterned circuit structure: clothing 7 For example, the integrated electron θ = circuit structure of the patent application item, where the pattern of the surface of the core board: the bearing structure is made of the circuit structure. The metal layer on the surface of the board is the integration of the terms. System for carrying structure of electronic components ^ Half ¥ Once the element is a semiconductor wafer .. ::: Integrated electronic element method of the scope of item!, Where the semiconductor element is a passive element. I. Structure of the system 1 10. If the patent application scope of the man-made method, Among them, "capacitor material 2: the load-bearing structure of electronic 7 ^ pieces. For example, if the scope of patent application i, 丨 house materials 枓. Potential method, 苴 Λ σ 70 of the bearing structure of the second part of the / /, one side of the core board is provided with a carrier, to seal: one side of the opening of the core board '俾 for semiconductor components connected :, 12. If the scope of patent application is 1st, the number of lives is eight. Manufacturing method, No. 1 is the carrier structure of the ancient and ancient sigma electronic components in the 8th and 5th insulation layers filled with the semiconductor device, the integrated electronic component bearing structure of the second area. The electric layer is one of a metal layer and a conductive polymer. 14: The integrated electronic component manufacturing method of item No. 14 of the scope of the patent application, wherein the resistive layer functions as a resistive layer for electrical deposits. Structure 15 · A bearing structure for integrating electronic components, comprising: 17930 19 1235464 Eight core plates with at least one opening, a surface of the core plate is formed with woolen elements, and at least-semiconductor components are accommodated in the openings. An insulating layer formed on the core board; and a patterned circuit structure of a capacitive element and a material conductor element formed on the insulating layer and electrically connected to the surface of the core board; 16 = The bearing structure of the integrated electronic component in the scope of the patent application No. 15; In the eighth, the core board has a circuit structure formed on the surface. 17. If the carrier structure of an integrated electronic component is claimed in item 15 of the scope of patent application, the pole includes a capacitor element formed on the patterned circuit structure. 18. For example, the supporting structure of the integrated electronic component under the scope of the patent application No. 15 includes a layered circuit structure formed on the patterned circuit structure. 19. According to the acceptance of the integrated electronic component in the scope of the patent application No. 15, wherein the semiconductor component is a semiconductor wafer. Please specialize: the acceptance of integrated electronic components in scope 15 of which the semiconductor component is a passive component. The second 2L is the acceptance of the integrated electronic component in item 15 of the scope of patent application, in which the capacitor material is a high dielectric material with a large dielectric constant. 22. The bearing of an integrated electronic component according to item 15 of the application, wherein the insulation layer is filled in the gap between the semiconductor element and the core, so that the semiconductor element is fixed in the core board. B of 17930 20
TW093130822A 2004-10-12 2004-10-12 Carried structure of integrated electronic element and method for fabricating the same TWI235464B (en)

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