CN107017288B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

Info

Publication number
CN107017288B
CN107017288B CN201610940128.5A CN201610940128A CN107017288B CN 107017288 B CN107017288 B CN 107017288B CN 201610940128 A CN201610940128 A CN 201610940128A CN 107017288 B CN107017288 B CN 107017288B
Authority
CN
China
Prior art keywords
layer
semiconductor device
insulating film
metal
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610940128.5A
Other languages
English (en)
Other versions
CN107017288A (zh
Inventor
栗林秀直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN107017288A publication Critical patent/CN107017288A/zh
Application granted granted Critical
Publication of CN107017288B publication Critical patent/CN107017288B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05172Vanadium [V] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518Molybdenum [Mo] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05558Shape in side view conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明的半导体装置抑制由氢导致的特性劣化。提供一种半导体装置,具备:半导体基板;设置于半导体基板的上表面的上方,且由具有储氢性的第一金属形成的储氢层;设置于储氢层的上方,且由第一金属的氮化物形成的氮化物层;设置于氮化物层的上方,且由铝和第二金属的合金形成的合金层;以及设置于合金层的上方,且由铝形成的电极层,在电极层和氮化物层之间,不设置有第二金属的纯金属层。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
以往,已知有由铝形成源极等电极且在半导体基板和铝电极之间设有阻挡金属的半导体装置(例如参照专利文献1)。
专利文献1:日本特开2012-129503号公报
发明内容
技术问题
当将由铝形成的电极置于高温环境下时,存在产生氢的情况。例如,当铝和水分反应时产生氢。若氢进入栅极绝缘膜和半导体层的界面附近,则在该界面产生正电荷,导致阈值电压发生变动。
对此,考虑在铝电极的下方形成钛等储氢金属层。通过由储氢金属吸收氢,能够抑制氢进入栅极绝缘膜的界面附近。然而,若铝和储氢金属发生合金化,则储氢功能降低。
技术方案
在本发明的第一形态中,提供具备半导体基板、储氢层、氮化物层、合金层以及电极层的半导体装置。储氢层可以设置在半导体基板的上表面的上方,且由具有储氢性的第一金属形成。氮化物层可以设置在储氢层的上方,且由第一金属的氮化物形成。合金层可以设置在氮化物层的上方,由铝和第二金属的合金形成。电极层可以设置在合金层的上方,且由铝形成。在电极层和氮化物层之间,可以不设置第二金属的纯金属层。
第一金属可以为钛。第二金属可以为钛、钼、钨、钒、铬、铜以及镍中的任一种。第二金属可以为钛。
合金层的厚度可以为15nm以上。合金层的厚度可以为0.5μm以下。电极层的厚度可以为3μm以下。电极层的厚度可以为1μm以上且2μm以下。
上述半导体装置,还可以具备设置于上述电极层的上方的焊料层。合金层可以至少形成于与焊料层对置的区域。半导体装置还可以具备设置在半导体基板的上表面的上方处的层间绝缘膜。在层间绝缘膜可以形成有使形成于半导体基板的上表面的源区露出的开口。储氢层、氮化物层以及合金层可以形成在层间绝缘膜的开口的上方。
储氢层、氮化物层以及合金层还可以形成于沿着层间绝缘膜的开口的侧面的区域。半导体基板可以为碳化硅基板。
在本发明的第二形态中,提供一种半导体装置的制造方法,具备:在半导体基板的上表面的上方,层叠由具有储氢性的第一金属形成的储氢层的步骤;在储氢层的上方,层叠由第一金属的氮化物形成的氮化物层的步骤;在氮化物层的上方,层叠由第二金属形成的前体层的步骤;以及通过在前体层的上层叠铝来利用铝使所有的前体层铝合金化而形成合金层,并且在合金层上形成铝的电极层的步骤。
铝的层叠温度可以为200度以上。
应予说明,上述的发明的主要内容并没有列举出本发明的全部特征。另外,这些特征组中的子组合也可构成本发明。
附图说明
图1是举例表示半导体装置100的上表面的结构的图。
图2是活性区120中的半导体装置100的剖视图。
图3是表示设置在源区20的上方的各电极层的示意图。
图4A是说明形成金属层的工序的图。
图4B是说明形成金属层的工序的图。
图4C是说明形成金属层的工序的图。
图4D是说明形成金属层的工序的图。
图5是比较例的半导体装置200的剖视图。
图6A是表示半导体装置100的电极层50的形状的示意图。
图6B是表示半导体装置200的电极层50的形状的示意图。
图7是表示半导体装置200的金属层的剥离的图。
符号说明
10:半导体基板
12:第一电极层
14:第二电极层
16:漂移层
18:阱区
20:源区
21:漂移区
22:基层
24:接触区
30:栅极绝缘膜
32:栅极
34:层间绝缘膜
36:硅化物区
40:氮化钛层
42:镍层
44:储氢层
46:氮化物层
47:前体层
48:合金层,
50:电极层
52:镀覆层
54:焊料层
56:销
60:金属层
70:金属层
74:空隙
76:侧面
78:上面
100:半导体装置
110:耐压结构部
120:活性区
130:栅极衬垫
200:半导体装置
具体实施方式
以下,虽然通过本发明的实施方式说明本发明,但以下的实施方式并不限定权利要求所涉及的发明。另外,在实施方式中说明的特征的全部组合不限定为解决本发明的技术问题所必需的。
图1是表示半导体装置100的上表面结构的一个例子的图。在本例中,将在与半导体装置100的上表面平行的表面内正交的两个方向设为x方向和y方向,将与x方向和y方向正交的方向设为z方向。在本说明书中将z方向称为深度方向。另外,说明时会将z方向上的相对位置关系表述为上或下。另外,将基板、各层、各区域等在z方向上的上侧的面称为上表面、将下侧的面称为下表面。应予说明,上和下表示相对的位置关系,不一定与重力方向上的上和下一致。
半导体装置100具备半导体基板10。作为一个例子,半导体基板10为碳化硅(SiC)基板。半导体基板10也可以为硅基板等的其他的半导体基板。在半导体基板10,形成有活性区120、栅极衬垫130以及耐压结构部110。在活性区120,形成有IGBT(Insulated GateBipolar Transistor:绝缘栅双极型晶体管)、MOSFET(Metal OxideSemiconductor FieldEffect Transistor:金属-氧化物半导体场效应晶体管)以及FWD(Free Wheel Diode:续流二极管)等的半导体元件。
栅极衬垫130通过形成于半导体基板10的布线与活性区120内的半导体元件等电连接。另外,栅极衬垫130通过引线等与半导体装置100的外部的电路电连接。
另外,在活性区120的上方,形成有作为源极起作用的电极层,但图1中省略了图示。在该电极层通过焊料等连接有一个以上的销。电极层通过该销与外部的电路电连接。
耐压结构部110以包围活性区120的方式沿半导体基板10的边缘而形成。耐压结构部110例如具有保护环、场板、降低表面电场区(Reduced SURfsce Field)以及将它们组合而成的结构。由此,缓和了活性区120的端部等上的电场集中。
图2是活性区120中的半导体装置100的剖视图。该剖视图中表示的是与xz面平行的面。在该剖面中,形成有纵型的MOSFET。本例的半导体基板10为N+型基板。
在半导体基板10上,形成有浓度比半导体基板10低的N-型的漂移层16。本例的漂移层16为掺杂了氮气等N型杂质的SiC外延层。
在漂移层16的上面侧,选择性地形成有P-型的阱区18。换言之,在漂移层16的上面侧,以残留一部分的漂移层16的方式由规定的图案形成阱区18。阱区18例如通过对漂移层16的上表面的规定的区域进行P型杂质的离子注入而形成。
在阱区18和漂移层16的上方,形成有P-型的基层22。本例的基层22是掺杂有铝等P型杂质的SiC外延层。在基层22中的与漂移层16对置的区域,形成有N-型的漂移区21。漂移区21是通过在基层22的规定的区域掺杂氮气等的N型的杂质而形成。
另外,在基层22的一部分的区域,形成有N+型的源区20。源区20通过在基层22的规定的区域掺杂磷等N型杂质而形成。另外,在源区20的一部分的区域,形成有P+型的接触区24。接触区24通过对源区20的规定的区域离子注入氮气等P型杂质而形成。
另外,在源区20和接触区24的上部,形成有硅化物区36。硅化物区36例如由镍硅化物形成。由此,能够使源区20和接触区24与上部的电极欧姆接触。
在与基层22对置的区域,形成有栅极绝缘膜30和栅极32。栅极32例如由多晶硅形成。栅极绝缘膜30设置在栅极32的下方。例如栅极绝缘膜30通过将半导体层的上表面氧化而形成。
栅极绝缘膜30和栅极32至少形成在从与源区20的端部对置的位置至与漂移区21的端部对置的位置。由此,根据施加到栅极32的电压,在基层22形成有沟道。
另外,以覆盖栅极绝缘膜30和栅极32的方式形成有层间绝缘膜34。栅极绝缘膜30、栅极32以及层间绝缘膜34形成为不覆盖接触区24和源区20中的至少一部分。在本例中,形成在接触区24和源区20的上部的硅化物区36,其至少一部分未被栅极绝缘膜30等覆盖而露出。
在层间绝缘膜34的上方,形成有氮化钛层40(TiN)。氮化钛层40覆盖层间绝缘膜34的整个上表面和侧面。层间绝缘膜34的侧面是指与xy面平行的层间绝缘膜34的上表面和与xy面平行的半导体层的上表面之间的层间绝缘膜34的表面。换言之,层间绝缘膜34的侧面是指层间绝缘膜34的表面中的不与xy面平行的面。氮化钛层40还形成在硅化物区36(或者源区20)的一部分的区域上。其中,氮化钛层40形成为不覆盖硅化物区36的至少一部分。
硅化物区36的上方,形成有镍层42。镍层42也可以形成在氮化钛层40的一部分的区域上。其中,镍层42形成为不覆盖氮化钛层40的至少一部分。在与栅极32对置的至少一部分的区域,本例的镍层42不覆盖氮化钛层40。
在镍层42和不被镍层42覆盖的氮化钛层40的上方,形成有由具有储氢性的第一金属形成的储氢层44。在本例中第一金属为钛。当然,第一金属不限于钛,只要具有储氢性且能够作为电极起作用即可。
储氢性是指在能将氢储藏到固体金属中的性质。储氢性金属例如通过氢进入金属原子之间或者通过金属原子被氢置换,从而将氢稳定地储藏到固体中。通过设置储氢层44,能够抑制在比储氢层44更靠近上方的位置产生的氢向比储氢层44靠近下方的栅极绝缘膜30和半导体层移动。因此,能够抑制栅极绝缘膜30的劣化。另外,能够抑制在半导体层和栅极绝缘膜30的界面产生正电荷,能够抑制半导体装置100的阈值变动。
在储氢层44的上方,设置有由第一金属的氮化物形成的氮化物层46。本例中的氮化物层46为氮化钛层。氮化物层46形成为覆盖储氢层44的整个上表面。氮化物层46防止储氢层44与上部的电极材料进行合金化。若储氢层44发生合金化,则储氢性减弱,但通过设置氮化物层46,则能够维持储氢层44的储氢性。
在氮化物层46的上方,形成有由铝和第二金属的合金形成的合金层48。第二金属可以为与第一金属相同的金属,也可以为不同的金属。本例中第二金属为钛。第二金属不限于钛,只要是通过与铝合金化而能形成硬度比铝高的合金,且能使合金层48作为电极的一部分的金属即可。例如第二金属为钛、钼、钨、钒、铬、铜以及镍中的任一种。
合金层48至少形成在与层间绝缘膜34的开口部分对置的范围的区域中。层间绝缘膜34的开口部分是指不被层间绝缘膜34覆盖的部分。另外,合金层48优选还形成在与层间绝缘膜34的侧面对置的范围的区域中。在本例中合金层48形成在氮化物层46的整个上表面。应予说明,在层间绝缘膜34的开口的上方,还形成有储氢层44和氮化物层46。另外,在沿着层间绝缘膜34的开口的侧面的范围,还形成有储氢层44和氮化物层46。
通过设置硬度比铝高的合金层48,能够抑制在比合金层48更靠近上侧的铝产生的应力传递到比合金层48更靠近下侧的位置。因此,能够抑制在比合金层48更靠近下侧的金属层产生形变,抑制该金属层从半导体区域或者层间绝缘膜34剥离。
电极层50形成在合金层48的上方。电极层50由铝形成。电极层50可以形成在合金层48的整个上表面。电极层50优选具有能够吸收由层间绝缘膜34等导致的阶梯差的程度的厚度。电极层50的上表面中的阶梯差小于半导体层的上表面中的阶梯差(即,由层间绝缘膜34等导致的阶梯差)。
在电极层50的上方,形成有镀覆层52。镀覆层52例如由镍形成。在镀覆层52的上表面通过焊料层54连接有销56。销56与半导体装置100的外部电路电连接。对电极层50经由销56施加有源极电压。
焊料层54例如形成在电极层50的上表面中的凹陷。在该情况下,焊料层54配置在与层间绝缘膜34的开口对置的位置。也可以在电极层50的上表面的、应该形成焊料层54的区域形成具有开口的保护膜。在镀覆层52的上表面形成了熔融之后的焊料层54后,焊料层54的温度降低至室温的程度。此时,在与焊料层54对置的电极层50中产生由焊料层54和电极层50的热膨胀系数之差导致的应力。
具体而言,在与焊料层54对置的区域的电极层50,在xy面内沿收缩的方向产生应力。对此,半导体装置100由于具有合金层48,所以如上所述,能够抑制该应力传递到与层间绝缘膜34接触的金属层。优选地,合金层48至少形成在与焊料层54对置的区域。
另外,为了减少电极层50的上表面的阶梯差,电极层50优选在高温的工序中进行层叠。例如电极层50的层叠温度为200度以上。电极层50的层叠温度也可以为300度以上。电极层50的层叠温度可以为400度以下。该温度可以根据半导体装置100的微细化而变高。电极层50可以利用高温回流焊溅射法而形成。
通过在高温下形成电极层50,能够提高电极层50的覆盖范围。另外,半导体装置100由于在储氢层44和电极层50之间具有氮化物层46,即使在高温下形成电极层50,也能够防止储氢层44和电极层50发生合金化。
应予说明,在电极层50和氮化物层46之间,不设置第二金属(本例中为钛)的纯金属层。在本例中,以与氮化物层46接触的方式形成有合金层48,以与合金层48接触的方式形成有电极层50。
合金层48能够通过使形成在氮化物层46的上方的第二金属层和电极层50的铝进行合金化而形成。通过在高温下形成电极层50,使形成在氮化物层46的上方的第二金属全部与铝成为合金。
应予说明,在本例中在半导体基板10的下表面,形成有第一电极层12和第二电极层14。第一电极层12例如为层叠了镍和钛的电极,并且形成在半导体基板10的下表面。第二电极层14例如为层叠了钛、镍以及金的电极,形成在第一电极层12的下表面。本例的第一电极层12和第二电极层14作为漏极起作用。
图3是表示设置在源区20的上方的各金属层的示意图。在本例中氮化钛层40的厚度为50nm以上且200nm以下。作为一个例子,氮化钛层40的厚度为100nm。应予说明,图2所示的层间绝缘膜的厚度为1μm左右,栅极32的厚度为500nm左右。
镍层42的厚度为30nm以上且100nm以下。镍层42可以比氮化钛层40薄。作为一个例子,镍层42的厚度为60nm。
在本例中,储氢层44的厚度为50nm以上且200nm以下。储氢层44的厚度可以与氮化钛层40同等程度。作为一个例子,储氢层44的厚度为100nm。
在本例中氮化物层46的厚度为50nm以上且200nm以下。氮化物层46的厚度可以与储氢层44同等程度。另外,氮化物层46可以比储氢层44薄。氮化物层46只要在形成电极层50时防止储氢层44与铝的合金化即可。作为一个例子,氮化物层46的厚度为100nm。
在本例中,合金层48的厚度为15nm以上且0.5μm以下。若合金层48的厚度比15nm薄,则合金层48的强度变弱,因焊接应力而产生金属层的剥离。另外,即使将合金层48的厚度设为大于0.5μm,也无法相应地提高金属层的剥离抑制效果,导致半导体装置100的厚度将增大。
合金层48可以比氮化物层46薄。另外,合金层48的厚度可以为50nm以上,也可以为100nm以上。应予说明,各金属层的厚度可以为平坦的区域的平均厚度。作为各金属层的厚度,可以使用与层间绝缘膜34不重叠的区域的厚度。
在本例中电极层50的厚度为3μm以下。由于半导体装置100具有氮化物层46,所以能够在高温的工序中形成电极层50。因此,即使形成比较薄的电极层50,也能够提高覆盖范围。电极层50的厚度可以为2μm以下。
其中,若电极层50变得过薄,则认为存在因制造偏差而导致铝全部与钛等第二金属合金化,无法形成纯铝的电极层50的情况。在该情况下,难以形成镀覆层52。因此,电优选的是极层50具有1μm以上的厚度。
应予说明,电形成在极层50的上表面的镀覆层52可以比电极层50厚。在本例中镀覆层52的厚度为5μm。
图4A~图4D是对形成各个金属层的工序进行说明的图。形成各个金属层时的半导体基板10的温度例如为250度。如图4A所示,在半导体基板10的上方,选择性地形成氮化钛层40。在形成有氮化钛层40的半导体基板10的上方,形成镍层42。另外,如图4B所示,在形成有镍层42的半导体基板10的上方,形成储氢层44。另外,在储氢层44的上方形成氮化物层46。
接下来,如图4C所示,在氮化物层46的上方,层叠由钛等第二金属形成的前体层47。前体层47的厚度可以为10nm以上且0.25μm以下。之后,通过250度左右的高温工程(high-temperature process)在前体层47的上方层叠铝。由此,如图4D所示,能够形成覆盖范围大的电极层50。另外,前体层47全部与铝合金化而变成合金层48。利用这样的工序,不会导致储氢层44的储氢性的劣化,而能形成覆盖范围大的电极层50。另外,利用合金层48,能够提高对焊接应力的耐受性。
图5是涉及比较例的半导体装置200的剖视图。相对于半导体装置100的构成,半导体装置200不具有氮化物层46和合金层48。其他的构成与半导体装置100相同。
图6A是表示半导体装置100的电极层50的形状的示意图。在图6A中,将氮化钛层40、镍层42、储氢层44、氮化物层46以及合金层48统称为金属层60。如上所述,半导体装置100的电极层50由于能够在高温工程中形成,所以能够提高覆盖范围。
图6B是表示半导体装置200的电极层50的形状的示意图。在图6B中,将氮化钛层40、镍层42以及储氢层44统称为金属层70。半导体装置200由于不具有氮化物层46,所以无法在高温下形成电极层50。因此,电极层50的覆盖范围小,导致在上表面产生大的凹陷。若有镀液等侵入到该凹陷中,则因镀液中所含的离子的影响,半导体装置100的阈值等的特性发生变动。
图7是表示半导体装置200中的金属层的剥离的图。如上所述,由于焊料层54和电极层50的热膨胀系数差,所以在与焊料层54对置的电极层50,产生向内侧收缩的应力。因此,例如在层间绝缘膜34的侧面76和半导体层的上表面78,氮化钛层40等发生剥离而产生空隙74。若保护用的树脂或者镀液等进入到空隙74中,则因树脂等中所含的离子等导致半导体装置100的阈值等特性发生变动。对此,半导体装置100通过设置合金层48能够抑制氮化钛层40等的剥离。
另外,在200度的气氛下对半导体装置200分别施加10分钟的+3MV/cm和-3MV/cm的栅极电压,分别测定阈值电压的变动。在施加了+3MV/cm的栅极电压之后,阈值电压的偏移量为0.1V以下。然而,在施加了-3MV/cm的栅极电压之后,阈值电压向负方向大幅偏移。
其结果示出,通过在高温气氛下施加大的负栅极电压,在栅极绝缘膜30和SiC等半导体层的界面附近或者栅极绝缘膜30中产生正的固定电荷。推断该固定电荷通过铝的电极层50而产生。
另一方面,对半导体装置100也进行相同的试验。在施加了+3MV/cm的栅极电压和-3MV/cm的栅极电压之后,阈值电压的变动都为0.1V以下。这样,根据半导体装置100,能够抑制阈值电压的变动。
以上,使用实施方式对本发明进行了说明,但本发明的技术范围并不限于上述实施方式中记载的范围。可以对上述实施方式进行多种变更或者改进对本领域技术人员是显而易见的。根据权利要求中记载的内容,进行了多种变更或者改进的实施方式可包含在本发明的技术范围内是显而易见的。
在权利要求、说明书以及附图中示出的装置、系统、程序,以及方法中的动作、顺序、步骤以及阶段等各处理的执行顺序没有特别明示为“在之前”,“先于”等,并且只要不是在后的处理需要使用之前的处理的结果,就可以以任意的顺序实现。关于权利要求、说明书以及附图中的动作流程,为了方便,即使使用“首先”、“接下来”等进行说明,也并不是指必须以该顺序实施。

Claims (17)

1.一种半导体装置,其特征在于,具备:
半导体基板;
栅极绝缘膜,设置于所述半导体基板的上表面;
层间绝缘膜,其设置于所述半导体基板的上表面的上方;
氮化钛层,其设置于所述层间绝缘膜的上方,并且覆盖所述层间绝缘膜的上表面和侧面;
镍层,其设置于所述氮化钛层的上方;
储氢层,设置于所述氮化钛层和所述镍层的上方,且由具有储氢性的第一金属形成;
第一氮化物层,设置于所述储氢层的上方,且由所述第一金属的氮化物形成;
合金层,设置于所述第一氮化物层的上方,且由铝和第二金属的合金形成;
电极层,设置于所述合金层的上方,且由铝形成;
栅极,其设置于所述栅极绝缘膜的上方以及所述储氢层的下方;以及
设置于所述电极层的上方的焊料层,
在所述电极层和所述第一氮化物层之间,不设置有所述第二金属的纯金属层,
所述镍层在与所述栅极对置的至少一部分区域不覆盖所述氮化钛层,
所述合金层至少形成在与所述焊料层对置的区域。
2.根据权利要求1所述的半导体装置,其中,
所述半导体基板具有:
P型的基层;以及
N型的源区,其形成于所述基层的一部分区域,
所述栅极绝缘膜与所述基层的至少一部分以及所述源区的至少一部分相接。
3.根据权利要求1或2所述的半导体装置,其中,
所述第一金属为钛。
4.根据权利要求1或2所述的半导体装置,其中,
所述第二金属为钛、钼、钨、钒、铬、铜以及镍中的任一种。
5.根据权利要求4所述的半导体装置,其中,
所述第二金属为钛。
6.根据权利要求1或2所述的半导体装置,其中,
所述合金层的厚度为15nm以上。
7.根据权利要求6所述的半导体装置,其中,
所述合金层的厚度为0.5μm以下。
8.根据权利要求1或2所述的半导体装置,其中,
所述电极层的厚度为3μm以下。
9.根据权利要求8所述的半导体装置,其中,
所述电极层的厚度为1μm以上且2μm以下。
10.根据权利要求1或2所述的半导体装置,其中,
所述储氢层的厚度为50nm以上且200nm以下。
11.根据权利要求1或2所述的半导体装置,其中,
在所述层间绝缘膜形成有使形成于所述半导体基板的上表面的源区露出的开口,
所述储氢层、所述第一氮化物层以及所述合金层至少形成在所述层间绝缘膜的所述开口的上方。
12.根据权利要求11所述的半导体装置,其中,
所述储氢层、所述第一氮化物层以及所述合金层还形成于沿着所述层间绝缘膜的所述开口的侧面的区域。
13.根据权利要求1或2所述的半导体装置,其中,
所述半导体基板为碳化硅基板。
14.根据权利要求2所述的半导体装置,其中,
所述半导体基板具有:
P型的接触区,其形成于所述源区的一部分区域;以及
硅化物区,其形成于所述源区和所述接触区的上部,
所述栅极绝缘膜不覆盖所述硅化物区的至少一部分区域。
15.一种半导体装置的制造方法,其特征在于,具备:
在半导体基板的上表面形成栅极绝缘膜的步骤;
在所述栅极绝缘膜的上方形成栅极的步骤;
在所述半导体基板的上表面的上方形成层间绝缘膜的步骤;
在所述层间绝缘膜的上方形成覆盖所述层间绝缘膜的上表面和侧面的氮化钛层的步骤;
在所述氮化钛层的上方形成在与所述栅极对置的至少一部分区域不覆盖所述氮化钛层的镍层的步骤;
在所述氮化钛和所述镍层的上方,层叠由具有储氢性的第一金属形成的储氢层的步骤;
在所述储氢层的上方,层叠由所述第一金属的氮化物形成的氮化物层的步骤;
在所述氮化物层的上方,层叠由第二金属形成的前体层的步骤;
通过在所述前体层上层叠铝,利用铝使所有的所述前体层合金化而形成合金层,并且在所述合金层上形成铝的电极层的步骤;以及
在所述电极层的上方形成焊料层的步骤,
所述合金层至少形成在与所述焊料层对置的区域。
16.根据权利要求15所述的半导体装置的制造方法,其中,
所述铝的层叠温度为200度以上。
17.根据权利要求15所述的半导体装置的制造方法,还包括:
在所述半导体基板形成P型的基层的步骤;以及
在所述基层的一部分区域形成N型的源区的步骤;
所述栅极绝缘膜与所述基层的至少一部分以及所述源区的至少一部分相接。
CN201610940128.5A 2015-12-11 2016-10-25 半导体装置及半导体装置的制造方法 Active CN107017288B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015242472A JP6617546B2 (ja) 2015-12-11 2015-12-11 半導体装置および半導体装置の製造方法
JP2015-242472 2015-12-11

Publications (2)

Publication Number Publication Date
CN107017288A CN107017288A (zh) 2017-08-04
CN107017288B true CN107017288B (zh) 2022-07-01

Family

ID=59020091

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610940128.5A Active CN107017288B (zh) 2015-12-11 2016-10-25 半导体装置及半导体装置的制造方法

Country Status (3)

Country Link
US (1) US9735109B2 (zh)
JP (1) JP6617546B2 (zh)
CN (1) CN107017288B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110214175B (zh) 2017-01-23 2022-06-14 普和希控股公司 收纳装置
JP6847020B2 (ja) * 2017-11-17 2021-03-24 株式会社 日立パワーデバイス 半導体チップおよびパワーモジュールならびにその製造方法
JP7472435B2 (ja) 2019-05-13 2024-04-23 富士電機株式会社 半導体モジュールの製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3360835B2 (ja) 1991-02-19 2003-01-07 ソニー株式会社 配線形成方法
JP3262390B2 (ja) * 1992-11-25 2002-03-04 川崎マイクロエレクトロニクス株式会社 金属膜の形成方法
JPH06275555A (ja) * 1993-03-23 1994-09-30 Kawasaki Steel Corp 半導体装置の製造方法
JPH0837163A (ja) * 1994-07-23 1996-02-06 Sony Corp 半導体装置の製造方法
JPH09252131A (ja) * 1996-01-10 1997-09-22 Yamaha Corp 半導体装置の製法
JPH10150041A (ja) * 1996-11-13 1998-06-02 Applied Materials Inc 成膜方法
JPH1126722A (ja) * 1997-07-02 1999-01-29 Fujitsu Ltd 半導体装置及びその製造方法
JP2002075910A (ja) * 2000-08-24 2002-03-15 Sharp Corp 窒化物系iii−v族化合物半導体装置用電極構造の作製方法
JP3913530B2 (ja) * 2001-11-09 2007-05-09 三洋電機株式会社 半導体装置の製造方法
JP2003309124A (ja) * 2003-05-16 2003-10-31 Seiko Epson Corp 半導体装置
JP2005093887A (ja) * 2003-09-19 2005-04-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2005327799A (ja) * 2004-05-12 2005-11-24 Sanyo Electric Co Ltd 半導体装置の製造方法
WO2007060745A1 (ja) * 2005-11-28 2007-05-31 Fujitsu Limited 半導体装置及びその製造方法
US7829416B2 (en) * 2007-08-07 2010-11-09 Panasonic Corporation Silicon carbide semiconductor device and method for producing the same
WO2011040213A1 (en) * 2009-10-01 2011-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5634742B2 (ja) * 2010-04-30 2014-12-03 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置の製造方法
JP5694119B2 (ja) * 2010-11-25 2015-04-01 三菱電機株式会社 炭化珪素半導体装置
JP5628765B2 (ja) * 2011-08-19 2014-11-19 株式会社日立製作所 半導体装置
JP6007770B2 (ja) * 2012-12-14 2016-10-12 豊田合成株式会社 半導体装置
DE112014001741T8 (de) * 2013-03-29 2016-02-18 Fuji Electric Co., Ltd. Halbleitervorrichtung und Verfahren zum Herstellen der Halbleitervorrichtung
EP3043376B1 (en) 2013-09-05 2021-03-03 Fuji Electric Co., Ltd. Method for manufacturing silicon carbide semiconductor element
JP2015053455A (ja) * 2013-09-09 2015-03-19 株式会社東芝 電力用半導体装置及びその製造方法
JP6192190B2 (ja) * 2014-03-11 2017-09-06 富士電機株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置

Also Published As

Publication number Publication date
CN107017288A (zh) 2017-08-04
US9735109B2 (en) 2017-08-15
JP6617546B2 (ja) 2019-12-11
US20170170126A1 (en) 2017-06-15
JP2017108074A (ja) 2017-06-15

Similar Documents

Publication Publication Date Title
JP5525940B2 (ja) 半導体装置および半導体装置の製造方法
CN109075089B (zh) 电力用半导体装置及其制造方法
US11456359B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP4221012B2 (ja) 半導体装置とその製造方法
US10978367B2 (en) Semiconductor device and method for manufacturing the same
CN107408577B (zh) 半导体装置及半导体装置的制造方法
CN106688104B (zh) 半导体装置
CN107017288B (zh) 半导体装置及半导体装置的制造方法
KR20120065962A (ko) 반도체 장치
US10177109B2 (en) Method of manufacturing semiconductor device
US11658093B2 (en) Semiconductor element with electrode having first section and second sections in contact with the first section, and semiconductor device
JP6295797B2 (ja) 炭化珪素半導体装置およびその製造方法
US20190214271A1 (en) Semiconductor device
JP6500912B2 (ja) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
US9741805B2 (en) Semiconductor device and method for manufacturing the semiconductor device
US10692979B2 (en) Method of manufacturing semiconductor device
US11876062B2 (en) Semiconductor device
CN111180514B (zh) 半导体装置
US20230317649A1 (en) Semiconductor device and semiconductor module
US9721915B2 (en) Semiconductor device
US20240096990A1 (en) Semiconductor device and method of manufacturing semiconductor device
US11967568B2 (en) Semiconductor device
US20230122575A1 (en) Semiconductor device and method for manufacturing semiconductor device
US20220181279A1 (en) Semiconductor device
JP2023139634A (ja) 半導体素子

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant