CN106688104B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN106688104B
CN106688104B CN201680002943.5A CN201680002943A CN106688104B CN 106688104 B CN106688104 B CN 106688104B CN 201680002943 A CN201680002943 A CN 201680002943A CN 106688104 B CN106688104 B CN 106688104B
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semiconductor substrate
semiconductor device
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protective film
insulating film
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原田祐一
星保幸
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Fuji Electric Co Ltd
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Abstract

若氢侵入半导体装置，则栅极结构的栅极电压阈值(Vth)会变化。本发明防止氢从位于半导体装置的端部的耐压结构部向半导体装置侵入。提供半导体装置，该半导体装置具备半导体基板，其具有有源区域和设置在所述有源区域的周围的耐压结构部；第1下部绝缘膜，其在所述半导体基板上设置于所述耐压结构部；以及第1保护膜，其设置在所述第1下部绝缘膜上，并且与所述半导体基板电绝缘，且对氢进行吸留。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
以往，为了防止由源电极中的铝(Al)引起的、层间绝缘膜的腐蚀以及由多晶硅形成的栅电极和源电极之间的短路，设置阻障金属层。另外，为了改善电接触，在具有Al的阳电极及阴电极与多晶硅层之间设置阻障金属层(例如，参照专利文献1)。
专利文献
专利文献1：日本特开2012-129503号公报
非专利文献
非专利文献1：ケイ·シェナイ(K.Shenai)，外2名，オプティマムセミコンダクターズフォーハイパワーエレクトロニクス(Optimum Semiconductors for High-PowerElectronics)，アイ·トリプル·イートランザクションズオンエレクトロンデバイシズ(IEEETransactions on Electron Devices)，1989年9月，第36卷，第9号，p.1811-1823
非专利文献2：ビー·ジャヤン·バリガ(B.Jayant Baliga)著，シリコンカーバイドパワーデバイシズ(Silicon Carbide Power Devices)，(美国)，ワールドサイエンティフィックパブリッシングカンパニー(World Scientific Publishing Co.)，2006年3月30日，p.61
发明内容
半导体装置的表面附着水分时，有时来自于水分的氢会进入到半导体装置的内部。另外，在使用铝作为源电极的情况下，有时铝中所含有的氢会进入到半导体装置内。氢具有还原作用，因此有时会由氢吸取半导体装置内的氧，而改变作为栅绝缘膜使用的二氧化硅等的绝缘膜的性质。由此改变栅极结构的栅极电压阈值(Vth)。氢向半导体装置的侵入在位于半导体装置的端部的耐压结构部中也成为问题。
在本发明的第1方式中，提供具备半导体基板、第1下部绝缘膜和第1保护膜的半导体装置。半导体基板可以具有有源区域和耐压结构部。耐压结构部可以设置在有源区域的周围。第1下部绝缘膜可以在半导体基板上设置于耐压结构部。第1保护膜可以设置在第1下部绝缘膜上。第1保护膜可以与半导体基板电绝缘。第1保护膜可以对氢进行吸留。
半导体基板可以具有第1导电型。半导体基板可以在耐压结构部的正面具有第2导电型的区域。第1保护膜可以至少覆盖第2导电型的区域的上方。
第2导电型的区域可以具有在从有源区域朝向耐压结构部的方向上浓度变低的区域。
设置于耐压结构部的第1保护膜可以与有源区域电隔离。
半导体装置在设置于耐压结构部的第1保护膜上还具备第1上部绝缘膜。
第1保护膜可以在耐压结构部中一体地形成。
半导体基板在耐压结构部中还可以具备具有倾斜部和平坦部的高低差部。第1保护膜可以设置为在耐压结构部中覆盖包括高低差部在内的半导体基板的整个上方。
半导体装置还可以具备栅流道部和栅焊盘部。栅流道部可以设置在有源区域与耐压结构部之间。栅焊盘部可以设置在有源区域与栅流道部之间。栅流道部以及栅焊盘部可以具有第2下部绝缘膜和第2保护膜。第2下部绝缘膜可以设置在半导体基板上。第2保护膜可以设置在第2下部绝缘膜上。第2保护膜可以对氢进行吸留。
有源区域还可以具备第3下部绝缘膜与第3保护膜。第3下部绝缘膜可以设置在半导体基板上。第3保护膜可以设置在第3下部绝缘膜上。第3保护膜可以对氢进行吸留。
有源区域还可以具备接触部。接触部可以提供半导体基板与第3保护膜的电连接。第3保护膜可以设置在半导体基板上。在接触部中，半导体基板可以至少具有硅化镍区域。在接触部中，第3保护膜可以至少具有碳化钛区域。
耐压结构部中的第1保护膜的厚度可以大于有源区域中的第3保护膜的厚度。
有源区域中的第3保护膜的厚度可以大于耐压结构部中的第1保护膜的厚度。
应予说明，上述的发明内容未列举出本发明的全部必要的特征。另外，这些特征组的子组合也可以构成发明。
附图说明
图1是表示半导体装置100的俯视图的图。
图2是表示图1中的A-A截面的图。
图3是表示图1中的B-B截面的图。
图4是表示图1中的C-C截面的图。
图5是表示相对于栅极偏压施加时间的栅极阈值(Vth)变化量的图。
图6A是表示形成漂移层12和多个p型区域的工序的图。
图6B是表示形成源极区26和接触区28的工序的图。
图6C是表示形成绝缘膜51的工序的图。
图6D是表示形成栅绝缘膜32、栅电极34、层间绝缘膜36和层间绝缘膜52的阶段的图。
图6E是表示形成钛膜42和金属层44的阶段的图。
图6F是表示形成钝化膜54和漏电极62的阶段的图。
符号说明
10：半导体基板，11：第1导电型层，12：漂移层，14：正面，16：背面，22：阱区，24：基区，26：源极区，28：接触区，29：硅化镍区域，30：接触部，32：栅绝缘膜，34：栅电极，36：层间绝缘膜，37：JTE高浓度区域，38：JTE低浓度区域，39：第2导电型的区域，42：钛膜，43：碳化钛区域，44：金属层，45：高低差部，46：平坦部，47：倾斜部，51：绝缘膜，52：层间绝缘膜，54：钝化膜，62：漏电极，100：半导体装置，101：有源区域，102：耐压结构部，103：栅流道部，105：栅焊盘部
具体实施方式
以下，参照本发明的实施方式对本发明进行说明，以下的实施方式并非用于限定本发明的保护范围。另外，在实施方式中说明的特征的组合的所有方式并不一定是本发明的技术方案所必需的。
在本说明书中，n或p分别意味着电子或者空穴为多数载流子的情况。另外，对于n或p所带的+或－而言，+意味着与未记载有+的情况相比杂质浓度高，－意味着与未记载有－的情况相比杂质浓度低。另外，在记载于本说明书的例子中，第1导电型指n型并且第2导电型指p型，但在其它例子中，也可以是第1导电型指p型并且第2导电型指n型。
图1是表示半导体装置100的俯视图的图。也就是说，图1是表示俯视半导体基板10的情况的图。半导体装置100具有与x-y平面平行的面。x方向与y方向为相互垂直的方向，z方向为与x-y平面垂直的方向。在本说明书中，正面侧是指具有与x-y平面平行的面的物体的+z方向一侧，背面侧是指该物体的-z方向一侧。位于物体的正面侧与背面侧之间的面称为该物体的侧面。应予说明，将半导体基板10的正面记为正面14，将半导体基板10的背面记为背面16。
半导体装置100具有半导体基板10。在半导体基板10设有有源区域101和耐压结构部102。耐压结构部102设置在有源区域101的周围。应予说明，在半导体装置100中，a设置在b的周围是指，在对半导体装置100进行图1的俯视的情况下，以包围b的周围的方式设置有a。
本例的有源区域101是具有纵型MOSFET(Metal Oxide Semiconductor FieldEffect Transistor，金属氧化物半导体场效应晶体管)的区域。但是，在其它的例子中，有源区域101也可以具有IGBT(Insulated Gate Bipolar Transisor，绝缘栅双极型晶体管)来代替纵型MOSFET。
耐压结构部102是具有使半导体基板10的端部的电场集中缓和或者分散的功能的部分。半导体基板10在耐压结构部102中具有后述的JTE(Junction TerminationExtension，结终端扩展)结构。JTE结构具有设置在有源区域101的周围的后述的JTE高浓度区域37和JTE低浓度区域38。
半导体装置100还具备栅流道部(gate runner)103和栅焊盘部105。在对半导体装置100进行俯视的情况下，栅流道部103设置在有源区域101与耐压结构部102之间。栅流道部103设置在有源区域101的周围。栅流道部103是与后述的栅电极34电连接的布线。
在对半导体装置100俯视的情况下，栅焊盘部105设置在有源区域101和栅流道部103之间。栅焊盘部105设置为与栅流道部103电连接。栅焊盘部105是从栅流道部103向有源区域101突出的部分。栅焊盘部105提供连接到外部布线的电连接。例如，在栅焊盘部105，利用引线键合连接栅极端子布线。
图2是表示图1中的A-A截面的图。图2是表示有源区域101的截面的图。本例的半导体基板10具有碳化硅(SiC)。但是，半导体基板10也可以是其他的宽带隙半导体材料。例如在另一例子中，半导体基板10具有氮化镓(GaN)。
半导体基板10具有第1导电型。半导体基板10在背面16侧具有n+型的第1导电型层11，在正面14侧具有n型的漂移层12。半导体基板10在漂移层12的正面14侧具有p型的阱区22、p型的基区24、n+型的源极区26和p+型的接触区28。
基区24的至少一部分设置在栅电极34的下方。在本说明书中，“上”或者“上方”是指从半导体基板10的背面16朝向正面14的方向。与此相对地，“下”或者“下方”是指从半导体基板10的正面14朝向背面16的方向。基区24作为沟道形成区域发挥功能。若隔着栅绝缘膜32从栅电极34施加电场，则在基区24的一部分形成沟道。
n+型的源极区26以被基区24夹着或者包围的方式设置在基区24中。p+型的接触区28以被源极区26夹着或者包围的方式设置在基区24中。p+型的接触区28具有使与源电极的接触电阻降低的功能。
栅绝缘膜32至少使基区24和栅电极34电隔离。本例的栅绝缘膜32设置为在正面14与基区24和源极区26相接。
栅电极34设置在栅绝缘膜32上。作为第3下部绝缘层的层间绝缘膜36位于栅电极34上。层间绝缘膜36以包围栅电极34的正面侧和侧面的方式设置。层间绝缘膜36可以是PSG(Phosphosilicate Glass，磷硅酸盐玻璃)膜或者BPSG(Borophosphosilicate Glass，硼磷硅酸盐玻璃)膜。
在层间绝缘膜36上设有作为第3保护膜的钛(Ti)膜42。钛膜42具有吸留氢的功能。钛膜42也可以含有硅化钛(TiSix)。
金属层44设置在钛膜42上。金属层44可以是铝(Al)，也可以是以重量比1％含有硅(Si)的铝硅化物(AlSi)等铝合金。钛膜42以及金属层44在有源区域101作为源电极发挥功能。应予说明，在半导体基板10的背面16下设置有漏电极62。
接触部30是使钛膜42与源极区26及接触区28接触的区域。接触部30提供半导体基板10与钛膜42的电连接。在接触部30，源极区26的一部分与接触区28具有硅化镍(NiSi)区域29。另外，在接触部30，钛膜42至少具有碳化钛(TiC)区域43。
图3是表示图1中的B-B截面的图。图3是表示横跨有源区域101的端部、栅流道部103以及耐压结构部102的截面的图。在半导体基板10上，绝缘膜51以及层间绝缘膜52的层叠体从有源区域101的外周端部起设置到耐压结构部102的外周端部为止。绝缘膜51可以是氧化硅(SiO2)等的氧化膜、PSG或者BPSG。层间绝缘膜52可以是与层间绝缘膜36相同的材料。层间绝缘膜52可以是PSG或BPSG。
栅流道部103具有作为第2下部绝缘膜的层间绝缘膜52、作为第2保护膜的钛膜42、和金属层44。钛膜42设置在层间绝缘膜52上。钛膜42吸留氢。在本例中，除了有源区域101以外，在栅流道部103中也能够防止活性氢向半导体基板10侵入。
耐压结构部102至少具有作为第1下部绝缘膜的层间绝缘膜52和作为第1保护膜的钛膜42。应予说明，由上述的记载可知，本例的第1保护膜～第3保护膜为钛膜42。耐压结构部102的钛膜42由于设置在层间绝缘膜52上，因此与半导体基板10电绝缘。
在本例中，将吸留氢的钛膜42也设置在耐压结构部102。由此，能够防止活性氢从耐压结构部102侵入到半导体基板10。因此，能够防止有源区域101的栅极阈值变动。
在耐压结构部102的钛膜42上设置作为第1上部绝缘膜的钝化膜54。钝化膜54在有源区域101、耐压结构部102以及栅流道部103设置在最上方。应予说明，在有源区域101以及栅焊盘部105为了确保与外部的电导通，钝化膜54被部分地除去。
耐压结构部102的钛膜42具有悬浮电位。设置在耐压结构部102的钛膜42与有源区域101电隔离。同样地，耐压结构部102的钛膜42也与栅流道部103电隔离。位于耐压结构部102的钛膜42与位于栅流道部103的钛膜42之间的间隔距离可以是2μm以上10μm以下。应予说明，位于有源区域101的钛膜42与位于栅流道部103之间的间隔距离也可以是2μm以上10μm以下。
半导体基板10在耐压结构部102具有高低差部45。高低差部45具有z方向的高度位置不同的2个平坦部46、和位于2个平坦部46之间的倾斜部47。在2个平坦部46中位于下方的平坦部46设有第2导电型的区域39。钛膜42具有悬浮电位，因此在第2导电型的区域39不施加电压。因此，耐压结构部102可以不是作为场板结构而是作为JTE结构而发挥功能。由此，可以防止绝缘膜51以及层间绝缘膜52被绝缘破坏。
半导体基板10在耐压结构部102的正面14具有作为第2导电型的区域39的JTE高浓度区域37和JTE低浓度区域38。JTE低浓度区域38具有比JTE高浓度区域37低的p型的杂质浓度。本例的JTE高浓度区域37具有p型杂质，JTE低浓度区域38具有p－型杂质。也就是说，第2导电型的区域39是在从有源区域101朝向耐压结构部102的方向上p型杂质的浓度变低的区域。
钛膜42在耐压结构部102中一体地形成。应予说明，所谓钛膜42一体地形成，意味着钛膜42为整面膜。例如，意味着在耐压结构部102中的钛膜42不形成孔和开口等。
钛膜42在耐压结构部102中至少覆盖第2导电型的区域39的上方。本例的钛膜42设置为在耐压结构部102中覆盖包括高低差部45在内的半导体基板10的整个上方。即，钛膜42可以设置为覆盖耐压结构部102的整个上方。由此，可以防止氢向JTE高浓度区域37以及JTE低浓度区域38侵入，因此可以防止耐压结构部102中的耐压特性的变动。
图4是表示图1中的C-C截面的图。图4是表示栅焊盘部105的截面的图。在半导体基板10上，绝缘膜51以及层间绝缘膜52的层叠体从栅焊盘部105起设置到有源区域101为止。栅焊盘部105具有作为第2下部绝缘膜的层间绝缘膜52、作为第2保护膜的钛膜42、和金属层44。钛膜42设置在层间绝缘膜52上。钛膜42吸留氢，因此除了有源区域101以外，在栅焊盘部105也可以防止活性氢向半导体基板10侵入。
图5是表示相对于栅极偏压施加时间的栅极阈值(Vth)变化量的图。通过对栅电极34连续地施加栅极偏压，对栅极阈值的变化进行试验并进行测定。横轴是栅极偏压施加时间[hr]，纵轴是栅极阈值(Vth)变化量[V]。
图5中的“比较例”表示只在有源区域101设置有钛膜42的情况的试验结果。与此相对地，图5中的“实施例”表示在有源区域101、耐压结构部102、栅流道部103以及栅焊盘部105设置有钛膜42的情况的试验结果。由图5可知，例如，对于400小时后的栅极阈值变化量而言，比较例是实施例的10倍以上。图5的试验结果示出了在有源区域101以外的位置也设置钛膜42对于抑制栅极阈值变化量是有效的。
从图6A到图6F是表示半导体装置100的制造工序的图。应予说明，在从图6A到图6F中，虽然省略了C-C截面，但在A-A截面、B-B截面以及C-C截面中使用相同的符号表示的层、区域以及膜等以相同的工序制作。例如，有源区域101、耐压结构部102以及栅焊盘部105中的源极区26以及接触区28在图6B的工序中形成。
图6A是表示形成漂移层12和多个p型区域的工序的图。首先，准备具有约2.0E19cm-3的n型杂质浓度的第1导电型层11。应予说明，E意味着10的幂。例如E19意味着10的19次方。本例的第1导电型层11为n+型SiC基板。n+型SiC基板的主面可以是在＜11-20＞方向上具有4度左右的偏角(off angle)的(000-1)面。
接下来，在第1导电型层11的上方，利用外延生长法以约10μm生长具有约1.0E16cm-3的n型杂质浓度的漂移层12。虽然第1导电型层11和漂移层12中的n型杂质为N(氮)，但只要是n型杂质，也可以使用其他的杂质。
接下来，在漂移层12的正面侧，利用外延生长法以约0.5μm生长具有约2.0E16cm-3的p型杂质浓度的阱区22和基区24。本例的p型杂质为Al，但只要是p型杂质，也可以使用其他的杂质。应予说明，在阱区22和基区24以外的区域，利用外延生长法以约0.5μm生长漂移层12。
应予说明，利用蚀刻对漂移层12的端部附近进行局部地去除，形成凹陷。之后，利用外延生长法形成JTE高浓度区域37和JTE低浓度区域38，从而形成第2导电型的区域39。通过调整外延生长法生长时的杂质浓度，可以使JTE高浓度区域37成为p型，JTE低浓度区域38成为p－型。
图6B是表示形成源极区26和接触区28的工序的图。图6B是表示图6A之后的工序的图。在图6B的工序中，利用光刻和离子注入在基区24的正面侧选择性地形成接触区28。接下来，利用光刻和离子注入在基区24的正面侧选择性地形成源极区26。接下来，为了使注入了的杂质活性化，对半导体基板10进行热处理。
图6C是表示形成绝缘膜51的工序的图。图6C是表示图6B之后的工序的图。在图6C的工序中，在半导体基板10上选择性地设置绝缘膜51。绝缘膜51可以设置为具有
Figure BDA0001255998850000081
以上的厚度。
图6D是表示形成栅绝缘膜32、栅电极34、层间绝缘膜36和层间绝缘膜52的阶段的图。图6D是表示图6C之后的工序的图。在图6D的工序中，在氧气和氢气的混合气氛下将半导体基板10曝露在约1000℃的温度并进行热氧化，由此形成栅绝缘膜32。栅绝缘膜32的厚度可以是约100nm。
接下来，在栅绝缘膜32的正面侧形成掺杂了磷的多晶硅。接下来，利用光刻选择性地去除多晶硅，由此形成具有多晶硅的栅电极34。接下来，在栅电极34的正面侧和侧面形成层间绝缘膜36，并且以覆盖包括耐压结构部102的高低差部45在内的半导体基板10的整个上方的方式形成层间绝缘膜52。层间绝缘膜36和层间绝缘膜52为PSG，将膜厚设为约1.0μm的厚度。
接下来，利用光刻对栅绝缘膜32、层间绝缘膜36和层间绝缘膜52进行图案化，形成多个接触部30。接下来，对半导体基板10进行热处理，由此使层间绝缘膜36和层间绝缘膜52回流而平坦化。
图6E表示形成钛膜42和金属层44的阶段的图。图6E是表示图6D之后的工序的图。在图6E的工序中，利用溅射法使钛膜42以
Figure BDA0001255998850000091
(＝100nm＝0.1μm)以上且0.5μm以下的厚度形成。通过形成为0.1μm以上的厚度，可以防止高低差部45中的钛膜42的断裂。
之后，利用光刻对钛膜42进行图案化。应予说明，在形成钛膜42之前，可以将镍(Ni)导入到在接触部30露出的半导体基板10，形成硅化镍区域29。与硅化镍区域29相接的钛膜42可以具有碳化钛区域43。
应予说明，作为变形例，耐压结构部102中的作为第1保护膜的钛膜42的厚度可以大于有源区域101中的作为第3保护膜的钛膜42的厚度。例如，将耐压结构部102的钛膜42的厚度设为大于0.5μm。在对半导体装置100俯视的情况下，耐压结构部102的钛膜42的面积为整体的10％左右。通过增大耐压结构部102的钛膜42的厚度，可以使耐压结构部102中的氢吸留效果变得更加可靠。
另外，代替该变形例，有源区域101中的作为第3保护膜的钛膜42的厚度可以大于耐压结构部102中的作为第1保护膜的钛膜42的厚度。例如，将有源区域101的钛膜42的厚度设为耐压结构部102的钛膜42的厚度的4倍。在有源区域101中含有铝(Al)的金属层44与钛膜42进行反应，因此有时钛膜42的厚度50nm左右会成为钛铝合金(TiAl)。钛铝合金的氢吸留效果比钛小。因此，通过将有源区域101的钛膜42的厚度设为比耐压结构部102的钛膜42厚，可以使有源区域101中的氢吸留效果变得更可靠。
接下来，形成5μm的厚度的金属层44。本例的金属层44为铝硅化物(AlSi)。金属层44在除了耐压结构部102的高低差部45以外的部分，选择性地形成。
图6F是表示形成钝化膜54和漏电极62的阶段的图。图6F是表示图6E之后的工序的图。在图6F的工序中，首先，在半导体基板10的背面侧利用溅射法将镍(Ni)成膜，并在970℃下进行热处理。由此，在背面16形成欧姆接合区域。在该欧姆接合区域的背面侧利用溅射法按照钛(Ti)、镍(Ni)和金(Au)的顺序进行成膜。由此，形成漏电极62。
接下来，在半导体基板10的正面侧的整个面形成钝化膜54。之后，在设置源极端子布线的有源区域101的一部分以及设置栅极端子布线的栅焊盘部105的一部分去除钝化膜54。由此，完成半导体装置100。
以上，使用实施方式对本发明进行了说明，但本发明的技术范围不限于记载于上述实施方式的范围。对于本领域技术人员可以容易地想到对上述实施方式进行各种变更或者改进。从权利要求的记载可以明确，这样的进行了变更或改良的实施方式也包含于本发明的技术范围。
需要注意的是，权利要求书、说明书及附图中所示的装置及方法中的动作、顺序、步骤以及阶段等各处理的执行顺序，只要未特别标注“先于”、“在之前”，或者只要前面的处理的结果不在后面的处理中使用，即可以以任意的顺序实现。关于权利要求书、说明书及附图中的工作流程，方便起见使用“首先”、“接下来”等进行了说明，但并不意味着必须按照该顺序进行实施。

Claims (11)

1.一种半导体装置，其特征在于，具备：
半导体基板，其具有有源区域和设置在所述有源区域的周围的耐压结构部；
第1下部绝缘膜，其在所述半导体基板上设置于所述耐压结构部；以及
第1保护膜，其设置在所述第1下部绝缘膜上，并且与所述半导体基板电绝缘，且对氢进行吸留，
所述半导体装置还具备：
栅流道部，其位于所述有源区域与所述耐压结构部之间；以及
栅焊盘部，其位于所述有源区域与所述栅流道部之间，
所述栅流道部和所述栅焊盘部具有：
第2下部绝缘膜，其位于所述半导体基板上；以及
第2保护膜，其设置在所述第2下部绝缘膜上，且对氢进行吸留。
2.根据权利要求1记载的半导体装置，其特征在于，
所述半导体基板具有第1导电型，
所述半导体基板在所述耐压结构部的正面具有第2导电型的区域，
所述第1保护膜至少覆盖所述第2导电型的区域的上方。
3.根据权利要求2记载的半导体装置，其特征在于，
所述第2导电型的区域具有在从所述有源区域朝向所述耐压结构部的方向上浓度变低的区域。
4.根据权利要求3记载的半导体装置，其特征在于，
设置在所述耐压结构部的所述第1保护膜与所述有源区域电隔离。
5.根据权利要求4记载的半导体装置，其特征在于，
在设置于所述耐压结构部的所述第1保护膜上还具备第1上部绝缘膜。
6.根据权利要求4记载的半导体装置，其特征在于，
所述第1保护膜在所述耐压结构部中一体地形成。
7.根据权利要求6记载的半导体装置，其特征在于，
所述半导体基板在所述耐压结构部中还具备高低差部，该高低差部具有倾斜部和平坦部，
所述第1保护膜设置为在所述耐压结构部中覆盖包括所述高低差部在内的所述半导体基板的整个上方。
8.根据权利要求1或2记载的半导体装置，其特征在于，
所述有源区域还具备：
第3下部绝缘膜，其设置在所述半导体基板上；以及
第3保护膜，其设置在所述第3下部绝缘膜上，且对氢进行吸留。
9.根据权利要求8记载的半导体装置，其特征在于，
所述有源区域还具备接触部，该接触部提供所述半导体基板与设置于所述半导体基板上的所述第3保护膜的电连接，
在所述接触部中，所述半导体基板至少具有硅化镍区域，
在所述接触部中，所述第3保护膜至少具有碳化钛区域。
10.根据权利要求8记载的半导体装置，其特征在于，
所述耐压结构部中的所述第1保护膜的厚度大于所述有源区域中的所述第3保护膜的厚度。
11.根据权利要求8记载的半导体装置，其特征在于，
所述有源区域中的所述第3保护膜的厚度大于所述耐压结构部中的所述第1保护膜的厚度。
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