CN107004653A - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
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- CN107004653A CN107004653A CN201580065241.7A CN201580065241A CN107004653A CN 107004653 A CN107004653 A CN 107004653A CN 201580065241 A CN201580065241 A CN 201580065241A CN 107004653 A CN107004653 A CN 107004653A
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Classifications
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Abstract
本技术涉及一种高导热性半导体装置以及半导体装置的制造方法。半导体装置具备绝缘基板(13)、半导体芯片(11)、板件(3)和冷却器(20)。绝缘基板(13)具备作为绝缘板的绝缘性陶瓷(6)以及设置于绝缘性陶瓷(6)的两面的导板(5)和导板(7)。半导体芯片(11)设置于绝缘基板(13)的上表面。板件(3)接合到绝缘基板(13)的下表面。冷却器(20)接合到板件(3)的下表面。绝缘基板(13)的下表面与板件(3)的接合以及板件(3)的下表面与冷却器(20)的接合中的至少一方是经由以锡为主成分的接合件而进行的。另外,板件(3)的反复应力比这些接合件的拉伸强度小。
Description
技术领域
本技术涉及半导体装置以及半导体装置的制造方法,特别涉及要求散热性的半导体装置以及该半导体装置的制造方法。
背景技术
在使用SiC MOSFET(Silicon-Carbide Metal Oxide Semiconductor-FieldEffect Transistor,碳化硅金属氧化物半导体场效应晶体管)或者Si IGBT(SiliconInsulated Gate Bipolar Transistor,硅绝缘栅双极型晶体管)等功率半导体芯片的半导体装置(功率模块)中,需要使从半导体芯片发出的热高效地散热,将半导体芯片的温度保持于规定温度以下。
以往以来,存在在绝缘基板的一面经由焊料等接合件接合有半导体芯片、在绝缘基板的另一面经由焊料等接合件直接或者间接地接合有冷却器的功率模块,其中,该绝缘基板是氮化硅、氮化铝或者氧化铝等高导热性的绝缘陶瓷板与设置于其两面的由铝或者铜(包括其合金,以下相同)等高导热性金属构成的导板形成一体而成的所谓的绝缘基板。
然而,根据使用条件,有时由于绝缘基板与冷却器之间的热膨张系数的差异,产生热应力,在将绝缘基板与冷却器接合的接合件中产生裂纹,无法在所要求的寿命期间维持足够的散热性能。
因此,为了解决这样的问题,提出了将应力缓和部件配置于绝缘基板与冷却器之间(例如,参照专利文献1)。
关于专利文献1中的应力缓和部件,由形成有多个贯通孔的壁厚0.3mm以上且3mm以下的铝板件构成,各贯通孔成为应力吸收空间。应力缓和部件被钎焊到绝缘基板以及散热器。通过应力吸收空间的作用,应力缓和部件发生变形,由此缓和热应力。
现有技术文献
专利文献1:日本特开2006-294699号公报
发明内容
但是,在专利文献1所示的具备具有应力吸收空间的应力缓和部件的半导体装置中,存在几个问题。
例如,是传热性的问题。应力缓和部件的平均热导率比母材的平均热导率低。这是由于,应力缓和部件的应力吸收空间是空气,其热导率极低。因此,应力缓和部件的平均热导率相对于母材具有的热导率降低了与应力吸收空间的体积比例相当的量。另外,在厚度最好是1mm以上且4mm以下的应力缓和部件中,热流的扩展不佳。这是由于,热的流动受到应力吸收空间阻碍。
本技术用于解决上述问题,涉及高传热性的半导体装置以及半导体装置的制造方法。
本技术的一个方式涉及一种半导体装置,具备:绝缘基板,具备绝缘板以及设置于所述绝缘板的两面的导板;半导体芯片,设置于所述绝缘基板的上表面;板件,接合到所述绝缘基板的下表面;以及冷却器,接合到所述板件的下表面,所述绝缘基板的下表面与所述板件的接合以及所述板件的下表面与所述冷却器的接合中的至少一方是经由以锡为主成分的接合件而进行的,所述板件的反复应力比所述接合件的拉伸强度小。
本技术的一个方式涉及一种半导体装置的制造方法,将具备绝缘板以及设置于所述绝缘板的两面的导板的绝缘基板的上表面与半导体芯片接合,将所述绝缘基板的下表面与板件接合,将所述板件的下表面与冷却器接合,所述绝缘基板的下表面与所述板件的接合以及所述板件的下表面与所述冷却器的接合中的至少一方是经由以锡为主成分的接合件而进行的,所述板件的反复应力比所述接合件的拉伸强度小,经由所述接合件进行接合时的温度比将所述绝缘基板的上表面与所述半导体芯片接合时的温度低。
本技术的一个方式涉及一种半导体装置,具备:绝缘基板,具备绝缘板以及设置于所述绝缘板的两面的导板;半导体芯片,设置于所述绝缘基板的上表面;板件,接合到所述绝缘基板的下表面;以及冷却器,接合到所述板件的下表面,所述绝缘基板的下表面与所述板件的接合以及所述板件的下表面与所述冷却器的接合中的至少一方是经由以锡为主成分的接合件而进行的,所述板件的反复应力比所述接合件的拉伸强度小。
根据这样的结构,由于板件的反复应力比接合件的拉伸强度小,从而能够在维持高的传热性的同时,抑制由于热膨张系数之差产生的热应力所导致的接合件的金属疲劳。
本技术的一个方式涉及一种半导体装置的制造方法,将具备绝缘板以及设置于所述绝缘板的两面的导板的绝缘基板的上表面与半导体芯片接合,将所述绝缘基板的下表面与板件接合,将所述板件的下表面与冷却器接合,所述绝缘基板的下表面与所述板件的接合以及所述板件的下表面与所述冷却器的接合中的至少一方是经由以锡为主成分的接合件而进行的,所述板件的反复应力比所述接合件的拉伸强度小,经由所述接合件进行接合时的温度比将所述绝缘基板的上表面与所述半导体芯片接合时的温度低。
根据这样的结构,由于板件的反复应力比接合件的拉伸强度小,从而能够在维持高的传热性的同时,抑制由于热膨张系数之差产生的热应力所导致的接合件的金属疲劳。
本技术的目的、特征、方面以及优点通过以下的详细说明以及附图将变得更明确。
附图说明
图1是作为实施方式的半导体装置的一个例子的、使用MOSFET的3相逆变器用功率模块的电路图。
图2是由1-in-1的子模块构成实施方式的功率模块的情况下的俯视图。
图3是由1-in-1的子模块构成实施方式的功率模块的情况下的剖视图。
图4是实施方式的子模块的剖视图。
图5是实施方式的子模块的具备框的情况下的剖视图。
图6是实施方式的子模块的具备层叠板件的情况下的剖视图。
图7是示意性地示出实施方式的子模块的温度循环试验后的剖视图(A材料)的图。
图8是示意性地示出实施方式的子模块的温度循环试验后的剖视图(A材料以及层叠板件)的图。
图9是示意性地示出实施方式的子模块的温度循环试验后的剖视图(B材料)的图。
图10是示意性地示出实施方式的子模块的温度循环试验后的剖视图(B材料以及层叠板件)的图。
图11是示意性地示出实施方式的子模块的温度循环试验后的剖视图(C材料)的图。
图12是示意性地示出实施方式的子模块的温度循环试验后的剖视图(C材料以及层叠板件)的图。
图13是例示A材料、B材料以及C材料各自的125℃左右下的变形2%左右的静态以及反复应力的图。
图14是说明实施方式的半导体装置的制造方法(接合工序)的图。
图15是说明实施方式的半导体装置的制造方法(管芯键合工序)的图。
图16是说明实施方式的半导体装置的制造方法(接合工序)的图。
图17是说明实施方式的半导体装置的制造方法(树脂成形工序)的图。
图18是说明实施方式的半导体装置的制造方法(管芯键合工序)的图。
图19是说明实施方式的半导体装置的制造方法(接合工序)的图。
图20是说明实施方式的半导体装置的制造方法(树脂成形工序)的图。
图21是说明实施方式的半导体装置的制造方法(接合工序)的图。
图22是说明实施方式的半导体装置的制造方法(接合工序)的图。
图23是说明实施方式的半导体装置的制造方法(粘接工序)的图。
图24是说明实施方式的半导体装置的制造方法(导线键合工序)的图。
图25是说明实施方式的半导体装置的制造方法(接合工序)的图。
图26是说明实施方式的半导体装置的制造方法(填充工序)的图。
图27是说明实施方式的半导体装置的制造方法(接合工序)的图。
(附图标记说明)
1、2、4、24、44接合件;3板件;5、7导板;6绝缘性陶瓷;8、18密封材料;9a、9b、9c、9d引线框;11半导体芯片;13绝缘基板;19导线;20冷却器;21水套;22冷却器顶板;22a凸片形状;25框;31、32薄板;33层叠板件;45控制端子;51、51a子模块;100焊料裂纹。
具体实施方式
以下,参照附图,说明实施方式。此外,附图是示意性地示出的,不同附图中分别示出的图像的尺寸以及位置的相互关系不一定是准确的记载,能够适当变更。另外,在以下说明中,设为对相同的结构要素附加相同的符号来进行图示,它们的名称以及功能也相同。因此,有时省略关于它们的详细说明。
另外,在以下说明中,有时使用表示“上”、“下”、“侧”、“底”、“表”或者“背”等特定的位置以及方向的用语,但这些用语是为了容易理解实施方式的内容而使用以提供方便的,与实际实施时的方向无关。
<第1实施方式>
<结构>
以下,在不特别指定地记载铜(Cu)或者铝(Al)等元素符号或者材料名称的情况下,还包括包含其他添加物的情况、例如铜合金或者铝合金。
图1是作为本实施方式的半导体装置的一个例子的、使用MOSFET的3相逆变器用功率模块的电路图。另外,图2是由1-in-1的子模块(针对1个子模块,支路是1个)构成本实施方式的功率模块的情况下的俯视图。在这里,如果是图1所例示的情况,则支路是指对应于作为半导体元件的1个MOSFET的单位,但例如在并联连接有多个被用作开关元件的MOSFET的情况下,支路对应于该多个MOSFET。另外,例如如果是IGBT的情况,则对应于将开关元件和二极管合起来的部分。另外,图3是由1-in-1的子模块构成本实施方式的功率模块的情况下的剖视图。另外,图4是子模块的剖视图。
首先,说明本实施方式的功率模块的结构。
如图3或者图4所例示的那样,SiC MOSFET等进行开关动作的半导体芯片11的下表面经由接合件1而与绝缘基板13进行电接合、机械接合以及热接合。另外,半导体芯片11的上表面经由接合件24而与引线框9a接合。
绝缘基板13具备导热性良好且导电性良好的导板5、导热性良好且导电性良好的导板7以及绝缘性陶瓷6。从绝缘基板13的上表面向下表面地,按导板7、绝缘性陶瓷6以及导板5的顺序进行层叠。作为绝缘基板13的上表面的导板7经由接合件1而与半导体芯片11接合。作为绝缘基板13的下表面的导板5经由接合件4、导热性良好且容易变形的铝板件3以及接合件2,与冷却器20进行机械接合以及热接合。接合件4、铝板件3以及接合件2从上方起向下方以该顺序依次层叠。另外,经由接合件44,将引线框9b接合于作为绝缘基板13的上表面的导板7。
另外,在本实施方式的功率模块中,具备覆盖半导体芯片11以及绝缘基板13的密封材料8。
冷却器20具备经由接合件4、铝板件3以及接合件2而与导板5进行机械接合以及热接合的冷却器顶板22以及配置于冷却器顶板22的下方的水套21。在作为冷却器顶板22的下方侧的面的下表面,设置有凸片形状22a。
包括半导体芯片11以及接合到半导体芯片11的绝缘基板13的各子模块51(在图1中,6个)由密封材料8密封。并且,子模块51之间经由引线框9a和引线框9b而电连接。
接下来,关于第1实施方式的结构部件进行叙述。
作为接合件1的材料,例如设想作为由有机保护分子覆盖的被覆银超微粒的纳米Ag(银)粒子的烧结材料。如果是该材料,则与使用焊料的情况相比,导热系数高并且几乎不发生高温劣化。另外,功率循环(power cycle)耐性以及热循环耐性优良,能够在高Tj(高芯片结(chip-junction)温度)下使用。另外,如果是该材料,则适合于与由于半导体芯片硬而容易对接合件造成源于热应力的变形的使用SiC的半导体芯片的组合。
作为接合件2的材料,例如设想以锡为主成分的高强度的Sn-Cu-Sb焊料。在这里,以锡为主成分的接合件是指包括Sn-Cu-Sb的Sn-Cu系焊料、Sn-Sb系焊料、Sn-Ag系焊料、它们的组合、进一步地添加了Ni、In、Ti等的液相线不超过300℃的所谓的Sn系的无铅焊料或锡箔、或者使用在其中混合有少量其他元素的箔或者膏并通过液相扩散进行接合而成的材料。如果是所例示的以锡为主成分的高强度的Sn-Cu-Sb焊料材料,则液相线是240℃左右以上且300℃左右以下,所以充分低于接合件1的烧结后的Ag的熔点。另外,在这里,为了使125℃左右下的拉伸强度为25MPa左右以上,例如最好将锑(Sb)的组成比调整为6重量%左右以上。但是,如果Sb的组成比变大,则固相线与液相线之差变大,变得难以处置。组成比的上限是在液相线为300℃以下时固相线与液相线之差为50℃以下的15重量%以下,最好是12重量%以下。
作为铝板件3的材料,例如设想纯度99.999%以上的超高纯度铝。如果是该材料,则125℃左右下的耐力(拉伸强度)是25MPa左右以下,并且,不会由于125℃左右下的反复硬化而耐力(拉伸强度)超过25MPa左右。即,反复应力不会超过25MPa左右。
作为接合件4的材料,例如设想与接合件2相同的以锡为主成分的高强度的Sn-Cu-Sb焊料或者通过液相扩散接合而得到的Cu-Sn合金。
但是,接合件2以及接合件4中的至少一方包括上述材料即可,不一定是接合件2以及接合件4这两者都包括上述材料。
作为导板5的材料以及导板7的材料,例如设想铜或者铝。作为绝缘性陶瓷6的材料,例如设想Si-N或者Al-N。
作为绝缘基板13,存在一般被称为DBC(Direct Bonded Cu,直接键合铜)基板或者DBA(Direct Bonded Al,直接键合铝)基板的基板。另外,导板5或者导板7也可以是如做成铜与铝的层叠构造的DBAC基板(Cu/Al/Ceramics/Al/Cu)那样的多层绝缘基板。
作为密封材料8的材料,例如设想环氧树脂。在该情况下,设想通过传递成形等形成的传递模塑型的密封材料。
作为引线框的材料,例如设想铜或者CIC(Cu-Invar-Cu)的层叠材料。
半导体芯片11例如是SiC MOSFET或者Si IGBT。虽然未图示,但也能够设想并排设置二极管芯片的情况。
水套21例如通过铝压铸(Die Casting)制造。冷却器顶板22例如是铝合金。水套21与冷却器顶板22通过兼用于密封的焊接等而一体化,构成冷却器20。
作为将半导体芯片11的上表面的上表面电极与引线框9a之间接合的接合件24的材料,例如设想Su-Cu焊料等。同样地,关于接合件44的材料,例如也设想Su-Cu焊料等。但是,也可以不具备接合件44,导板7与引线框9b通过超声波接合等方法直接接合。
上述所示的各材料适合于子模块51是传递模塑型且要求按同一形状大量制造的情况。
另一方面,如图5所例示的那样,也可以是如下构造的子模块51a:在绝缘基板13上粘接框25,通过导线键合(wire-bonding)而形成导线19,之后,使密封材料18流入到框25内。此外,图5是子模块的具备框的情况下的剖视图。
为了使用子模块51a来制造功率模块,如后所述,需要经过与冷却器20的焊料接合工序。因此,对于子模块51a来说,需要能够耐受这样的焊料接合工序的耐热性。
作为密封材料18的材料,例如设想环氧系的灌注树脂或者硅凝胶(siliconegel)。作为框25的材料,例如最好是poly phenylene sulfide(PPS,聚苯硫醚)树脂或者高耐热液晶聚合物等高耐热性的材料。
做成上述构造的子模块51a由于引线框9c以及引线框9d的取出不受传递模塑模具的裂口等的制约,所以布线的自由度高。另外,还能够进行主电路的向上取出,所以适合于高密度安装。
在铝板件3是超高纯度铝的情况下,即在铝板件3是由纯度99.999%以上的铝构成的板件的情况下,根据后述的理由,如图6所例示的那样,例如最好应用层叠板件33。在层叠板件33中,由薄板31和薄板32夹着铝板件3,薄板31和薄板32是如铜、镍、Al-Mg-Si系、Al-Cu系铝合金那样的导电体或者如金刚石那样的绝缘体,即使是薄板也具有机械强度并且是导热性优良的材料。在这里,高强度材料是指杨氏模量是70GPa以上、最好是100GPa以上的材料,导热性优良的材料意味着导热系数是30W/m/k以上、最好是60W/m/k以上的材料。图6是子模块的具备层叠板件的情况下的剖视图。
用于薄板31和薄板32与铝板件3的一体化的接合是通过在进行利用接合件2的接合作业时的温度下对薄板31和薄板32与铝板件3的接合部不造成影响的、即耐热性高的接合方法来进行即可。作为该接合方法的例子,例如存在压焊、轧制、压接或者钎焊等。此外,在接合表面是铝的情况下,为了能够进行焊接,例如最好通过镀镍(Ni)等而对表面进行加工。
图7至图12是示意性地示出如下情况下的温度循环试验后的剖视图的图,即,接合件2以及接合件4是高强度的Sn-Cu-Sb焊料,绝缘基板13是DBC基板,导板5和导板7分别是铜且厚度是0.4mm左右,绝缘性陶瓷6的厚度是0.32mm左右,铝板件3是作为厚度0.5mm左右的超高纯度铝的、纯度不同的A材料、B材料以及C材料(纯度分别是公称6N(99.9999%以上)、公称5N(99.999%以上)以及公称4N(99.99%以上)),冷却器顶板22是厚度4mm左右的铝合金(A6063)。此外,A材料、B材料以及C材料各自的125℃左右下的变形2%左右的静态以及反复应力如图13所例示。
在图7以及图8中,铝板件3是A材料。在图9以及图10中,铝板件3是B材料。在图11以及图12中,铝板件3是C材料。另外,在图7、图9以及图11中,不具备薄板31和薄板32。另一方面,在图8、图10以及图12中,具备薄板31和薄板32。即,应用由薄板31和薄板32夹着铝板件3的层叠板件33。
在上述中的图7、图9以及图11的情况下,即在不具备薄板31和薄板32的情况下,在绝缘基板13的下表面的接合件4中形成焊料裂纹100。裂纹长度在图7的情况下最长,在图11的情况下最短。
在图8的情况下,即在铝板件3是纯度优良的A材料、并且具备薄板31和薄板32的情况下,未形成裂纹。在图10的情况下,即在铝板件3是B材料并且具备薄板31和薄板32的情况下,在绝缘基板13的下表面的接合件4中形成极小的焊料裂纹100,另外,在铝板件3中也形成极小的焊料裂纹100。在图12的情况下,即在铝板件3是C材料并且具备薄板31和薄板32的情况下,在绝缘基板13的下表面的接合件4中形成焊料裂纹100,另外,在铝板件3中也形成焊料裂纹100。根据以上所述可知,根据薄板31和薄板32的有无,铝的纯度与裂纹长度的关系发生变化。具体来说,在不具备薄板31和薄板32的情况下,铝的纯度越高,则裂纹长度越长,但在具备薄板31和薄板32的情况下,铝的纯度越高,则裂纹长度越短。
根据专心研究的结果,超高纯度铝板件被认为在板厚方向上局部地产生大的热应力,并且知道了通过约束其运动才能够在机械特性方面得到预想的结果。
在薄板31和薄板32是铜的情况下,在低于0.1mm的厚度时,难以抑制超高纯度铝的板厚方向的变形。因此,厚度为0.1mm左右是必须的,厚度最好是0.2mm左右以上。
但是,如果厚度超过0.5mm左右,则不只是热阻增加,铜的机械特性的影响也变得显著,即使使用A材料,在接合件4中也形成焊料裂纹100。因此,在薄板31和薄板32是铜的情况下,厚度最好是0.1mm左右以上且0.5mm左右以下。
熔点(固相线温度)比其他结构部件低的焊料在高温时其强度(拉伸强度)急剧降低。直接接合于水冷类型的冷却器的情况下的绝缘基板13的接合部的最高温度大约是125℃左右。在该程度的温度下,接合件2或者接合件4的强度比铝板件3高,从而在使用温度范围下,在接合件2或者接合件4中不发生大的塑性变形,由疲劳破坏导致的裂纹不会扩展,能够保持长期可靠性。
<制造方法>
接下来,说明本实施方式的半导体装置的制造方法。首先,作为第1个制造方法例,关于接合件4是通过液相扩散接合而得到的Cu-Sn合金、且将层叠板件33接合于绝缘基板13的情况下的制造方法,参照图14至图17进行说明。
如图14所例示的那样,在绝缘基板13的下表面与预先一体化而成的层叠板件33之间,夹着厚度是0.02mm左右以上且0.1mm左右以下的Sn箔或者Sn膏。然后,进一步地,通过一边施加1kPa左右以上且100kPa左右以下的压力一边进行加热,使锡(Sn)熔融。然后,通过使该加热维持一定时间,从而使液相扩散推进,形成Cu-Sn合金。通过这样,将绝缘基板13与层叠板件33接合。
为了得到优质的液相扩散层,被接合的板件的平坦度以及平滑度高很重要。因此,将上述绝缘基板13与层叠板件33接合的工序最好是容易将平坦度以及平滑度维持得较高的初始的工序。此外,在图14中,例示出层叠板件33,但也能够作为替代而使用例如对铝板件3进行镀铜而得到的部件。
接下来,如图15所例示的那样,进行将半导体芯片11接合到绝缘基板13的上表面的所谓的管芯键合(die-bonding)工序。关于接合件1,为了避免在后面的工序中进行焊接时熔融,使接合件1的熔点或者固相线温度高于在进行焊接的焊接工序中达到的最高温度。该条件例如能够通过使用纳米Ag的所谓的Ag烧结法、上述液相扩散法或者高熔点焊接(solder)等来实现。其中,最好是由于导热系数高并且不易形成空隙(气泡)而能够稳定地实现低的热阻的Ag烧结法。
接下来,如图16所例示的那样,半导体芯片11的上表面经由接合件24而与引线框9a接合。另外,导板7的上表面经由接合件44而与引线框9b接合。接合件24以及接合件44例如是Su-Cu焊料等。
接下来,如图17所例示的那样,例如通过传递成形或者灌注等对环氧树脂进行成形。由此,半导体芯片11以及绝缘基板13被密封材料8覆盖,完成子模块51。
接下来,实施该子模块51的包括电气特性的检查,仅将优良产品传递给后面的工序。
最后,将多个子模块51经由接合件2接合到冷却器20,进行布线等,并且根据需要对模块整体进行二次密封,制造图2或者图3所例示的功率模块。此外,图3所例示的构造是不使用层叠板件33而使用铝板件3的情况下的功率模块的构造。
关于经过上述工序制造完成的功率模块,在将多个半导体芯片11固定到冷却器20之前,针对每个子模块51检查电气特性等,所以不会由于1个半导体芯片11的不佳状况而需要将功率模块全部丢弃。另外,可加工性也优良。
<第2实施方式>
<制造方法>
接下来,作为第2个制造方法例,关于接合件2是通过液相扩散接合而得到的Cu-Sn合金、并且将层叠板件33接合于冷却器20的情况下的制造方法,参照图18至图22进行说明。
如图18所例示的那样,进行将半导体芯片11接合到绝缘基板13的所谓的管芯键合工序。关于接合件1,为了避免在后面的工序中进行焊接时熔融,使接合件1的熔点或者固相线温度高于在进行焊接的焊接工序中达到的最高温度。该条件例如能够通过使用纳米Ag的所谓的Ag烧结法、上述液相扩散法或者高熔点焊接等来实现。其中,最好是由于导热系数高并且不易形成空隙而能够稳定地实现低的热阻的Ag烧结法。
接下来,如图19所例示的那样,使半导体芯片11的上表面经由接合件24接合到引线框9a。另外,使导板7的上表面经由接合件44接合到引线框9b。接合件24以及接合件44例如是Su-Cu焊料等。
接下来,如图20所例示的那样,例如,通过传递成形或者灌注等对环氧树脂进行成形。由此,半导体芯片11以及绝缘基板13被密封材料8覆盖,完成子模块51。
接下来,实施该子模块51的包括电气特性的检查,仅将优良产品传递给后面的工序。
另行地,如图21所例示的那样,在层叠板件33的下表面与预先一体化而成的冷却器20之间,夹着厚度是0.02mm左右以上且0.1mm左右以下的Sn箔或者Sn膏。然后,进一步地,通过一边施加1kPa左右以上且100kPa左右以下的压力一边进行加热,使锡(Sn)熔融。然后,通过使该加热维持一定时间,使液相扩散推进,形成Cu-Sn合金。通过这样,将冷却器20与层叠板件33接合。在这里,最好对冷却器顶板22的接合面进行镀铜。此外,在图21中虽然示出层叠板件33,但与第1实施方式中的制造方法的情况同样地,例如还能够使用对铝板件3进行镀铜而得到的部件。
最后,如图22所例示的那样,将多个子模块51经由接合件4接合到接合于冷却器20的层叠板件33,进行布线等,并且根据需要对模块整体进行二次密封,制造功率模块。
在该情况下,半导体装置制造的最先的工序为管芯键合工序,所以存在容易将管芯键合时的绝缘基板13的平面度以及平坦度维持得较高、能够更加容易地应用Ag烧结法等这样的效果。
<第3实施方式>
接下来,作为第3个制造方法例,说明接合件4由与接合件2同种材料构成的情况。子模块51的制造方法与第2实施方式所示的制造方法例相同。
在子模块51与冷却器20之间,从上层起依次配设接合件2、层叠板件33以及接合件4,在回流焊炉(reflow furnace)等中同时进行接合。完成的构造与图22所例示的构造相同,但由于接合件2与接合件4由同种材料构成,所以不需要特别区分处理。
在该情况下,与第1实施方式所示的制造方法以及第2实施方式所示的制造方法相比,能够省略接合件4的接合工序,所以能够以低成本制造功率模块。
此外,在本实施方式所示的制造方法例中,代替层叠板件33而使用作为铝板件3的超高纯度铝时,由于在温度循环试验时板厚方向的变形变得极为显著,所以不优选。
<第4实施方式>
接下来,作为图5所例示的构造的子模块51a的制造方法例,关于接合件4是通过液相扩散接合而得到的Cu-Sn合金、并且将层叠板件33接合于绝缘基板13的情况下的制造方法,参照图23至图27进行说明。
直至管芯键合工序之前,与图14以及图15所例示的情况相同。另外,在图23至图27中虽然示出层叠板件33,但还能够使用例如对铝板件3进行镀铜而得到的部件,这与第1实施方式所示的制造方法的情况相同。
接下来,如图23所例示的那样,例如通过硅酮粘接剂等将框25粘接于导板7的电极上。如果粘接于电极上,则即使在由于热循环等而硅酮粘接剂的一部分剥落、框25的粘接面浮起的情况下,在绝缘性方面也不产生问题。框25由高耐热的树脂等构成,通过嵌入或者外嵌(outsert)而设置有控制端子用的电极。
接下来,如图24所例示的那样,作为所谓的导线键合工序,通过铝等导线19连接半导体芯片11的控制端子与框25的控制端子45。
接下来,如图25所例示的那样,将引线框9c经由接合件24接合到半导体芯片11上。另外,将引线框9d经由接合件44接合到导板7上。接合件24以及接合件44例如是Su-Cu焊料等。
接下来,如图26所例示的那样,通过灌注等方法将密封材料18填充到由框25包围的区域。密封材料18是环氧或者硅凝胶等。由此,完成子模块51a。
接下来,实施该子模块51a的包括电气特性的检查,仅将优良产品传递给后面的工序。
最后,将多个子模块51a经由接合件2接合到冷却器20,进行布线等,并且根据需要对模块整体进行二次密封,制造图27所例示的功率模块。
此外,图23、图24以及图25所例示的工序的顺序也可以适当调换。另外,在由于子模块51a的电气特性的检查的原因而不需要密封材料18的情况下,也可以在利用接合件2的接合之后进行密封材料18的填充。
在经过上述工序制造完成的功率模块中,能够从子模块51a进行主电路的向上取出布线(引线框9c以及引线框9d),所以能够避免与邻接的子模块51a的主电路之间的干扰。由此,能够进行高密度安装。
另外,通过该灌注构造,能够应用与第2实施方式所示的制造方法例以及第3实施方式所示的制造方法例相同的制造方法。
此外,在上述制造方法例中,记载了在冷却器20中的水套21和冷却器顶板22通过焊接或者钎焊等方法而预先一体化的情况,但也可以将冷却器20改记为冷却器顶板22,通过接合件2接合的是冷却器顶板22,其后,通过例如FSW(Friction Stir Welding,摩擦搅拌焊接)等方法与水套21进行密封以及一体化。
如上所述,根据上述实施方式,通过使用125℃左右下的反复应力为接合件2的拉伸强度以下的导热性优良的板件,能够不妨碍散热性而缓和由于热膨张系数之差引起的热应力所导致的接合件的金属疲劳。
另外,在将多个半导体芯片固定到冷却器之前,能够针对每个子模块检查电气特性等,所以能够抑制由于1个半导体芯片11的不佳状况而需要将功率模块全部丢弃的情况。因此,能够达到优良的传热性、可靠性以及可加工性。
<效果>
以下,例示上述实施方式的效果。
根据上述实施方式,半导体装置具备绝缘基板13、半导体芯片11、铝板件3和冷却器20。
绝缘基板13具备作为绝缘板的绝缘性陶瓷6以及设置于绝缘性陶瓷6的两面的导板5和导板7。半导体芯片11设置于绝缘基板13的上表面。铝板件3接合到绝缘基板13的下表面。冷却器20接合到铝板件3的下表面。
绝缘基板13的下表面与铝板件3的接合以及铝板件3的下表面与冷却器20的接合中的至少一方是经由以锡为主成分的接合件而进行的。绝缘基板13的下表面与铝板件3的接合是经由接合件4而进行的。铝板件3的下表面与冷却器20的接合是经由接合件2而进行的。另外,铝板件3的反复应力比这些接合件的拉伸强度小。
此外,铝板件3还能够与层叠板件33调换。
根据这样的结构,铝板件3的反复应力比接合件的拉伸强度小,从而能够在维持高的传热性的同时,抑制由于热膨张系数之差产生的热应力所导致的接合件的金属疲劳。具体来说,即使在半导体装置反复经受温度历程(热循环)的情况下,接合件4或者接合件2的塑性变形也小,能够抑制金属疲劳的累积。因此,在接合件中不易产生焊料裂纹100,半导体装置的可靠性提高。
此外,关于这些结构以外的结构,能够适当省略,在适当追加了本说明书所示的任意结构的情况下,也能够产生上述效果。
另外,根据上述实施方式,铝板件3由纯度99.999%以上的铝构成。
根据这样的结构,125℃左右下的耐力(拉伸强度)是25MPa左右以下,并且,不会由于125℃左右下的反复硬化而耐力(拉伸强度)超过25MPa左右。即,反复应力不会超过25MPa左右。
另外,根据上述实施方式,层叠板件33具备由纯度99.999%以上的铝构成的铝板件3以及设置于铝板件3的两面的铜板件31和铜板件32。
根据这样的结构,能够抑制铝板件3的板厚方向上的变形,接合件的热循环耐性提高。
另外,根据上述实施方式,接合件2以及接合件4中的至少一方包括6重量%以上的锑。
根据这样的结构,接合件2以及接合件4中的至少一方的125℃左右下的拉伸强度为25MPa左右以上,所以包括6重量%以上的锑的接合件的拉伸应力比铝板件3的反复应力大,能够在维持高的传热性的同时,抑制由于热膨张系数之差产生的热应力所导致的接合件的金属疲劳。
另外,根据上述实施方式,125℃下的铝板件3的反复应力比125℃下的接合件2以及接合件4中的至少一方的拉伸强度小。
根据这样的结构,即使在被设想为接合部的最高温度的125℃下,铝板件3的反复应力也比125℃下的接合件2以及接合件4中的至少一方的拉伸强度小。
另外,根据上述实施方式,在半导体装置的制造方法中,将具备绝缘性陶瓷6以及设置于绝缘性陶瓷6的两面的导板5和导板7的绝缘基板13的上表面与半导体芯片11接合。然后,将绝缘基板13的下表面与板件3接合。然后,将板件3的下表面与冷却器20接合。
绝缘基板13的下表面与板件3的接合以及板件3的下表面与冷却器20的接合中的至少一方是经由以锡为主成分的接合件而进行的。绝缘基板13的下表面与板件3的接合是经由接合件4而进行的。板件3的下表面与冷却器20的接合是经由接合件2而进行的。然后,板件3的反复应力比接合件的拉伸强度小。另外,经由接合件进行接合时的温度比将绝缘基板13的上表面与半导体芯片11接合时的温度低。
此外,板件3还能够与层叠板件33调换。
根据这样的结构,板件3的反复应力比接合件的拉伸强度小,从而能够在维持高的传热性的同时,抑制由于热膨张系数之差产生的热应力所导致的接合件的金属疲劳。具体来说,即使在半导体装置反复经受温度历程(热循环)的情况下,接合件4或者接合件2的塑性变形也小,能够抑制金属疲劳的累积。因此,在接合件中不易产生焊料裂纹100,半导体装置的可靠性提高。
另外,绝缘基板13的下表面与板件3的接合以及板件3的下表面与冷却器20的接合中的至少一方的接合时的温度比将绝缘基板13的上表面与半导体芯片11接合时的温度低,所以在将绝缘基板13与半导体芯片11接合的状态下,检查各半导体芯片11的电气特性等,其后,能够接合绝缘基板13与板件3、进而接合冷却器20。
一般来说,应力缓和部件与绝缘基板的钎焊由于处理温度的关系,在将半导体芯片搭载于绝缘基板的状态下无法实施,在冷却器、应力缓和部件以及绝缘基板形成一体而成的基板ASSY品(装配件)的状态下,需要进行半导体芯片的管芯键合、进而需要进行导线键合。
然而,例如如果该功率模块用于3相马达的逆变器用途,则具有开关功能的功率半导体芯片至少需要6个,在汽车用途等中,还有时使用几十个。如果在管芯键合工序或者导线键合工序等中哪怕有1个半导体芯片产生不佳状况,则也需要将功率模块全部丢弃,产生的损失变大。
在这点上,根据上述实施方式所示的结构,能够在将多个半导体芯片11接合到冷却器20之前进行各半导体芯片11的电气特性等的检查,所以即使在1个半导体芯片11中产生不佳状况的情况下,也不需要将功率模块全部丢弃,能够抑制损失。
另外,根据上述实施方式,在半导体装置的制造方法中,通过使用纳米Ag的Ag烧结法将绝缘基板13的上表面与半导体芯片11接合。
根据这样的结构,绝缘基板13的上表面与半导体芯片11之间的接合温度高于在后面的焊接工序中达到的最高温度。因此,该接合在后面的焊接工序中不会熔融。另外,由于导热系数高并且不易形成空隙(气泡),所以在绝缘基板13与半导体芯片11之间能够稳定地实现低的热阻。
另外,根据上述实施方式,在半导体装置的制造方法中,在将绝缘基板13的上表面与半导体芯片11接合之前,经由接合件4将绝缘基板13的下表面与层叠板件33接合。
而且,在经由接合件4将绝缘基板13的下表面与层叠板件33接合时,在绝缘基板13的下表面与层叠板件33之间,夹着厚度是0.02mm以上且0.1mm以下的锡箔或者锡膏,进一步地,通过一边施加1kPa以上且100kPa以下的压力一边进行加热,使锡箔或者锡膏熔融,通过液相扩散而形成作为铜-锡合金的接合件4。
根据这样的结构,能够把将绝缘基板13与层叠板件33接合的工序设为容易将平坦度以及平滑度维持得较高的初始的工序,所以能够得到优质的液相扩散层。
另外,根据上述实施方式,在半导体装置的制造方法中,在将绝缘基板13的下表面与层叠板件33接合之前,经由接合件2将层叠板件33的下表面与冷却器20接合。
而且,在经由接合件2接合层叠板件33的下表面与冷却器20时,在层叠板件33的下表面与冷却器20之间,夹着厚度是0.02mm以上且0.1mm以下的锡箔或者锡膏,进一步地,通过一边施加1kPa以上且100kPa以下的压力一边进行加热,使锡箔或者锡膏熔融,通过液相扩散而形成作为铜-锡合金的接合件2。
根据这样的结构,容易将管芯键合时的绝缘基板13的平面度以及平坦度维持得较高,能够更加容易地应用Ag烧结法等。
另外,根据上述实施方式,在半导体装置的制造方法中,通过灌注,形成至少覆盖绝缘基板13以及半导体芯片11的密封材料8。
根据这样的结构,通过密封材料8覆盖绝缘基板13以及半导体芯片11,能够完成功率模块。
<变形例>
在上述实施方式中,有时也记载了各结构要素的材质、材料、尺寸、形状、相对配置关系或者实施的条件等,但这些在所有方面都是示例,不限于本说明书的记载。因此,能够在本技术范围内设想未例示出的无数变形例。例如包括使任意的结构要素变形的情况、追加的情况或者省略的情况,还包括提取至少1个实施方式中的至少1个结构要素来与其他实施方式的结构要素进行组合的情况。
另外,只要不产生矛盾,则在上述实施方式中,被记载为具备“1个”的结构要素也可以具备“1个以上”。进一步地,各结构要素是概念性的单位,包括1个结构要素由多个构造物构成的情况以及1个结构要素对应于某个构造物的一部分的情况,还包括在1个构造物中具备多个结构要素的情况。另外,在各结构要素中,只要发挥相同功能,则包括具有其他构造或者形状的构造物。
另外,本说明书中的说明是出于本技术的所有目的而参照的,均不能认为是现有技术。
Claims (12)
1.一种半导体装置,具备:
绝缘基板(13),具备绝缘板(6)以及设置于所述绝缘板(6)的两面的导板(5、7);
半导体芯片(11),设置于所述绝缘基板(13)的上表面;
板件(3、33),接合到所述绝缘基板(13)的下表面;以及
冷却器(20),接合到所述板件(3、33)的下表面,
所述绝缘基板(13)的下表面与所述板件(3、33)的接合以及所述板件(3、33)的下表面与所述冷却器(20)的接合中的至少一方是经由以锡为主成分的接合件(4、2)而进行的,
所述板件(3、33)的反复应力比所述接合件(4、2)的拉伸强度小。
2.根据权利要求1所述的半导体装置,其特征在于,
所述板件(3、33)由纯度99.999%以上的铝构成。
3.根据权利要求1所述的半导体装置,其特征在于,
所述板件(33)具备由纯度99.999%以上的铝构成的铝板件(3)以及设置于所述铝板件(3)的两面的传导件(31、32)。
4.根据权利要求3所述的半导体装置,其特征在于,
所述传导件(31、32)是铜,设置于所述铝板件(3)的两面的各传导件的厚度是0.1mm以上。
5.根据权利要求3或者4所述的半导体装置,其特征在于,
所述铝板件(3)与所述传导件(31、32)的接合是通过压焊、轧制、压接或者钎焊而进行的。
6.根据权利要求1至5中的任一项所述的半导体装置,其特征在于,
所述接合件(4、2)包括6重量%以上的锑。
7.根据权利要求1至6中的任一项所述的半导体装置,其特征在于,
在125℃下的所述板件(3、33)的所述反复应力比在125℃下的所述接合件(4、2)的所述拉伸强度小。
8.一种半导体装置的制造方法,其中,
将具备绝缘板(6)以及设置于所述绝缘板(6)的两面的导板(5、7)的绝缘基板(13)的上表面与半导体芯片(11)接合,
将所述绝缘基板(13)的下表面与板件(3、33)接合,
将所述板件(3、33)的下表面与冷却器(20)接合,
所述绝缘基板(13)的下表面与所述板件(3、33)的接合以及所述板件(3、33)的下表面与所述冷却器(20)的接合中的至少一方是经由以锡为主成分的接合件(4、2)而进行的,
所述板件(3、33)的反复应力比所述接合件(4、2)的拉伸强度小,
经由所述接合件(4、2)进行接合时的温度比将所述绝缘基板(13)的上表面与所述半导体芯片(11)接合时的温度低。
9.根据权利要求8所述的半导体装置的制造方法,其特征在于,
通过使用纳米Ag的Ag烧结法,将所述绝缘基板(13)的上表面与所述半导体芯片(11)接合。
10.根据权利要求8或者9所述的半导体装置的制造方法,其特征在于,
在将所述绝缘基板(13)的上表面与所述半导体芯片(11)接合之前,经由所述接合件(4)将所述绝缘基板(13)的下表面与所述板件(3、33)接合,
在经由所述接合件(4)将所述绝缘基板(13)的下表面与所述板件(3、33)接合时,
在所述绝缘基板(13)的下表面与所述板件(3、33)之间,夹着厚度是0.02mm以上且0.1mm以下的锡箔或者锡膏,进一步地,通过一边施加1kPa以上且100kPa以下的压力一边进行加热,使所述锡箔或者所述锡膏熔融,通过液相扩散而形成铜-锡合金的所述接合件(4)。
11.根据权利要求8或者9所述的半导体装置的制造方法,其特征在于,
在将所述绝缘基板(13)的下表面与所述板件(3、33)接合之前,经由所述接合件(2)将所述板件(3、33)的下表面与所述冷却器(20)接合,
在经由所述接合件(2)将所述板件(3、33)的下表面与所述冷却器(20)接合时,
在所述板件(3、33)的下表面与所述冷却器(20)之间,夹着厚度是0.02mm以上且0.1mm以下的锡箔或者锡膏,进一步地,通过一边施加1kPa以上且100kPa以下的压力一边进行加热,使所述锡箔或者所述锡膏熔融,通过液相扩散而形成铜-锡合金的所述接合件(2)。
12.根据权利要求8至11中的任一项所述的半导体装置的制造方法,其特征在于,
通过灌注,进一步形成至少覆盖所述绝缘基板(13)以及所述半导体芯片(11)的密封材料(8)。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108493122A (zh) * | 2018-03-30 | 2018-09-04 | 深圳赛意法微电子有限公司 | 半导体器件及其封装方法 |
EP3460837A1 (en) * | 2017-09-26 | 2019-03-27 | Infineon Technologies AG | A housing for a power semiconductor module, a power semiconductor module and a method for producing the same |
CN114846598A (zh) * | 2019-12-26 | 2022-08-02 | 三菱电机株式会社 | 功率模块和电力变换装置 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107112318B (zh) * | 2014-12-29 | 2019-06-18 | 三菱电机株式会社 | 功率模块 |
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US20210066157A1 (en) * | 2018-01-18 | 2021-03-04 | Abb Schweiz Ag | Power electronics module and a method of producing a power electronics module |
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US20220181310A1 (en) * | 2019-05-24 | 2022-06-09 | Rohm Co., Ltd. | Semiconductor device |
US11081421B2 (en) * | 2019-12-12 | 2021-08-03 | Amulaire Thermal Technology, Inc. | IGBT module with heat dissipation structure having ceramic layers corresponding in position and in area to chips |
JP7351209B2 (ja) | 2019-12-17 | 2023-09-27 | 富士電機株式会社 | 半導体装置 |
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EP3852138B1 (en) * | 2020-01-20 | 2023-11-08 | Infineon Technologies Austria AG | An electronic module comprising a semiconductor package connected to a fluid heatsink |
JP7487533B2 (ja) | 2020-04-02 | 2024-05-21 | 富士電機株式会社 | 半導体モジュールおよび車両 |
EP4047648A1 (de) * | 2021-02-18 | 2022-08-24 | Siemens Aktiengesellschaft | Leistungsmodul mit einem mittels sintern und löten mit einem substrat verbundenen leistungs-bauelement und entsprechendes herstellungsverfahren |
JP7562012B2 (ja) | 2021-10-25 | 2024-10-04 | 三菱電機株式会社 | 半導体装置、電力変換装置、および半導体装置の製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1418978A (zh) * | 2001-11-14 | 2003-05-21 | 住友金属工业株式会社 | 抗疲劳龟裂扩展性优良的钢材及其制造方法 |
JP2010177414A (ja) * | 2009-01-29 | 2010-08-12 | Sumitomo Light Metal Ind Ltd | 発熱部品冷却装置用アルミニウム・クラッド材 |
JP4917375B2 (ja) * | 2006-07-25 | 2012-04-18 | 株式会社豊田中央研究所 | パワー半導体モジュールの製造方法 |
US20120182692A1 (en) * | 2011-01-13 | 2012-07-19 | Kabushiki Kaisha Toyota Jidoshokki | Double-sided substrate, semiconductor device and method for the same |
US20120267149A1 (en) * | 2011-04-20 | 2012-10-25 | Mitsubishi Materials Corporation | Method of manufacturing power module substrate and power module substrate |
WO2014115677A1 (ja) * | 2013-01-22 | 2014-07-31 | 三菱マテリアル株式会社 | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板、ヒートシンク付パワーモジュール |
CN104247009A (zh) * | 2012-09-19 | 2014-12-24 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4315272A1 (de) | 1993-05-07 | 1994-11-10 | Siemens Ag | Leistungshalbleiterbauelement mit Pufferschicht |
EP0789397B1 (en) | 1996-02-07 | 2004-05-06 | Hitachi, Ltd. | Circuit board and semiconductor device using the circuit board |
DE19647590A1 (de) | 1996-11-18 | 1998-05-20 | Abb Research Ltd | Hochleistungs-Halbleitermodul |
DK1056321T3 (da) * | 1999-05-28 | 2008-03-03 | Denki Kagaku Kogyo Kk | Keramisk substratkredslöb og dets fremstillingsproces |
JP2004031696A (ja) * | 2002-06-26 | 2004-01-29 | Kyocera Corp | 熱電モジュール及びその製造方法 |
JP2004253736A (ja) * | 2003-02-21 | 2004-09-09 | Ngk Insulators Ltd | ヒートスプレッダモジュール |
JP4621531B2 (ja) | 2005-04-06 | 2011-01-26 | 株式会社豊田自動織機 | 放熱装置 |
JP2007081200A (ja) * | 2005-09-15 | 2007-03-29 | Mitsubishi Materials Corp | 冷却シンク部付き絶縁回路基板 |
WO2007032486A1 (ja) * | 2005-09-15 | 2007-03-22 | Mitsubishi Materials Corporation | 絶縁回路基板および冷却シンク部付き絶縁回路基板 |
US7821613B2 (en) * | 2005-12-28 | 2010-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US8164176B2 (en) * | 2006-10-20 | 2012-04-24 | Infineon Technologies Ag | Semiconductor module arrangement |
JP4964009B2 (ja) * | 2007-04-17 | 2012-06-27 | 株式会社豊田中央研究所 | パワー半導体モジュール |
US8211752B2 (en) * | 2007-11-26 | 2012-07-03 | Infineon Technologies Ag | Device and method including a soldering process |
JP2009283741A (ja) * | 2008-05-23 | 2009-12-03 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
SG179071A1 (en) * | 2010-09-09 | 2012-04-27 | Tanaka Electronics Ind | Aluminum ribbon for ultrasonic bonding |
US8587116B2 (en) | 2010-09-30 | 2013-11-19 | Infineon Technologies Ag | Semiconductor module comprising an insert |
US8736052B2 (en) * | 2011-08-22 | 2014-05-27 | Infineon Technologies Ag | Semiconductor device including diffusion soldered layer on sintered silver layer |
EP2793258A4 (en) * | 2011-12-12 | 2015-11-11 | Mitsubishi Materials Corp | POWER MODULE SUBSTRATE, SUBSTRATE FOR A POWER MODULE WITH A COOLING BODY, POWER MODULE, PASTE FOR PRODUCING A RIVER COMPONENT INHIBITING PREVENTION LAYER AND BINDING METHOD FOR A PRODUCT TO BE BINDED |
JP2013229579A (ja) * | 2012-03-30 | 2013-11-07 | Mitsubishi Materials Corp | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板及びパワーモジュール |
JP6189015B2 (ja) | 2012-04-19 | 2017-08-30 | 昭和電工株式会社 | 放熱装置および放熱装置の製造方法 |
JP6621076B2 (ja) * | 2013-03-29 | 2019-12-18 | 三菱マテリアル株式会社 | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板及びパワーモジュール |
TWI572582B (zh) * | 2013-09-30 | 2017-03-01 | 三菱綜合材料股份有限公司 | 銅/陶瓷接合體,銅/陶瓷接合體之製造方法及電力模組用基板 |
US9837363B2 (en) * | 2014-07-04 | 2017-12-05 | Mitsubishi Materials Corporation | Power-module substrate unit and power module |
-
2015
- 2015-09-14 CN CN201580065241.7A patent/CN107004653B/zh active Active
- 2015-09-14 JP JP2016571667A patent/JP6272512B2/ja active Active
- 2015-09-14 DE DE112015006049.9T patent/DE112015006049B4/de active Active
- 2015-09-14 US US15/518,368 patent/US10510640B2/en active Active
- 2015-09-14 WO PCT/JP2015/075944 patent/WO2016121159A1/ja active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1418978A (zh) * | 2001-11-14 | 2003-05-21 | 住友金属工业株式会社 | 抗疲劳龟裂扩展性优良的钢材及其制造方法 |
JP4917375B2 (ja) * | 2006-07-25 | 2012-04-18 | 株式会社豊田中央研究所 | パワー半導体モジュールの製造方法 |
JP2010177414A (ja) * | 2009-01-29 | 2010-08-12 | Sumitomo Light Metal Ind Ltd | 発熱部品冷却装置用アルミニウム・クラッド材 |
US20120182692A1 (en) * | 2011-01-13 | 2012-07-19 | Kabushiki Kaisha Toyota Jidoshokki | Double-sided substrate, semiconductor device and method for the same |
US20120267149A1 (en) * | 2011-04-20 | 2012-10-25 | Mitsubishi Materials Corporation | Method of manufacturing power module substrate and power module substrate |
CN104247009A (zh) * | 2012-09-19 | 2014-12-24 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
WO2014115677A1 (ja) * | 2013-01-22 | 2014-07-31 | 三菱マテリアル株式会社 | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板、ヒートシンク付パワーモジュール |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3460837A1 (en) * | 2017-09-26 | 2019-03-27 | Infineon Technologies AG | A housing for a power semiconductor module, a power semiconductor module and a method for producing the same |
CN108493122A (zh) * | 2018-03-30 | 2018-09-04 | 深圳赛意法微电子有限公司 | 半导体器件及其封装方法 |
CN108493122B (zh) * | 2018-03-30 | 2019-11-29 | 深圳赛意法微电子有限公司 | 半导体器件及其封装方法 |
CN114846598A (zh) * | 2019-12-26 | 2022-08-02 | 三菱电机株式会社 | 功率模块和电力变换装置 |
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