CN106531700A - 一种芯片封装结构及其封装方法 - Google Patents

一种芯片封装结构及其封装方法 Download PDF

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Publication number
CN106531700A
CN106531700A CN201611107747.2A CN201611107747A CN106531700A CN 106531700 A CN106531700 A CN 106531700A CN 201611107747 A CN201611107747 A CN 201611107747A CN 106531700 A CN106531700 A CN 106531700A
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China
Prior art keywords
chip
layer
wafer
silicon substrate
back side
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CN201611107747.2A
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CN106531700B (zh
Inventor
张黎
徐虹
陈栋
陈锦辉
赖志明
陈启才
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Priority to CN201611107747.2A priority Critical patent/CN106531700B/zh
Priority to PCT/CN2016/109499 priority patent/WO2018103117A1/zh
Priority to US16/330,765 priority patent/US10777477B2/en
Priority to EP16923366.5A priority patent/EP3483928B1/en
Publication of CN106531700A publication Critical patent/CN106531700A/zh
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Abstract

本发明涉及一种芯片封装结构及其封装方法，属于半导体封装技术领域。其包括硅基本体和芯片电极，所述硅基本体的正面设置钝化层并开设钝化层开口，所述芯片电极由背面嵌入于硅基本体的正面，所述钝化层开口露出芯片电极的正面，所述钝化层的上表面设置介电层并开设介电层开口，所述芯片电极的正面设置金属凸块结构；所述硅基本体的侧壁和背面设置包封层。本发明提供了一种侧壁绝缘保护、不易漏电或短路、提高可靠性、改善芯片贴装良率的芯片封装结构，本发明的封装方法采用在晶圆背面设置沟槽，将晶圆分割成芯片单体，并实施芯片单体四周和背面保护技术，这种方法避免了晶圆重构，对于较小芯片来说，有效地提高了产能，进一步降低成本。

Description

一种芯片封装结构及其封装方法
技术领域
本发明涉及一种芯片封装结构及其封装方法，属于半导体封装技术领域。
背景技术
随着半导体硅工艺的发展，芯片的尺寸越来越小，芯片尺寸封装是主流，但部分封装结构并不采用BGA阵列结构，而是采用与传统QFN或LGA相类似地平面焊盘结构。由于硅基体本身是半导体材料，其芯片四周的硅基本体1裸露在组装环境中，如图1所示，在贴装回流工艺中，电极区域11容易因为焊锡膏2印刷量过多而导致部分焊锡爬升到硅基本体1的侧壁裸露的硅上面，造成芯片漏电或短路；或者由于芯片间距比较近，加热或回流后，导致芯片的侧壁接触到了其他芯片的金属凸块而导致失效。
发明内容
本发明的目的在于克服上述不足，提供一种侧壁绝缘保护、不易漏电或短路、提高可靠性、改善芯片贴装良率的芯片封装结构及其封装方法。
本发明的目的是这样实现的：
本发明一种芯片封装结构及其封装方法，其包括硅基本体和芯片电极，所述硅基本体的正面设置钝化层并开设钝化层开口，所述芯片电极由背面嵌入于硅基本体的正面，所述钝化层开口露出芯片电极的正面，
所述钝化层的上表面设置介电层并开设介电层开口，所述介电层开口也露出芯片电极的正面；
所述芯片电极的正面设置金属凸块结构，并与芯片电极固连，所述金属凸块结构由下而上依次包括金属种子层、金属柱、焊料层；
所述硅基本体的侧壁与芯片电极所在的水平面的夹角为α，夹角α取值范围为60°≤α≤120°，所述硅基本体的背面设置导电加强层和包封层，所述导电加强层附着于硅基本体的背面，所述包封层包覆导电加强层并覆盖硅基本体的裸露的背面和侧壁，所述包封层为一体结构，其与介电层于两者的交界处密闭连接；
所述芯片封装结构的总厚度H为50~300微米。
进一步地，所述包封层与介电层于两者的交界处设置密闭连接结构，所述密闭连接结构在介电层和\或硅基本体上呈点状、锯齿状、阶梯状。
进一步地，所述导电加强层由上而下依次包括金属种子层、导电金属层。
进一步地，所述导电加强层为高分子导电材料或导电纳米材料。
进一步地，所述导电加强层完全覆盖硅基本体的背面。
进一步地，所述导电加强层部分覆盖硅基本体的背面，其呈复数个同心环状、复数个条形状。
本发明一种芯片封装结构的封装方法，包括步骤：
步骤一，取集成电路晶圆，其表面设有芯片电极及相应的电路布局，覆盖于晶圆上表面的钝化层于芯片电极上方开设钝化层开口并露出芯片电极的正面；
步骤二，利用光刻工艺在晶圆表面设置介电层并开设介电层开口，介电层开口，介电层开口露出芯片电极的正面；
步骤三，利用溅射或化学镀的方法在晶圆表面沉积金属种子层，再依次利用光刻工艺、电镀工艺在芯片电极的正面设置金属柱和金属柱顶端的焊料层，去除剩余的光刻胶，并腐蚀去掉金属柱以外区域的无效的金属种子层，形成金属凸块结构；
步骤四，在晶圆正面临时键合与之大小一致的支撑载体，所述支撑载体是硅基加强板或是玻璃基载体；
步骤五，通过物理研磨或湿法腐蚀的方法将晶圆背面进行减薄工艺，其减薄厚度根据实际情况确定；
步骤六，在减薄的晶圆的背面通过蒸镀或印刷的方法形成导电加强层13，
步骤七，沿划片道方向依次通过光刻、干法或湿法刻蚀以及光刻胶剥离工艺形成沟槽，所述沟槽的底部在垂直方向上的位置低于芯片电极的电路的底部，所述沟槽的槽壁与沟底的夹角范围为β，夹角β的取值范围为60°≤β≤120°；
步骤八，在真空环境下，在形成沟槽的晶圆背面通过注塑包封料或者贴膜工艺贴覆包封膜的方式形成包封层，所述包封层完全包覆硅基本体的侧壁和背面；
步骤九，通过印刷工艺或贴膜工艺在包封层的背面形成背面保护层；
步骤十，去除键合的支撑载体，并对步骤三中的封装结构的上表面进行清洗，并去除残留物，露出晶圆正面及金属凸块结构；
步骤十一，将上述步骤中的封装结构再次沿划片道进行切割，形成复数颗独立的封装单体。
进一步地，步骤七中，所述沟槽在深度方向上贯穿晶圆，将晶圆分割成复数量的硅基本体。
进一步地，步骤七中，在沟槽形成之后还包括步骤：在所述沟槽的沟底和\或槽壁通过激光工艺或刻蚀工艺形成呈点状、锯齿状或阶梯状的密闭连接结构。
本发明的有益效果是：
1）、本发明封装的芯片封装结构侧壁设置绝缘保护，避免了因焊锡爬升到硅基本体的侧壁裸露的硅上面而造成的漏电或短路，提高可靠性，改善了芯片的良率；
2）、本发明实现的芯片封装结构的金属柱高度尺寸进一步减薄，且采用裸露设计，而硅基本体的四周和背面设置的包封层为一体结构，结构简洁，降低了设计难度，节约了制造成本；
3）、本发明采用在晶圆背面设置沟槽，将晶圆分割成芯片单体，并实施芯片单体四周和背面保护技术，这种方法避免了晶圆重构，对于较小芯片来说，有效地提高了产能，进一步降低成本；
4）、本发明采用的临时键合技术，解决了薄片的取放问题，有利于便携式电子设备的集成发展，同时实现了封装结构的小型化、薄型化和轻量化。
附图说明
图1为现有芯片封装结构的剖面示意图；
图2为本发明一种芯片封装结构及其封装方法的流程图；
图3A为本发明一种芯片封装结构的实施例的正面示意图；
图3B为图3A的A-A剖面示意图；
图4A、4B为导电加强层的示意图；
图5A~5L 为图3A的实施例的封装方法流程图；
图中：
晶圆100
硅基本体1
芯片电极11
钝化层12
钝化层开口121
导电加强层13
包封层3
介电层4
介电层开口41
金属凸块结构5
金属种子层51
金属柱53
焊料层55
支撑载体6
临时键合胶61
临时键合膜63
沟槽7
背面保护层8。
具体实施方式
参见图2，本发明一种芯片封装结构及其封装方法的工艺流程如下：
S1：取集成电路晶圆，在晶圆表面设置介电层并开介电层开口；
S2：在介电层开口内设置金属凸块结构；
S3：在晶圆正面键合支撑载体；
S4：减薄晶圆背面
S5：在减薄的晶圆的背面形成导电加强层，再沿划片道设置沟槽；
S6：在设置沟槽的晶圆背面形成包封层；
S7：去除临时键合的支撑载体；
S8：将完成封装工艺的上述结构切割成复数颗背面及四周保护的封装单体。
现在将在下文中参照附图更加充分地描述本发明，在附图中示出了本发明的示例性实施例，从而本公开将本发明的范围充分地传达给本领域的技术人员。然而，本发明可以以许多不同的形式实现，并且不应被解释为限制于这里阐述的实施例。
具体实施例，参见图3A和图3B。
其中，图3A为本发明一种芯片封装结构的实施例的正面示意图、图3B为图3A的实施例的A-A剖面示意图。其硅基本体1的正面设置钝化层12并开设钝化层开口121。芯片电极11至少为两个，其中一个为负极，如图3A所示，并规则排布。芯片电极11由背面嵌入硅基本体1的正面，钝化层开口121露出芯片电极11的正面。
钝化层12的上表面设置介电层4并开设介电层开口41，介电层开口41略小于钝化层开口121，介电层开口41也露出芯片电极11的正面。
在芯片电极11的正面设置金属凸块结构5，该金属凸块结构5由下而上依次包括金属种子层51、金属柱53、焊料层55。其中，金属柱53采用裸露设计，一般地，金属柱53的厚度范围为3~10微米。为了在贴装回流工艺中避免电极区域的爬锡现象，起连接固定作用的金属凸块结构5的高度只需略高于介电层4的高度即可，其中以金属柱53的厚度范围3~5微米为佳。如图3B所示，金属凸块结构5的高度尺寸尽可能地减薄，节约了制造成本，其简洁的封装结构，也降低了工艺难度，提高了封装的可靠性。
硅基本体1的侧壁与芯片电极11所在的水平面的夹角为α，夹角α取值范围为60°≤α≤120°，如图3B所示为α=90°。优选地，当90°＜α≤120°时，硅基本体1呈梯台，以有助于提高封装结构的整体稳定性和电性能的可靠性。硅基本体1的四个侧壁和背面设置包封层3，该包封层3由可以起到防水、防潮、防震、防尘、散热、绝缘等作用的包封料形成的。该包封层3以一体结构为佳。在包封层3与介电层4的交界处，包封层3与介电层4密闭连接。一般地，在包封层3与介电层4于两者的交界处、在包封层3与硅基本体1于两者的交界处设置密闭连接结构，见图3B之I区域，该密闭连接结构呈点状、锯齿状、阶梯状等，以增强交界处的连接强度。
包封层3使硅基本体1的前后左右四个侧壁及背面均得到物理和电气保护，防止芯片的侧壁接触到了其他芯片的金属凸块而导致失效，避免了外界干扰，提高了其可靠性；同时为侧壁提供绝缘保护，使其不易漏电或短路，改善了芯片贴装良率。
为了使封装结构的整体的电场均匀，还可以在硅基本体1的背面设置导电加强层13，该导电加强层13由上而下依次包括金属种子层、导电金属层，金属种子层可以增强导电金属层与硅基本体1的牢固性。当然，导电加强层13也可以使用密度小、易加工、耐腐蚀、可大面积成膜的高分子导电材料或纳米导电材料，其电导率的范围以10-2 S/cm～1S/cm为佳。
另外，导电加强层13可以完全覆盖硅基本体1的背面，使整体的电场充分均匀。导电加强层13也可以部分覆盖硅基本体1的背面，根据实际需要，通过设计，使其呈复数个同心环状、复数个条形状等结构，如图4A和图4B所示，在设计满足需要的同时获得满意的功能，提高可靠性能，同时节约材料成本。
本发明一种芯片封装结构采用先进的圆片级工艺，可以得到整体厚度50～300微米的封装结构，远比传统的封装结构更薄、更轻、更小。
本发明一种芯片封装结构的封装方法，参见图5A至5K，其工艺包括如下步骤：
步骤一，参见图5A，取集成电路晶圆100，其表面设有芯片电极11及相应的电路布局，覆盖于晶圆100上表面的钝化层12于芯片电极11上方开设钝化层开口121并露出芯片电极11的正面。
步骤二，参见图5B，利用光刻工艺在晶圆100表面设置介电层4并开设介电层开口41，介电层开口41也露出芯片电极11的正面。
步骤三，参见图5C，利用溅射或化学镀的方法在晶圆100表面沉积金属种子层51，再依次利用光刻工艺、电镀工艺在芯片电极的正面设置金属柱53和金属柱53顶端的焊料层55，去除剩余的光刻胶，并腐蚀去掉金属柱53以外区域的无效的金属种子层，形成金属凸块结构5。
步骤四，参见图5D，在晶圆100的正面临时键合与之大小一致的支撑载体6，该支撑载体6可以是硅基加强板，如硅片，也可以是玻璃基载体，如玻璃片，通过临时键合胶61将晶圆100的正面与支撑载体6连接，参见图5D，；临时键合也可以采用临时键合膜63，该临时键合膜可以是温敏性的热剥离膜，也可以是UV剥离膜，将金属凸块结构5陷在临时键合膜63中，参见图5E。临时键合有利于薄片工艺的进行，减少了碎片的风险。
步骤五，参见图5F，通过物理研磨或湿法腐蚀的方法将晶圆100的背面进行减薄工艺，其减薄厚度根据实际情况确定。
步骤六，参见图5G，在减薄的晶圆100的背面形成导电加强层13，该导电加强层13可以通过蒸镀的方法先形成金属种子层，再在金属种子层上蒸镀导电金属层，也可以将高分子导电材料或导电纳米材料通过印刷的方法来实现，不管是通过何种方式，导电加强层13都可以完全覆盖硅基本体1的背面或者部分覆盖硅基本体1的背面，使其呈复数个同心环状、复数个条形状，如图4A和图4B所示。
步骤七，参见图5H，沿划片道方向依次通过光刻、干法或湿法刻蚀以及光刻胶剥离工艺形成沟槽7，所述沟槽7的底部在垂直方向上的位置低于芯片电极11的电路的底部，优选地，所述沟槽7在深度方向上贯穿晶圆100，使沟槽7足够深，并将晶圆100分割成复数量的硅基单体1，所述沟槽7的槽壁与沟底的夹角范围为β，夹角β的取值范围为60°≤β≤120°，一般地，沟槽7底部的宽度需小于相邻芯片有效区域的间距，以防止破坏芯片的电路，故沟槽7的槽壁与沟底的夹角β的取值范围为90°≤β≤120°为佳。
步骤八，参见图5I，在真空环境下，将形成沟槽7的晶圆100的背面通过注塑工艺注塑包封料或者贴膜工艺贴覆包封膜的方式形成包封层3，包封层3完全包覆硅基本体1的四个侧壁和背面，形成包封层保护的包封体。
步骤九，参见图5J，通过印刷工艺或贴膜工艺在包封层3的背面形成背面保护层8。
步骤十，参见图5K，去除键合的支撑载体6，并对步骤三中的封装结构的上表面进行清洗以去除残留物，露出金属凸块结构5。
步骤十一，参见图5L，将步骤八中的封装结构再次沿划片道进行切割，形成复数颗独立的封装单体。
在上述工艺过程中，步骤六中通过设置沟槽7将晶圆分割成硅基单体1，这种方法与传统的刀片切割或者激光切割相比产能较高，并且通过蚀刻方式产生的沟槽7形状可控，沟槽7的侧壁可以是垂直的，也可以是倾斜的，沟槽7的宽度也只需通过光刻开口来调控。此外，蚀刻方式将晶圆分割成硅基单体1产生的应力较小，并且产生的沟槽侧壁有一定的粗糙度，可以增加侧壁与包封层3结合力。若采用切割的方式会给较薄的晶圆100带来应力，容易发生隐裂，切割的深度也不好控制，可能切割不足，也可能造成过切，而且对于较小的芯片来说切割整片花费的时间较长，从而降低了生产效率；
步骤七通过注塑包封料或者贴包封膜的方式在一定的压力下形成包封层3，进一步形成包封层保护的包封体。与通过涂保护胶的方式形成保护胶保护的包封体相比，此发明方法工艺更简单，而且覆盖的晶圆表面很平整。涂胶方式容易覆盖不足，也容易造成晶圆表面凹凸不平，若采用大量的胶先涂胶再进行表面抛平的方式来实现，一方面会造成胶材的浪费，另一方面也会使工艺复杂化。另外，本发明方法在沟槽7形成之后还包括步骤：在所述沟槽7的沟底和\或槽壁通过激光工艺或刻蚀工艺形成呈点状、锯齿状或阶梯状的密闭连接结构，以加强包封层3与介电层4、硅基本体1的连接强度。
此外，步骤六和步骤七通过沟槽刻蚀的方式首先将晶圆100分割成复数量的硅基本体1，再通过注塑包封料或者贴包封膜的方式得到四面和背面保护的芯片封装结构，这种方式与现有的侧壁保护技术，如扇出型封装技术相比，不但工艺高效，而且成本明显降低。因为现有的侧壁保护技术，通常需要先进行晶圆重构，再通过芯片包覆来实现芯片侧壁保护。在晶圆重构之前首先需要对晶圆进行减薄及切割处理成单颗，而在完成晶圆重构之后存在一定的芯片偏移，势必会对后续的光刻对位造成困扰，尤其对于对小芯片来说，现有工艺实施侧壁保护需先进行装片，耗时较长，浪费机台产能，而本发明方法通过沟槽刻蚀的方法将其分割成单颗实施侧壁保护，避免了晶圆重构，也不存在芯片偏移这一问题。
本发明一种芯片封装结构及其封装方法不限于上述优选实施例，这种封装的应用也可以扩展到许多不同的领域，如无线、光学等等，但不局限于此，任何本领域技术人员在不脱离本发明的精神和范围内，依据本发明的技术实质对以上实施例所作的任何修改、等同变化及修饰，均落入本发明权利要求所界定的保护范围内。

Claims (9)

1.一种芯片封装结构，其包括硅基本体（1）和芯片电极（11），所述硅基本体（1）的正面设置钝化层（12）并开设钝化层开口（121），所述芯片电极（11）由背面嵌入于硅基本体（1）的正面，所述钝化层开口（121）露出芯片电极（11）的正面，
其特征在于：所述钝化层（12）的上表面设置介电层（4）并开设介电层开口（41），所述介电层开口（41）也露出芯片电极（11）的正面；
所述芯片电极（11）的正面设置金属凸块结构（5），并与芯片电极（11）固连，所述金属凸块结构（5）由下而上依次包括金属种子层（51）、金属柱（53）、焊料层（55）；
所述硅基本体（1）的侧壁与芯片电极（11）所在的水平面的夹角为α，夹角α取值范围为60°≤α≤120°，所述硅基本体（1）的背面设置导电加强层（13）和包封层（3），所述导电加强层（13）附着于硅基本体（1）的背面，所述包封层（3）包覆导电加强层（13）并覆盖硅基本体（1）的裸露的背面和侧壁，所述包封层（3）为一体结构，其与介电层（4）于两者的交界处密闭连接；
所述芯片封装结构的总厚度H为50~300微米。
2.根据权利要求1所述的一种芯片封装结构，其特征在于：所述包封层（3）与介电层（4）于两者的交界处设置密闭连接结构，所述密闭连接结构在介电层（4）和\或硅基本体（1）上呈点状、锯齿状、阶梯状。
3.根据权利要求1所述的一种芯片封装结构，其特征在于：所述导电加强层（13）由上而下依次包括金属种子层、导电金属层。
4.根据权利要求1所述的一种芯片封装结构，其特征在于：所述导电加强层（13）为高分子导电材料或导电纳米材料。
5.根据权利要求1至4中任一项所述的一种芯片封装结构，其特征在于：所述导电加强层（13）完全覆盖硅基本体（1）的背面。
6.根据权利要求1至4中任一项所述的一种芯片封装结构，其特征在于：所述导电加强层（13）部分覆盖硅基本体（1）的背面，其呈复数个同心环状、复数个条形状。
7.一种芯片封装结构的封装方法，包括步骤：
步骤一，取集成电路晶圆（100），其表面设有芯片电极（11）及相应的电路布局，覆盖于晶圆（100）上表面的钝化层（12）于芯片电极（11）上方开设钝化层开口（121）并露出芯片电极（11）的正面；
步骤二，利用光刻工艺在晶圆（100）表面设置介电层（4）并开设介电层开口（41），介电层开口（41）也露出芯片电极（11）的正面；
步骤三，利用溅射或化学镀的方法在晶圆（100表面沉积金属种子层（51），再依次利用光刻工艺、电镀工艺在芯片电极的正面设置金属柱（53）和金属柱（53）顶端的焊料层（55），去除剩余的光刻胶，并腐蚀去掉金属凸块结构（5）以外区域的无效的金属种子层，形成金属凸块结构（5）；
步骤四，在晶圆（100）的正面临时键合与之大小一致的支撑载体（6），所述支撑载体（6）是硅基加强板或是玻璃基载体；
步骤五，通过物理研磨或湿法腐蚀的方法将晶圆（100）的背面进行减薄工艺，其减薄厚度根据实际情况确定；
步骤六，在减薄的晶圆（100）的背面通过蒸镀或印刷的方法形成导电加强层（13）；
步骤七，沿划片道方向依次通过光刻、干法或湿法刻蚀以及光刻胶剥离工艺形成沟槽（7），所述沟槽（7）的底部在垂直方向上的位置低于芯片电极（11）的电路的底部，所述沟槽（7）的槽壁与沟底的夹角范围为β，夹角β的取值范围为60°≤β≤120°；
步骤八，在真空环境下，将形成沟槽（7）的晶圆（100）的背面通过注塑工艺注塑包封料或者贴膜工艺贴覆包封膜的方式形成包封层（3），所述包封层（3）完全包覆硅基本体（1）的侧壁和背面；
步骤九，通过印刷工艺或贴膜工艺在包封层（3）的背面形成背面保护层（8）；
步骤十，去除键合的支撑载体（6），并对步骤三中的封装结构的上表面进行清洗以去除残留物，露出金属凸块结构（5）；
步骤十一，将上述步骤中的封装结构再次沿划片道进行切割，形成复数颗独立的封装单体。
8.根据权利要求7所述的一种芯片封装结构的封装方法，其特征在于：步骤七中，所述沟槽（7）在深度方向上贯穿晶圆（100），将晶圆（100）分割成复数量的硅基本体（1）。
9.根据权利要求7或8所述的一种芯片封装结构的封装方法，其特征在于：步骤七中，在沟槽（7）形成之后还包括步骤：在所述沟槽（7）的沟底和\或槽壁通过激光工艺或刻蚀工艺形成呈点状、锯齿状或阶梯状的密闭连接结构。
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