CN204303814U - 一种不规则芯片封装结构 - Google Patents

一种不规则芯片封装结构 Download PDF

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Publication number
CN204303814U
CN204303814U CN201420780683.2U CN201420780683U CN204303814U CN 204303814 U CN204303814 U CN 204303814U CN 201420780683 U CN201420780683 U CN 201420780683U CN 204303814 U CN204303814 U CN 204303814U
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chip
substrate
packaging material
plastic packaging
irregular
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梁志忠
王孙艳
王亚琴
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Changjiang Electronics Technology Chuzhou Co Ltd
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Changjiang Electronics Technology Chuzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Buffer Packaging (AREA)

Abstract

本实用新型涉及一种不规则芯片封装结构，它包括基板（1）和芯片（2），所述芯片（2）包括一正面、一背面和四侧面，所述芯片（2）四侧面为倾斜面或圆弧面，所述芯片（2）背面通过装片胶（3）粘结到基板（1）上，所述装片胶（3）延伸至芯片（2）侧面，所述芯片（2）正面与基板（1）表面之间通过金属线（4）相连接，所述芯片（2）周围填充有塑封料（5）。本实用新型一种不规则芯片封装结构，芯片侧面切割成与水平面呈夹角，增加了芯片与四周塑封料之间的接触面积，装片胶易于爬上芯片侧面，增强两者的结合强度，受热时可以通过装片胶的缓冲作用缓减芯片与塑封料之间应力拉扯的现象，保护芯片以及周围塑封料不易破裂。

Description

一种不规则芯片封装结构
技术领域
本实用新型涉及一种不规则芯片封装结构，属于半导体封装技术领域。
背景技术
现有的封装芯片都是切割成正规的长方体形状，芯片侧面与水平面垂直，装片后装片胶只能聚集在芯片底部与基板粘结，芯片、基板与塑封料之间的热膨胀系数不一致，受热的时候三者由于热膨胀系数的差异性，在芯片周围会产生应力集中点，芯片与基板之间有装片胶的缓冲，所以应力会缓减，不会影响芯片与基板的结合，但是芯片周围与塑封料的结合处没有缓冲材料，由于应力拉扯的作用芯片周围塑封料会出现破裂的情况。
发明内容
本实用新型的目的在于克服上述不足，提供一种不规则芯片封装结构，其芯片侧面切割成倾斜面，装片时装片胶能爬上芯片侧面，在受热的时候，装片胶在芯片、基板以及塑封料之间作一个缓冲材料，避免出现由于热膨胀系数的差异在芯片四周应力集中的现象，保护芯片以及周围塑封料不破损，提高了生产良率。
本实用新型的目的是这样实现的：一种不规则芯片封装结构，它包括基板和芯片，所述芯片包括一正面、一背面和四侧面，所述芯片四侧面为倾斜面或圆弧面，所述芯片背面通过装片胶粘结到基板上，所述装片胶延伸至芯片侧面，所述芯片正面与基板表面之间通过金属线相连接，所述芯片周围填充有塑封料。
所述芯片侧面形状由不同形状的切割刀通过一次或两次切割形成。
与现有技术相比，本实用新型具有以下有益效果：
本实用新型一种不规则芯片封装结构，芯片侧面切割成与水平面呈夹角，增加了芯片与四周塑封料之间的接触面积，且装片时，由于芯片侧面为斜面，装片胶易于爬上芯片侧面，增强两者的结合强度，受热时可以通过装片胶的缓冲作用缓减芯片与塑封料之间应力拉扯的现象，保护芯片以及周围塑封料不易破裂。
附图说明
图1为本实用新型一种不规则芯片封装结构的示意图。
图2、图3为芯片切割形状的其他两种实施例图。
其中：
基板1
芯片2
装片胶3
金属线4
塑封料5。
具体实施方式
参见图1~图3，本实用新型一种不规则芯片封装结构，它包括基板1和芯片2，所述芯片2包括一正面、一背面和四侧面，所述芯片2四侧面为倾斜面、圆弧面或其他不规则形状，所述芯片2背面通过装片胶3粘结到基板1上，所述装片胶3延伸至芯片2侧面，所述芯片2正面与基板1表面之间通过金属线4相连接，所述芯片2周围填充有塑封料5。
所述芯片2侧面形状由不同形状的切割刀通过一次或两次切割形成。

Claims (2)

1.一种不规则芯片封装结构，其特征在于：它包括基板（1）和芯片（2），所述芯片（2）包括一正面、一背面和四侧面，所述芯片（2）四侧面为倾斜面或圆弧面，所述芯片（2）背面通过装片胶（3）粘结到基板（1）上，所述装片胶（3）延伸至芯片（2）侧面，所述芯片（2）正面与基板（1）表面之间通过金属线（4）相连接，所述芯片（2）周围填充有塑封料（5）。
2.根据权利要求1所述的一种不规则芯片封装结构，其特征在于：所述芯片（2）侧面形状通过一次或两次切割形成。
CN201420780683.2U 2014-12-12 2014-12-12 一种不规则芯片封装结构 Active CN204303814U (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304587A (zh) * 2015-11-20 2016-02-03 江阴长电先进封装有限公司 一种提高芯片可靠性的封装结构及其圆片级制作方法
CN106531700A (zh) * 2016-12-06 2017-03-22 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
CN111564417A (zh) * 2020-05-22 2020-08-21 甬矽电子(宁波)股份有限公司 一种ic封装结构和ic封装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304587A (zh) * 2015-11-20 2016-02-03 江阴长电先进封装有限公司 一种提高芯片可靠性的封装结构及其圆片级制作方法
CN106531700A (zh) * 2016-12-06 2017-03-22 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
CN106531700B (zh) * 2016-12-06 2019-05-28 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
CN111564417A (zh) * 2020-05-22 2020-08-21 甬矽电子(宁波)股份有限公司 一种ic封装结构和ic封装方法

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