CN111564417A - 一种ic封装结构和ic封装方法 - Google Patents

一种ic封装结构和ic封装方法 Download PDF

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CN111564417A
CN111564417A CN202010444402.6A CN202010444402A CN111564417A CN 111564417 A CN111564417 A CN 111564417A CN 202010444402 A CN202010444402 A CN 202010444402A CN 111564417 A CN111564417 A CN 111564417A
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stress
substrate
chip
packaged chip
sheet
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CN111564417B (zh
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王顺波
钟磊
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Forehope Electronic Ningbo Co Ltd
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Priority to US17/223,739 priority patent/US11626335B2/en
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Abstract

本发明的实施例提供了一种IC封装结构和IC封装方法，涉及芯片封装领域，该IC封装结构包括：基板、贴装在基板上的应力缓冲片、贴装在应力缓冲片上的封装芯片、以及包覆在封装芯片外的塑封体，其中，封装芯片与基板电连接，应力缓冲片用于缓冲作用在封装芯片上的应力。相较于现有技术，本发明提供的IC封装结构，将应力缓冲片通过银胶贴装在基板上，封装芯片通过银胶贴装在应力缓冲片上。应力缓冲片具有一定的形变能力，利用应力缓冲片来缓冲作用在封装芯片上的应力，避免将封装芯片直接贴装在基板上，从而避免了由热膨胀系数不匹配导致的应力作用在正装封装芯片上，避免了应力引起封装芯片性能下降。

Description

一种IC封装结构和IC封装方法
技术领域
本发明涉及芯片封装领域，具体而言，涉及一种IC封装结构和IC封装方法。
背景技术
着半导体行业的快速发展，打线BGA产品结构(WBBGA)广泛应用于集成电路封装电子产品中，其拥有高I/O引脚数，封装尺寸小的优势，集成度不断提高的情况下，电子产品向轻、薄、短、小、多功能、高可靠性方向发展WBBGA(wire bonding ball array)技术的应用将会越来越广泛.通常正装芯片采用打线工艺与基板底部线路相连，由于封装体内部芯片材料硅(热膨胀系数为2.5ppm/C)与基板材料(热膨胀系数为12ppm/C)、材料(线材、银胶)，由热膨胀系数不匹配导致的应力作用在正装芯片上，该应力引起产品性能下降，甚至失效。
发明内容
本发明的目的包括，例如，提供了一种IC封装结构和IC封装方法，其能够缓冲应用在芯片上的应力，避免应力引起产品性能下降。
本发明的实施例可以这样实现：
第一方面，本发明实施例提供一种IC封装结构，包括：
基板；
贴装在所述基板上的应力缓冲片；
贴装在所述应力缓冲片上的封装芯片；
包覆在所述封装芯片外的塑封体；
其中，所述封装芯片与所述基板电连接，所述应力缓冲片用于缓冲作用在所述封装芯片上的应力。
在可选的实施方式中，所述应力缓冲片包括基材、嵌设在所述基材中部的网状结构以及嵌设在所述基材两端的弹簧结构，所述网状结构用于缓冲作用在所述封装芯片上的应力，所述弹簧结构用于缓冲所述基板的内部应力。
在可选的实施方式中，所述网状结构采用金属或高分子聚合物制成。
在可选的实施方式中，所述基板上设置有凹槽，所述应力缓冲片贴装在所述凹槽内。
在可选的实施方式中，所述凹槽的深度与所述应力缓冲片的厚度相同，以使所述应力缓冲片与所述凹槽周围的所述基板的表面相平齐。
在可选的实施方式中，所述封装芯片正装在所述应力缓冲片上，且所述封装芯片上设置有于所述基板连接的连接线，以使所述封装芯片与所述基板电连接。
在可选的实施方式中，所述封装芯片上设置有表面保护层，所述表面保护层外包覆有胶层，所述塑封体包覆在所述胶层外，且所述胶层的杨氏模量低于所述表面保护层的杨氏模量。
在可选的实施方式中，所述胶层的杨氏模量低于3400MPa。
第二方面，本发明实施例提供一种IC封装方法，包括以下步骤：
将应力缓冲片贴装在基板上；
将封装芯片贴装在所述应力缓冲片上；
形成包覆在所述封装芯片外的塑封体；
其中，所述封装芯片与所述基板电连接，所述应力缓冲片用于缓冲作用在所述封装芯片上的应力。
在可选的实施方式中，在所述形成包覆在所述封装芯片外的塑封体的步骤之前，还包括：
形成包覆在所述封装芯片外的胶层。
本发明实施例的有益效果包括，例如：
通过在基板上贴装应力缓冲片，并将封装芯片贴装在应力缓冲片上，利用应力缓冲片来缓冲作用在封装芯片上的应力，避免将封装芯片直接贴装在基板上，从而避免了由热膨胀系数不匹配导致的应力作用在正装封装芯片上，避免了应力引起封装芯片性能下降。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本发明第一实施例提供的IC封装结构的示意图；
图2为图1中应力缓冲片的结构示意图；
图3为本发明第二实施例提供的IC封装结构的示意图；
图4为本发明第三实施例提供的IC封装方法的步骤框图；
图5为本发明第四实施例提供的IC封装方法的步骤框图。
图标：100-IC封装结构；110-基板；111-凹槽；130-应力缓冲片；131-基材；133-网状结构；135-弹簧结构；150-封装芯片；151-连接线；170-塑封体；190-胶层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
需要说明的是，在不冲突的情况下，本发明的实施例中的特征可以相互结合。
经发明人调研发现，现有技术中传统的打线BGA产品结构通常是采用正装芯片贴装在基板上，并采用打线工艺与基板底部线路相连，也就是说正装芯片直接贴装在基板上，由于基板材料、芯片内部材料以及贴合材料(银胶)等的热膨胀系数相差较大，会导致热膨胀系数不匹配的问题，导致热应力作用在正装芯片上，影响产品性能。此外，现有的BGA产品通常是将芯片贴装在平面基板上，导致其由于热膨胀系数不匹配产生的热应力较大，影响产品性能。
本发明提供一种新型的IC封装结构，通过额外设置应力缓冲片的方式来对作用在芯片上的应力进行缓冲，防止因热膨胀系数不匹配产生的热应力直接作用在芯片上影响芯片性能。
第一实施例
请参考图1和图2，本实施例提供了一种IC封装结构100，其能够缓冲作用在芯片上的应力，避免热膨胀系数不匹配产生的热应力直接作用在芯片上影响芯片性能。
本实施例提供的IC封装结构100，包括：基板110、贴装在基板110上的应力缓冲片130、贴装在应力缓冲片130上的封装芯片150、以及包覆在封装芯片150外的塑封体170，其中，封装芯片150与基板110电连接，应力缓冲片130用于缓冲作用在封装芯片150上的应力。
在本实施例中，应力缓冲片130通过银胶贴装在基板110上，封装芯片150通过银胶贴装在应力缓冲片130上。应力缓冲片130具有一定的形变能力，利用应力缓冲片130来缓冲作用在封装芯片150上的应力，避免将封装芯片150直接贴装在基板110上，从而避免了由热膨胀系数不匹配导致的应力作用在正装封装芯片150上，避免了应力引起封装芯片150性能下降。
在本实施例中，基板110上设置有凹槽111，应力缓冲片130贴装在凹槽111内。具体地，通过在基板110表面激光开槽，形成预留给应力缓冲片130的凹槽111，凹槽111的形状/尺寸与应力缓冲片130相匹配，使得应力缓冲片130能够配合贴装在凹槽111内，贴装时可在凹槽111内划银胶，再将应力缓冲片130贴装在凹槽111内。
在本实施例中，凹槽111的深度与应力缓冲片130的厚度相同，以使得应力缓冲片130与凹槽111周围的基板110的表面相平齐。具体地，应力缓冲片130的厚度，指的是包含胶层190在内的厚度，即贴胶后应力缓冲片130与基板110的表面相平齐。
应力缓冲片130包括基材131、嵌设在基材131中部的网状结构133以及嵌设在基材131两端的弹簧结构135，网状结构133用于缓冲作用在封装芯片150上的应力，弹簧结构135用于缓冲基板110的内部应力。具体地，封装芯片150尺寸小于应力缓冲片130，并贴装在应力缓冲片130的网状结构133所在区域。
网状结构133以及弹簧结构135相结合可以有效解决封装结构内部X/Y/Z(三维)方向的应力，网状结构133可以有效解决作用在封装芯片150上的应力，应力缓冲弹簧可以在基板110发生弹性形变，从而缓冲应力，原理类似于水泥路开槽，释放应力，吸收热胀冷缩变形，使变形先发生在封装芯片150底部设计的这部分材料处。
在本实施中，网状结构133采用金属或高分子聚合物制成。具体地，基材131材料采用与封装芯片150内部热膨胀系数相近的材料作为堆叠材料，其内部网状结构133起到内部缓冲应力和支撑作用。
需要说明的是，本实施例中应力缓冲片130采用基材131层压制程，先放置一层基材131后，层压一层铜层，再次在其表面层压网状结构133和弹簧图形，利用保护膜保护不需要蚀刻的区域，通过蚀刻方式成型网状结构133和弹簧结构135，然后在其表面层压基材131，完成应力缓冲片130的制作。
在本实施例中，封装芯片150正装在应力缓冲片130上，且封装芯片150上设置有于基板110连接的连接线151，以使封装芯片150与基板110电连接。具体地，应力缓冲片130的尺寸大于封装芯片150的尺寸，使得封装芯片150能够正装在应力缓冲片130之上。封装芯片150通过导热胶或银胶贴装在应力缓冲片130的表面，并通过连接线151与基板110实现电连接。连接线151为常规的金线、银线或铜线等。
本实施例提供的IC封装结构100，利用激光在基板110表面开槽，形成预留给应力缓冲片130的凹槽111。将应力缓冲片130贴装在凹槽111内，其凹槽111高度/尺寸与应力缓冲片130一致，解决应力缓冲片130放置的问题，其中应力缓冲片130采用基材131层压制程，先放置一层基材131后，层压一层铜层再次在其表面层压网状结构133和弹簧图形，利用保护膜保护不需要蚀刻的区域，通过蚀刻方式完成网状结构133和弹簧结构135，再次在其表面层压基材131，完成应力缓冲片130制作，其尺寸需要大于正装的封装芯片150，贴装应力缓冲片130，应力缓冲片130的结构由网状结构133、基材131、弹簧结构135组成，网状结构133以及弹簧结构135相结合可以有效解决封装结构内部X/Y/Z方向的应力，弹簧结构135可以有效缓冲基板110内部应力，网状结构133可以有效解决作用在芯片上的应力，从而避免了热膨胀系数不匹配产生的热应力直接作用在芯片上影响芯片性能。
第二实施例
参考图3，本实施例提供了一种IC封装结构100，其基本结构和原理及产生的技术效果和第一实施例相同，为简要描述，本实施例部分未提及之处，可参考第一实施例中相应内容。
在本实施例中，封装芯片150上设置有表面保护层，表面保护层外包覆有胶层190，塑封体170包覆在胶层190外，且胶层190的杨氏模量低于表面保护层的杨氏模量。具体地，在塑封前，在线弧和封装芯片150上方点胶，且胶水在-65℃到280℃之间的任何温度下，杨氏模量都低于表面保护层的杨氏模量，在胶水固化后形成胶层190，由于胶层190更加柔软，导致其在热应力作用下先变形，有效地保护了线弧和封装芯片150。
在本实施例中，胶层190的杨氏模量低于3400MPa。具体地，封装芯片150内部结构的杨氏模量或达131000MPa，封装芯片150的表面保护层小于10μm，且表面保护层的杨氏模量为3400MPa，故能够保证胶层190的杨氏模量更低，胶层190更柔软，从而有效保护了线弧和封装芯片150。
第三实施例
参考图4，本实施例提供了一种IC封装方法，其适用于如第一实施例提供的IC封装结构100，该方法包括以下步骤：
S1：将应力缓冲片130贴装在基板110上。
具体地，通过在基板110上激光开槽形成凹槽111，凹槽111的尺寸/高度与应力缓冲片130相适配，将应力缓冲片130通过导热胶或银胶贴装在凹槽111内。
其中，应力缓冲片130在封装工艺前已完成制作，具体地，应力缓冲片130采用基材131层压制程，先放置一层基材131后，层压一层铜层，再次在其表面层压网状结构133和弹簧图形，利用保护膜保护不需要蚀刻的区域，通过蚀刻方式成型网状结构133和弹簧结构135，然后在其表面层压基材131，完成应力缓冲片130的制作。
S2：将封装芯片150贴装在应力缓冲片130上。
具体地，通过导热胶或银胶将封装芯片150正装在应力缓冲片130上，通过应力缓冲片130缓冲作用在封装芯片150上的热应力。其中应力缓冲片130的网状结构133用于缓冲作用在封装芯片150上的应力，弹簧结构135用于缓冲基板110的内部应力。
其中，封装芯片150与基板110电连接，应力缓冲片130用于缓冲作用在封装芯片150上的应力。
在封装芯片150贴装完成后，需要对封装芯片150进行打线操作，利用连接线151将封装芯片150与基板110实现电连接。
S3:形成包覆在封装芯片150外的塑封体170。
具体地，利用塑封机形成塑封体170，塑封体170将封装芯片150和线弧均保护起来。在塑封后利用机台将产品切成单颗，最后进行包装出货。
需要说明的是，本实施例中应力缓冲片130并不起到电气连接的作用，其主要起到对作用在封装芯片150上的应力进行缓冲的作用。
本发明提供的IC封装方法，在实际操作时，包括基板110制作-贴装应力缓冲片130-贴封装芯片150-烘烤-打线-包封-切割等步骤，具体包括：
1.基板110制作：提供一基板110，并在基板110上激光开槽，预留凹槽111。
2.贴装应力缓冲片130：将应力缓冲片130通过导热胶/银胶贴装在凹槽111内。
3.贴封装芯片150：将封装芯片150通过导热胶/银胶正装在应力缓冲片130上。
4.烘烤：通过烘烤固化正装的封装芯片150。
5.打线：通过连接线151时薪封装芯片150与基板110的线路相连。
6.包封：利用塑封机通过塑封料将连接好的芯片线路塑封起来，形成塑封体170，起到保护作用。
7.切割：利用机台将产品切成单颗，并进行包装出货。
本发明提供的IC封装方法，利用基板110表面激光完成开槽工序，预留给应力缓冲片130。将应力缓冲片130贴装在凹槽111内，其结构由网状结构133、基材131、弹簧结构135组成，网状结构133以及弹簧结构135相结合可以有效解决封装结构内部X/Y/Z方向的应力，弹簧结构135可以有效缓冲基板110内部应力，网状结构133可以有效解决作用在芯片上的应力，从而避免了热膨胀系数不匹配产生的热应力直接作用在芯片上影响芯片性能。
第四实施例
参考图5，本实施例提供了一种IC封装方法，其适用于第二实施例所提供的IC封装结构100，该方法的基本步骤和原理及产生的技术效果和第三实施例相同，为简要描述，本实施例部分未提及之处，可参考第三实施例中相应内容，该方法包括以下步骤：
S1：将应力缓冲片130贴装在基板110上。
具体地，通过在基板110上激光开槽，形成凹槽111，将应力缓冲片130贴装在凹槽111内。
S2：将封装芯片150贴装在应力缓冲片130上。
具体地，将封装芯片150正装在应力缓冲片130上，使得封装芯片150与基板110之间不直接接触。贴装完成后进行打线，利用连接线151电连接基板110和封装芯片150。
S3：形成包覆在封装芯片150外的胶层190。
具体地，封装芯片150具有一层表面保护层，在打线完成后，在线弧和封装芯片150上方点胶，且胶水在-65℃到280℃之间的任何温度下，杨氏模量都低于表面保护层的杨氏模量，在胶水固化后形成胶层190，由于胶层190更加柔软，导致其在热应力作用下先变形，有效地保护了线弧和封装芯片150。
S4:形成包覆在封装芯片150外的塑封体170。
具体地，利用塑封机形成塑封体170，塑封体170将封装芯片150、线弧以及胶层190均保护起来。在塑封后利用机台将产品切成单颗，最后进行包装出货。
本发明提供的IC封装方法，在实际操作时，包括基板110制作-贴装应力缓冲片130-贴封装芯片150-烘烤-打线-点胶-包封-切割等步骤，具体包括：
1.基板110制作：提供一基板110，并在基板110上激光开槽，预留凹槽111。
2.贴装应力缓冲片130：将应力缓冲片130通过导热胶/银胶贴装在凹槽111内。
3.贴封装芯片150：将封装芯片150通过导热胶/银胶正装在应力缓冲片130上。
4.烘烤：通过烘烤固化正装的封装芯片150。
5.打线：通过连接线151时薪封装芯片150与基板110的线路相连。
6.点胶：在连接线151和封装芯片150上方点胶，固化后形成胶层190。
7.包封：利用塑封机通过塑封料将连接好的芯片线路塑封起来，形成塑封体170，起到保护作用。
8.切割：利用机台将产品切成单颗，并进行包装出货。
本发明提供的IC封装方法，通过额外设置胶层190，由于胶层190更加柔软，导致其在热应力作用下先变形，有效地保护了线弧和封装芯片150。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

1.一种IC封装结构，其特征在于，包括：
基板；
贴装在所述基板上的应力缓冲片；
贴装在所述应力缓冲片上的封装芯片；
包覆在所述封装芯片外的塑封体；
其中，所述封装芯片与所述基板电连接，所述应力缓冲片用于缓冲作用在所述封装芯片上的应力。
2.根据权利要求1所述的IC封装结构，其特征在于，所述应力缓冲片包括基材、嵌设在所述基材中部的网状结构以及嵌设在所述基材两端的弹簧结构，所述网状结构用于缓冲作用在所述封装芯片上的应力，所述弹簧结构用于缓冲所述基板的内部应力。
3.根据权利要求2所述的IC封装结构，其特征在于，所述网状结构采用金属或高分子聚合物制成。
4.根据权利要求1-3任一项所述的IC封装结构，其特征在于，所述基板上设置有凹槽，所述应力缓冲片贴装在所述凹槽内。
5.根据权利要求4所述的IC封装结构，其特征在于，所述凹槽的深度与所述应力缓冲片的厚度相同，以使所述应力缓冲片与所述凹槽周围的所述基板的表面相平齐。
6.根据权利要求1所述的IC封装结构，其特征在于，所述封装芯片正装在所述应力缓冲片上，且所述封装芯片上设置有于所述基板连接的连接线，以使所述封装芯片与所述基板电连接。
7.根据权利要求1所述的IC封装结构，其特征在于，所述封装芯片上设置有表面保护层，所述表面保护层外包覆有胶层，所述塑封体包覆在所述胶层外，且所述胶层的杨氏模量低于所述表面保护层的杨氏模量。
8.根据权利要求7所述的IC封装结构，其特征在于，所述胶层的杨氏模量低于3400MPa。
9.一种IC封装方法，其特征在于，包括以下步骤：
将应力缓冲片贴装在基板上；
将封装芯片贴装在所述应力缓冲片上；
形成包覆在所述封装芯片外的塑封体；
其中，所述封装芯片与所述基板电连接，所述应力缓冲片用于缓冲作用在所述封装芯片上的应力。
10.根据权利要求9所述的IC封装方法，其特征在于，在所述形成包覆在所述封装芯片外的塑封体的步骤之前，还包括：
形成包覆在所述封装芯片外的胶层。
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