CN107221517B - 一种包覆型芯片尺寸封装结构及其封装方法 - Google Patents
一种包覆型芯片尺寸封装结构及其封装方法 Download PDFInfo
- Publication number
- CN107221517B CN107221517B CN201710556249.4A CN201710556249A CN107221517B CN 107221517 B CN107221517 B CN 107221517B CN 201710556249 A CN201710556249 A CN 201710556249A CN 107221517 B CN107221517 B CN 107221517B
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- chip
- silicon substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000002161 passivation Methods 0.000 claims abstract description 29
- 238000001259 photo etching Methods 0.000 claims abstract description 16
- 238000001465 metallisation Methods 0.000 claims abstract description 13
- 235000012431 wafers Nutrition 0.000 claims description 28
- 239000000178 monomer Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000009719 polyimide resin Substances 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000003486 chemical etching Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 238000011946 reduction process Methods 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 2
- 230000035800 maturation Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 14
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明公开了一种包覆型芯片尺寸封装结构及其封装方法,属于半导体封装技术领域。其硅基本体(111)的正面设置钝化层(210),芯片电极(113)由背面嵌入硅基本体(111)的正面,所述钝化层(210)的上表面设置介电层Ⅰ310),所述介电层Ⅰ(310)不覆盖到钝化层(210)的边缘,其上依次覆盖金属种子层Ⅰ(410)、金属层Ⅰ(510)和介电层Ⅱ(320),所述介电层Ⅱ(320)开设介电层Ⅱ开口Ⅰ(321)露出金属层Ⅰ(510)的上表面;所述金属层Ⅰ(510)的上表面设置凸块底部金属Ⅱ,在所述硅基本体(111)的四周和背面设置包封层Ⅱ(123),所述包封层Ⅱ(123)向上延展覆盖钝化层(210)的裸露部分,以实现侧壁绝缘保护、不易漏电或短路、避免芯片偏移带来的光刻偏移。
Description
技术领域
本发明涉及一种包覆型芯片尺寸封装结构及其封装方法,属于半导体封装技术领域。
背景技术
随着无线手持设备、掌上电脑以及其他移动电子设备的增加,消费者对各种小外形、特征丰富产品的需求也与日俱增,微电子封装技术面临着电子产品“高性价比、高可靠性、多功能、小型化及低成本”发展趋势带来的挑战和机遇。圆片级芯片尺寸封装技术满足了电子产品向更加小型、更多功能、更高可靠性对电路组件的要求。然而圆片级芯片尺寸封装也面临着一些问题,随着芯片变的小而薄,而且其侧壁没有保护,在SMT时芯片的取放会造成边角应力,甚至芯片碎裂。
同时,传统的扇出型芯片尺寸封装工艺,将重构后的晶圆再做RDL工艺,往往存在芯片偏移带来的光刻偏移问题。
发明内容
本发明的目的在于克服上述不足,提供一种侧壁绝缘保护、不易漏电或短路、避免芯片偏移带来的光刻偏移的包覆型芯片尺寸封装结构及其封装方法。
本发明的目的是这样实现的:
本发明一种包覆型芯片尺寸封装结构,其包括硅基本体和芯片电极,所述硅基本体的正面设置钝化层并开设钝化层开口,所述芯片电极由背面嵌入硅基本体的正面,所述钝化层开口露出芯片电极的正面。
所述钝化层的上表面设置介电层Ⅰ并开设介电层Ⅰ开口Ⅰ,所述介电层Ⅰ开口Ⅰ露出芯片电极的正面,所述介电层Ⅰ不覆盖到钝化层的边缘,其上依次覆盖金属种子层Ⅰ、金属层Ⅰ和介电层Ⅱ,所述介电层Ⅱ开设介电层Ⅱ开口Ⅰ露出金属层Ⅰ的上表面;
所述金属层Ⅰ的上表面设置凸块底部金属Ⅱ,所述凸块底部金属Ⅱ由下而上依次包括金属种子层Ⅱ、金属层Ⅱ组成,并在金属层Ⅱ上设置焊球;
在所述硅基本体的四周和背面设置包封层Ⅱ,所述包封层Ⅱ向上延展覆盖钝化层的裸露部分,其上表面与介电层Ⅱ的上表面齐平,所述包封层Ⅱ为一体结构。
可选地,所述硅基本体的侧壁设有台阶。
本发明一种包覆型芯片尺寸封装结构的封装方法,其包括如下步骤:
步骤一,取集成电路晶圆,其表面设有芯片电极及相应电路布局,覆盖于晶圆上表面的钝化层于芯片电极上方开设芯片表面钝化层开口露出芯片电极的正面;
步骤二,利用光刻工艺在晶圆表面设置介电层Ⅰ并开设介电层Ⅰ开口Ⅰ和介电层Ⅰ开口Ⅱ,其中,介电层Ⅰ开口Ⅰ露出芯片电极的正面,介电层Ⅰ开口Ⅱ沿划片道设置,并露出钝化层的上表面;
步骤三,利用溅射或化学镀的方法在晶圆表面沉积金属种子层,再利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在芯片电极的上表面设置再布线金属层Ⅰ,并腐蚀去掉无效的金属种子层Ⅰ,形成凸块底部金属Ⅰ,该凸块底部金属Ⅰ由下而上依次包括金属种子层Ⅰ、金属层Ⅰ,并在金属层Ⅰ的最外层设有输入/输出端;
步骤四,再次利用光刻工艺在金属层Ⅰ上覆盖介电层Ⅱ并开设介电层Ⅱ开口Ⅰ和介电层Ⅱ开口Ⅱ,其中,介电层Ⅱ开口Ⅰ露出金属层Ⅰ的输入/输出端,介电层Ⅱ开口Ⅱ再次沿划片道设置,并与介电层Ⅰ开口Ⅱ重合露出钝化层的上表面;
步骤五,再次利用溅射或化学镀的方法在介电层Ⅱ的表面沉积金属种子层Ⅱ,再次利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在金属种子层Ⅱ的上表面设置再布线金属层Ⅱ,并腐蚀去掉无效的金属种子层Ⅱ,形成凸块底部金属Ⅱ,该凸块底部金属Ⅱ由下而上依次包括金属种子层Ⅱ、金属层Ⅱ,并在金属层Ⅱ的最外层设有输入/输出端;
步骤六,通过物理研磨的方法将晶圆背面进行减薄工艺,其减薄厚度根据实际情况确定,并将减薄的晶圆切成单颗,形成芯片单体;
步骤七,取一硅基支撑载体,并在硅基支撑载体本体上黏贴剥离膜,将复数颗步骤六的芯片单体按照一定的排列顺序倒装至硅基支撑载体上,芯片单体通过剥离膜与硅基支撑载体临时键合;
步骤八,在真空环境下,在硅基支撑载体上通过注塑包封料或者贴包封膜的方式形成包封层,包封层完全包覆芯片单体,形成包封层保护的包封体,并将硅基支撑板键合至薄膜包封体的背面;
步骤九,将硅基支撑载体去除,同时去除剥离膜,露出芯片单体上表面的金属层Ⅱ,并对芯片单体的表面进行清洗,去除残留物;
步骤十,通过物理研磨或化学蚀刻的方式去除硅基支撑板;
步骤十一,在金属层Ⅱ的输入/输出端处设置焊球;
步骤十二,将上述通过圆片级工艺完成的包覆型芯片尺寸封装结构进行切割形成侧壁由包封层Ⅱ包覆的芯片单体。
可选地, 所述介电层Ⅰ的材质是低温固化的聚酰亚胺树脂,或者是高温固化的高分子材料。
可选地,所述介电层Ⅱ的材质是低温固化的聚酰亚胺树脂,或者是高温固化的高分子材料。
可选地,所述剥离膜为UV剥离膜或者热剥离膜。
可选地,步骤六中,通过激光切割或者刀片物理切割的方式将减薄的晶圆切成单颗。
本发明的有益效果是:
1、本发明包覆型芯片封装结构侧壁和边角设置保护,加强了芯片拐角处的抗应力破裂强度,避免了芯片切割造成的芯片碎角或者侧壁开裂,同时降低了SMT时芯片取放造成芯片碎角、芯片碎裂等缺陷的发生几率,减少了漏电流的产生,提高了芯片的可靠性能,改善了芯片的良率;
2、本发明包覆型芯片封装结构上表面边缘、四周和下表明设置的包封层为一体结构,与同类产品如扇出型芯片尺寸封装技术封装的结构相比增强了包封层与侧壁的结合力,不容易因受力而脱落;
3、本发明采用成熟的圆片级芯片尺寸封装技术后将晶圆切割成单颗进行侧壁保护,与扇出型芯片尺寸封装技术相比,不存在重构晶圆带来的光刻对位偏移的问题;并且本发明制作晶圆再布线工艺时,不受包封胶的影响,不局限于使用低温固化胶。
附图说明
图1为本发明一种包覆型芯片尺寸封装结构的正面示意图;
图2为本发明一种包覆型芯片尺寸封装结构的实施例的A-A剖面示意图;
图3A-3L为本发明上述实施例的封装方法的工艺流程示意图;
图3M为图2实施例的变形一;
图3N为图2实施例的变形二;
其中:
晶圆100
硅基本体111
芯片电极113
包封层Ⅰ121
包封层Ⅱ123
钝化层210
钝化层开口213
介电层Ⅰ310
介电层Ⅰ开口Ⅰ311
介电层Ⅰ开口Ⅱ312
金属种子层Ⅰ410
金属层Ⅰ510
介电层Ⅱ320
介电层Ⅱ开口Ⅰ321
介电层Ⅱ开口Ⅱ322
金属种子层Ⅱ420
金属层Ⅱ520
焊球600
硅基支撑载体710
剥离膜730
硅基支撑板800。
具体实施方式
下面结合附图对本发明的具体实施方式进行详细说明。
实施例
图1为本发明一种包覆型芯片尺寸封装结构的实施例的正面示意图,图2为其A-A剖面示意图。
本发明一种包覆型芯片尺寸封装结构,其硅基本体111的正面设置钝化层210并开设钝化层开口213,其芯片电极113由背面嵌入硅基本体111的正面,钝化层开口213露出芯片电极113的正面。
钝化层210的上表面设置介电层Ⅰ310并开设介电层Ⅰ开口Ⅰ311,介电层Ⅰ开口Ⅰ311露出芯片电极113的正面,介电层Ⅰ310不覆盖到钝化层210的边缘,其上依次覆盖金属种子层Ⅰ410、金属层Ⅰ510和介电层Ⅱ320,该介电层Ⅱ320开设介电层Ⅱ开口Ⅰ321露出金属层Ⅰ510的上表面。
在金属层Ⅰ510的上表面设置凸块底部金属Ⅱ,该凸块底部金属Ⅱ由下而上依次包括金属种子层Ⅱ420、金属层Ⅱ520,并在金属层Ⅱ520上方设置焊球600。
在硅基本体111的四周和背面设置包封层Ⅱ123,该包封层Ⅱ123向上延展覆盖钝化层210的裸露部分,其上表面与介电层Ⅱ320的上表面齐平,该包封层Ⅱ123为一体结构。该硅基本体111的侧壁是垂直的。该硅基本体111的侧壁也可以设有台阶,以进一步增强包封层Ⅱ123与侧壁的结合力,使其不容易因受力而脱落。
本发明包覆型芯片边角设置了介电层Ⅱ320进行绝缘保护,加强了芯片拐角处的抗应力破裂强度,避免了碎角的风险,也减少了漏电流的产生。而且降低了SMT时芯片取放造成芯片碎角、芯片碎裂等缺陷的发生几率。
上述实施例的包覆型芯片尺寸封装结构的封装方法,包括如下步骤:
步骤一,参见图3A,取集成电路晶圆100,其表面设有芯片电极113及相应电路布局,覆盖于晶圆100上表面的钝化层210于芯片电极113上方开设芯片表面钝化层开口213露出芯片电极113的正面。
步骤二,参见图3B,利用光刻工艺在晶圆100表面设置介电层Ⅰ310并开设介电层Ⅰ开口Ⅰ311和介电层Ⅰ开口Ⅱ312,其中,介电层Ⅰ开口Ⅰ311露出芯片电极113的正面,介电层Ⅰ开口Ⅱ312沿划片道设置,并露出钝化层210的上表面;此处介电层Ⅰ310材质可以是低温固化的聚酰亚胺树脂,也可以是高温固化的高分子材料,可根据产品需求选择。
步骤三,参见图3C,利用溅射或化学镀的方法在晶圆100表面沉积金属种子层,再利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在芯片电极113的上表面设置再布线金属层Ⅰ,并腐蚀去掉无效的金属种子层Ⅰ,形成凸块底部金属Ⅰ,该凸块底部金属Ⅰ由下而上依次包括金属种子层Ⅰ410、金属层Ⅰ510,并在金属层Ⅰ510的最外层设有输入/输出端。
步骤四,参见图3D,再次利用光刻工艺在金属层Ⅰ510上覆盖介电层Ⅱ320并开设介电层Ⅱ开口Ⅰ321和介电层Ⅱ开口Ⅱ322,其中,介电层Ⅱ开口Ⅰ321露出金属层Ⅰ510的输入/输出端,介电层Ⅱ开口Ⅱ322再次沿划片道设置,并与介电层Ⅰ开口Ⅱ312重合露出钝化层210的上表面;此处介电层Ⅱ320材质可以是低温固化的聚酰亚胺树脂,也可以是高温固化的高分子材料,可根据产品需求选择。
步骤五,参见图3E,再次利用溅射或化学镀的方法在介电层Ⅱ320的表面沉积金属种子层Ⅱ,再次利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在金属种子层Ⅱ的上表面设置再布线金属层Ⅱ,并腐蚀去掉无效的金属种子层Ⅱ,形成凸块底部金属Ⅱ,该凸块底部金属Ⅱ由下而上依次包括金属种子层Ⅱ420、金属层Ⅱ520,并在金属层Ⅱ520的最外层设有输入/输出端。
步骤六,参见图3F,通过物理研磨的方法将晶圆100背面进行减薄工艺,其减薄厚度根据实际情况确定,并将减薄的晶圆100切成单颗,形成芯片单体;将减薄的晶圆100切成单颗的方式可以是用激光切割或者刀片物理切割。
步骤七,参见图3G,取一硅基支撑载体710,并在硅基支撑载体710本体上黏贴剥离膜730,将复数颗步骤六的芯片单体按照一定的排列顺序倒装至硅基支撑载体710上,芯片单体通过剥离膜730与硅基支撑载体710临时键合;所用的剥离膜730为临时键合膜,如UV剥离膜或者热剥离膜。
步骤八,参见图3H,在真空环境下,在硅基支撑载体710上通过注塑包封料或者贴包封膜的方式形成包封层120,包封层120完全包覆芯片单体,形成包封层120保护的包封体,并将硅基支撑板800键合至薄膜包封体的背面。
步骤九,参见图3I,将硅基支撑载体710去除,同时去除剥离膜730,露出芯片单体上表面的金属层Ⅱ520,并对芯片单体的表面进行清洗,去除残留物。
步骤十,参见图3J,通过物理研磨或化学蚀刻的方式去除硅基支撑板800。
步骤十一,参见图3K,在金属层Ⅱ520的输入/输出端处形成连接件,图中以焊球600示意。
步骤十二,参见图3L,将上述通过圆片级工艺完成的包覆型芯片尺寸封装结构进行切割形成侧壁由包封层120包覆的芯片单体。
以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步地详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,如芯片侧壁可以是垂直的,如图3F所示,也可以是呈台阶状的,如图3M所示;在步骤十中,硅基支撑板800也可以部分去除,在硅基本体111的背面形成硅基加强层115,如图3N所示。凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (5)
1.一种包覆型芯片尺寸封装结构的封装方法,其特征在于,其包括如下步骤:
步骤一,取集成电路晶圆(100),其表面设有芯片电极(113)及相应电路布局,覆盖于晶圆(100)上表面的钝化层(210)于芯片电极(113)上方开设芯片表面钝化层开口(213)露出芯片电极(113)的正面;
步骤二,利用光刻工艺在晶圆(100)表面设置介电层Ⅰ(310)并开设介电层Ⅰ开口Ⅰ(311)和介电层Ⅰ开口Ⅱ(312),其中,介电层Ⅰ开口Ⅰ(311)露出芯片电极(113)的正面,介电层Ⅰ开口Ⅱ(312)沿划片道设置,并露出钝化层(210)的上表面;
步骤三,利用溅射或化学镀的方法在晶圆(100)表面沉积金属种子层,再利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在芯片电极(113)的上表面设置再布线金属层Ⅰ,并腐蚀去掉无效的金属种子层Ⅰ,形成凸块底部金属Ⅰ,该凸块底部金属Ⅰ由下而上依次包括金属种子层Ⅰ(410)、金属层Ⅰ(510),并在金属层Ⅰ(510)的最外层设有输入/输出端;
步骤四,再次利用光刻工艺在金属层Ⅰ(510)上覆盖介电层Ⅱ(320)并开设介电层Ⅱ开口Ⅰ(321)和介电层Ⅱ开口Ⅱ(322),其中,介电层Ⅱ开口Ⅰ(321)露出金属层Ⅰ(510)的输入/输出端,介电层Ⅱ开口Ⅱ(322)再次沿划片道设置,并与介电层Ⅰ开口Ⅱ(312)重合露出钝化层(210)的上表面;
步骤五,再次利用溅射或化学镀的方法在介电层Ⅱ(320)的表面沉积金属种子层Ⅱ,再次利用成熟的再布线工艺形成,具体为依次利用光刻工艺和电镀工艺在金属种子层Ⅱ的上表面设置再布线金属层Ⅱ,并腐蚀去掉无效的金属种子层Ⅱ,形成凸块底部金属Ⅱ,该凸块底部金属Ⅱ由下而上依次包括金属种子层Ⅱ(420)、金属层Ⅱ(520),并在金属层Ⅱ(520)的最外层设有输入/输出端;
步骤六,通过物理研磨的方法将晶圆(100)背面进行减薄工艺,其减薄厚度根据实际情况确定,并将减薄的晶圆(100)切成单颗,形成芯片单体;
步骤七,取一硅基支撑载体(710),并在硅基支撑载体(710)本体上黏贴剥离膜(730),将复数颗步骤六的芯片单体按照一定的排列顺序倒装至硅基支撑载体(710)上,芯片单体通过剥离膜(730)与硅基支撑载体(710)临时键合;
步骤八,在真空环境下,在硅基支撑载体(710)上通过注塑包封料或者贴包封膜的方式形成包封层(120),包封层(120)完全包覆芯片单体,形成包封层(120)保护的包封体,并将硅基支撑板(800)键合至包封体的背面;
步骤九,将硅基支撑载体(710)去除,同时去除剥离膜(730),露出芯片单体上表面的金属层Ⅱ(520),并对芯片单体的表面进行清洗,去除残留物;
步骤十,通过物理研磨或化学蚀刻的方式去除硅基支撑板(800);
步骤十一,在金属层Ⅱ(520)的输入/输出端处设置焊球(600);
步骤十二,将上述通过圆片级工艺完成的包覆型芯片尺寸封装结构进行切割形成侧壁由包封层Ⅱ(123)包覆的芯片单体。
2.根据权利要求1所述的包覆型芯片尺寸封装结构的封装方法,其特征在于, 所述介电层Ⅰ(310)的材质是低温固化的聚酰亚胺树脂,或者是高温固化的高分子材料。
3.根据权利要求1所述的包覆型芯片尺寸封装结构的封装方法,其特征在于,所述介电层Ⅱ(320)的材质是低温固化的聚酰亚胺树脂,或者是高温固化的高分子材料。
4.根据权利要求1所述的包覆型芯片尺寸封装结构的封装方法,其特征在于,所述剥离膜(730)为UV剥离膜或者热剥离膜。
5.根据权利要求1所述的包覆型芯片尺寸封装结构的封装方法,其特征在于,步骤六中,通过激光切割或者刀片物理切割的方式将减薄的晶圆(100)切成单颗。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710556249.4A CN107221517B (zh) | 2017-07-10 | 2017-07-10 | 一种包覆型芯片尺寸封装结构及其封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710556249.4A CN107221517B (zh) | 2017-07-10 | 2017-07-10 | 一种包覆型芯片尺寸封装结构及其封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107221517A CN107221517A (zh) | 2017-09-29 |
CN107221517B true CN107221517B (zh) | 2019-04-16 |
Family
ID=59952027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710556249.4A Active CN107221517B (zh) | 2017-07-10 | 2017-07-10 | 一种包覆型芯片尺寸封装结构及其封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107221517B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910287B2 (en) | 2018-02-28 | 2021-02-02 | Stmicroelectronics Pte Ltd | Semiconductor package with protected sidewall and method of forming the same |
CN111668115A (zh) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
CN111916359B (zh) * | 2019-05-09 | 2022-04-26 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
CN111933534B (zh) * | 2019-05-13 | 2023-01-24 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
CN111952190B (zh) * | 2019-05-16 | 2022-07-01 | 矽磐微电子(重庆)有限公司 | 半导体封装方法 |
CN116092929A (zh) * | 2023-02-16 | 2023-05-09 | 浙江萃锦半导体有限公司 | 一种双面晶圆化镀工艺 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104599985A (zh) * | 2014-12-11 | 2015-05-06 | 南通富士通微电子股份有限公司 | 全包封半导体芯片的制作方法 |
CN106531700A (zh) * | 2016-12-06 | 2017-03-22 | 江阴长电先进封装有限公司 | 一种芯片封装结构及其封装方法 |
CN206907755U (zh) * | 2017-07-10 | 2018-01-19 | 江阴长电先进封装有限公司 | 一种包覆型芯片尺寸封装结构 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101743467B1 (ko) * | 2015-08-24 | 2017-06-07 | 주식회사 에스에프에이반도체 | 팬-아웃형 웨이퍼 레벨 패키지의 제조 방법 |
-
2017
- 2017-07-10 CN CN201710556249.4A patent/CN107221517B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104599985A (zh) * | 2014-12-11 | 2015-05-06 | 南通富士通微电子股份有限公司 | 全包封半导体芯片的制作方法 |
CN106531700A (zh) * | 2016-12-06 | 2017-03-22 | 江阴长电先进封装有限公司 | 一种芯片封装结构及其封装方法 |
CN206907755U (zh) * | 2017-07-10 | 2018-01-19 | 江阴长电先进封装有限公司 | 一种包覆型芯片尺寸封装结构 |
Also Published As
Publication number | Publication date |
---|---|
CN107221517A (zh) | 2017-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107221517B (zh) | 一种包覆型芯片尺寸封装结构及其封装方法 | |
TWI324800B (en) | Method for manufacturing semiconductor device | |
US6876066B2 (en) | Packaged microelectronic devices and methods of forming same | |
CN106531700B (zh) | 一种芯片封装结构及其封装方法 | |
CN103515260A (zh) | 封装内封装及其形成方法 | |
CN101211874A (zh) | 超薄芯片尺寸封装结构及其方法 | |
JP2003347441A (ja) | 半導体素子、半導体装置、及び半導体素子の製造方法 | |
KR20130117332A (ko) | Cmos 이미지 센서에서의 유리 제거를 위한 방법 및 장치 | |
US20140004657A1 (en) | Method for producing chip stacks | |
CN102637713B (zh) | 一种含有金属微凸点的图像传感器封装方法 | |
CN106415817A (zh) | 用于晶片级封装的切割方法和具有适于晶片级封装的切割结构的半导体芯片 | |
TWI582919B (zh) | 無基板扇出型多晶片封裝構造及其製造方法 | |
JP3459234B2 (ja) | 半導体装置およびその製造方法 | |
WO2019127337A1 (zh) | 一种半导体芯片的封装结构及其封装方法 | |
JP2003204014A (ja) | 半導体ウエハ、バンプ付き半導体ウエハの製造方法、バンプ付き半導体チップ及びその製造方法、半導体装置、回路基板並びに電子機器 | |
US8569169B2 (en) | Bottom source power MOSFET with substrateless and manufacturing method thereof | |
CN103904093A (zh) | 晶圆级封装结构以及封装方法 | |
US20150140739A1 (en) | Discrete semiconductor device package and manufacturing method | |
US20130026615A1 (en) | Double-side exposed semiconductor device and its manufacturing method | |
CN110890285A (zh) | 一种芯片包覆封装结构及其封装方法 | |
CN101436553A (zh) | 芯片重新配置的封装结构中使用金属凸块的制造方法 | |
CN203967091U (zh) | 晶圆级封装结构 | |
CN110379721A (zh) | 扇出型封装方法及封装结构 | |
CN103247639A (zh) | 图像传感器圆片级封装方法及其结构 | |
CN104347542A (zh) | 五面包封的csp结构及制造工艺 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |