CN205303448U - 一种芯片封装结构 - Google Patents

一种芯片封装结构 Download PDF

Info

Publication number
CN205303448U
CN205303448U CN201521099897.4U CN201521099897U CN205303448U CN 205303448 U CN205303448 U CN 205303448U CN 201521099897 U CN201521099897 U CN 201521099897U CN 205303448 U CN205303448 U CN 205303448U
Authority
CN
China
Prior art keywords
chip
silica
based body
chip electrode
passivation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201521099897.4U
Other languages
English (en)
Inventor
张黎
赖志明
龙欣江
陈栋
陈锦辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangyin Changdian Advanced Packaging Co Ltd
Original Assignee
Jiangyin Changdian Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangyin Changdian Advanced Packaging Co Ltd filed Critical Jiangyin Changdian Advanced Packaging Co Ltd
Priority to CN201521099897.4U priority Critical patent/CN205303448U/zh
Application granted granted Critical
Publication of CN205303448U publication Critical patent/CN205303448U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本实用新型涉及一种芯片封装结构，属于半导体封装技术领域。其包括硅基本体(1)和芯片电极(11)，所述硅基本体(1)的正面设置钝化层(13)并开设钝化层开口(131)，所述芯片电极(11)由背面嵌入于硅基本体(1)的正面，所述钝化层开口(131)露出芯片电极(11)的正面，所述钝化层(13)的上表面设置介电层(4)并开设介电层开口(41)，所述介电层开口(41)露出芯片电极(11)的正面；所述芯片电极(11)的上表面设置凸块结构(5)；所述硅基本体(1)的四周和背面设置包封层(3)。本实用新型提供了一种侧壁绝缘保护、不易漏电或短路、提高可靠性、改善芯片贴装良率的芯片封装结构。

Description

一种芯片封装结构
技术领域
本实用新型涉及一种芯片封装结构，属于半导体封装技术领域。
背景技术
随着半导体硅工艺的发展，芯片的尺寸越来越小，芯片尺寸封装是主流，但部分封装结构并不采用BGA阵列结构，而是采用与传统QFN或LGA相类似地平面焊盘结构，但由于硅基体本身是半导体材料，其芯片四周的硅基本体1裸露在组装环境中，如图1所示，在贴装回流工艺中，电极区域11容易因为焊锡膏2印刷量过多而导致部分焊锡爬升到硅基本体1的侧壁裸露的硅上面，造成芯片漏电或短路；或者由于芯片间距比较近，加热或回流后，导致芯片的侧壁接触到了其他芯片的金属凸块而导致失效。
发明内容
本实用新型的目的在于克服上述不足，提供一种侧壁绝缘保护、不易漏电或短路、提高可靠性、改善芯片贴装良率的芯片封装结构。
本实用新型的目的是这样实现的：
本实用新型一种芯片封装结构，其包括硅基本体和芯片电极，所述硅基本体的正面设置钝化层并开设钝化层开口，所述芯片电极由背面嵌入于硅基本体的正面，所述钝化层开口露出芯片电极的正面，
所述钝化层的上表面设置介电层并开设介电层开口，所述介电层开口露出芯片电极的正面；
所述芯片电极的上表面设置凸块结构，所述凸块结构由下而上依次包括金属种子层、金属柱、焊料层；
所述硅基本体的四周和背面设置包封层。
进一步地，所述包封层为一体结构。
进一步地，所述包封层与介电层于两者的交界处密闭连接。
本实用新型有益效果是：
1、本实用新型的芯片封装结构侧壁设置绝缘保护，避免了因焊锡爬升到硅基本体的侧壁裸露的硅上面而造成的漏电或短路，提高可靠性，改善了芯片的贴装良率；
2、本实用新型的芯片封装结构的金属柱高度尺寸进一步减薄，且采用裸露设计，而硅基本体的四周和背面设置的包封层为一体结构，结构简洁，降低了设计难度，节约了制造成本。
附图说明
图1为现有芯片封装结构的剖面示意图；
图2为本实用新型一种芯片封装结构的实施例的示意图；
图3为图2的A-A剖面示意图；
图中：
硅基本体1
芯片电极11
钝化层13
钝化层开口131
包封层3
介电层4
介电层开口41
凸块结构5
金属种子层51
金属柱53
焊料层55。
具体实施方式
参见图2和图3，实施例
本实用新型一种芯片封装结构，芯片电极11至少为两个，图2中以两个芯片电极11示意，设置于芯片的正面，规则排布，如图2所示。其硅基本体1的正面设置钝化层13并开设钝化层开口131，所述芯片电极11由背面嵌入于硅基本体1的正面，所述钝化层开口131露出芯片电极11的正面。
所述钝化层13的上表面设置介电层4并开设介电层开口41，所述介电层开口41露出芯片电极11的正面；
所述芯片电极11的上表面设置凸块结构5，所述凸块结构5由下而上依次包括金属种子层51、金属柱53、焊料层55；金属柱53采用裸露设计，其高度尺寸尽可能地减薄。凸块结构5的高度只需略高于介电层4的高度即可。如图3所示，该简洁的封装结构，节约了制造成本，降低了设计难度。
所述硅基本体1的四周和背面设置由可以起到防水、防潮、防震、防尘、散热、绝缘等作用的包封料形成的包封层3。所述包封层3可以为一体结构。在包封层3与介电层4的交界处，包封层3与介电层4密闭连接。包封层3使硅基本体1的前后左右四个面及背面均得到物理和电气保护，防止外界干扰，以提高其可靠性；同时为侧壁提供绝缘保护，使其不易漏电或短路，改善了芯片贴装良率。
本实用新型一种芯片封装结构不限于上述实施例，任何本领域技术人员在不脱离本实用新型的精神和范围内，依据本实用新型的技术实质对以上实施例所作的任何修改、等同变化及修饰，均落入本实用新型权利要求所界定的保护范围内。

Claims (3)

1.一种芯片封装结构，其包括硅基本体(1)和芯片电极(11)，所述硅基本体(1)的正面设置钝化层(13)并开设钝化层开口(131)，所述芯片电极(11)由背面嵌入于硅基本体(1)的正面，所述钝化层开口(131)露出芯片电极(11)的正面，
其特征在于：所述钝化层(13)的上表面设置介电层(4)并开设介电层开口(41)，所述介电层开口(41)露出芯片电极(11)的正面；
所述芯片电极(11)的上表面设置凸块结构(5)，所述凸块结构(5)由下而上依次包括金属种子层(51)、金属柱(53)、焊料层(55)；
所述硅基本体(1)的四周和背面设置包封层(3)。
2.根据权利要求1所述的一种芯片封装结构，其特征在于：所述包封层(3)为一体结构。
3.根据权利要求1或2所述的一种芯片封装结构，其特征在于：所述包封层(3)与介电层(4)于两者的交界处密闭连接。
CN201521099897.4U 2015-12-28 2015-12-28 一种芯片封装结构 Active CN205303448U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201521099897.4U CN205303448U (zh) 2015-12-28 2015-12-28 一种芯片封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201521099897.4U CN205303448U (zh) 2015-12-28 2015-12-28 一种芯片封装结构

Publications (1)

Publication Number Publication Date
CN205303448U true CN205303448U (zh) 2016-06-08

Family

ID=56472764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201521099897.4U Active CN205303448U (zh) 2015-12-28 2015-12-28 一种芯片封装结构

Country Status (1)

Country Link
CN (1) CN205303448U (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531700A (zh) * 2016-12-06 2017-03-22 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
CN110890285A (zh) * 2019-12-11 2020-03-17 江阴长电先进封装有限公司 一种芯片包覆封装结构及其封装方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106531700A (zh) * 2016-12-06 2017-03-22 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
WO2018103117A1 (zh) * 2016-12-06 2018-06-14 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
CN106531700B (zh) * 2016-12-06 2019-05-28 江阴长电先进封装有限公司 一种芯片封装结构及其封装方法
US20190214324A1 (en) * 2016-12-06 2019-07-11 Jiangyin Changdian Advanced Packaging Co., Ltd Chip packaging structure, and packaging method thereof
EP3483928A4 (en) * 2016-12-06 2019-12-04 Jiangyin Changdian Advanced Packaging Co., Ltd. CHIP PACKING STRUCTURE AND PACKAGING METHOD THEREFOR
US10777477B2 (en) 2016-12-06 2020-09-15 Jiangyin Changdian Advanced Packaging Co., Ltd Chip packaging structure, and packaging method thereof
CN110890285A (zh) * 2019-12-11 2020-03-17 江阴长电先进封装有限公司 一种芯片包覆封装结构及其封装方法

Similar Documents

Publication Publication Date Title
US20210265244A1 (en) Electronic package structure
CN103137609B (zh) 带有电磁屏蔽结构的集成电路封装结构
US20110304036A1 (en) Semiconductor package with heat dissipation devices
TW200729444A (en) Semiconductor package structure and fabrication method thereof
JP2011129584A (ja) 半導体装置及び通信方法
CN203721707U (zh) 芯片封装结构
CN209544312U (zh) 一种集成电路抗静电装置
CN205303448U (zh) 一种芯片封装结构
CN102255034B (zh) 发光二极管封装结构
CN206225350U (zh) 一种芯片封装结构
CN203536467U (zh) 一种具有过渡基板的led器件
CN102368484A (zh) 一种多芯片集成电路封装结构
CN105489578A (zh) 叠层芯片封装结构
CN203055893U (zh) 一种再布线热增强型fcqfn封装器件
CN104064612A (zh) 太阳能供电的ic芯片
TWM556924U (zh) 可提高性能的高腳數封裝結構
CN204204830U (zh) 多腔体多层陶瓷双列直插式封装外壳
CN102856280B (zh) 焊盘和芯片
CN204516737U (zh) 一种新型半导体防脱落封装结构
CN101127332A (zh) 晶片上引脚球格阵列封装构造
CN204732390U (zh) 载板级半导体芯片嵌入式封装结构
JP6005805B2 (ja) 半導体装置及び電子装置
CN202796930U (zh) 用于mosfet芯片的封装体
TWI501379B (zh) 共用封膠體之封裝層疊構造
TW201438173A (zh) 導線架、封裝件及其製法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant